[AMDGPU][NPM] Port SIModeRegister to NPM

[optimisan]

No description provided.

[optimisan]

• [CodeGen][NPM] Port MIRFSDiscriminator to NPM #129511
• [CodeGen][NPM]RAGreedy: Put up include guard in the header #129510
• [CodeGen][NPM] Port ExpandPostRAPseudos to NPM #129509
• [AMDGPU][NPM] Port SIModeRegister to NPM #129014 👈 (View in Graphite)
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[llvmbot]

@llvm/pr-subscribers-backend-amdgpu

Author: Akshat Oke (optimisan)

Changes

---

Full diff: https://github.com/llvm/llvm-project/pull/129014.diff

6 Files Affected:

• (modified) llvm/lib/Target/AMDGPU/AMDGPU.h (+7-1)
• (modified) llvm/lib/Target/AMDGPU/AMDGPUPassRegistry.def (+1-1)
• (modified) llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp (+1-1)
• (modified) llvm/lib/Target/AMDGPU/SIModeRegister.cpp (+37-17)
• (modified) llvm/test/CodeGen/AMDGPU/mode-register-fptrunc.gfx11plus-fake16.mir (+1)
• (modified) llvm/test/CodeGen/AMDGPU/mode-register.mir (+1)

diff --git a/llvm/lib/Target/AMDGPU/AMDGPU.h b/llvm/lib/Target/AMDGPU/AMDGPU.h
index 428355a739628..09d090ed4ead1 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPU.h
+++ b/llvm/lib/Target/AMDGPU/AMDGPU.h
@@ -346,6 +346,12 @@ class AMDGPUAnnotateUniformValuesPass
   PreservedAnalyses run(Function &F, FunctionAnalysisManager &AM);
 };
 
+class SIModeRegisterPass : public PassInfoMixin<SIModeRegisterPass> {
+public:
+  SIModeRegisterPass() {}
+  PreservedAnalyses run(MachineFunction &F, MachineFunctionAnalysisManager &AM);
+};
+
 FunctionPass *createAMDGPUAnnotateUniformValuesLegacy();
 
 ModulePass *createAMDGPUPrintfRuntimeBinding();
@@ -413,7 +419,7 @@ extern char &SIAnnotateControlFlowLegacyPassID;
 void initializeSIMemoryLegalizerPass(PassRegistry&);
 extern char &SIMemoryLegalizerID;
 
-void initializeSIModeRegisterPass(PassRegistry&);
+void initializeSIModeRegisterLegacyPass(PassRegistry &);
 extern char &SIModeRegisterID;
 
 void initializeAMDGPUInsertDelayAluPass(PassRegistry &);
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUPassRegistry.def b/llvm/lib/Target/AMDGPU/AMDGPUPassRegistry.def
index e89d84c8a105f..7b07486c61b0f 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUPassRegistry.def
+++ b/llvm/lib/Target/AMDGPU/AMDGPUPassRegistry.def
@@ -111,6 +111,7 @@ MACHINE_FUNCTION_PASS("si-load-store-opt", SILoadStoreOptimizerPass())
 MACHINE_FUNCTION_PASS("si-lower-control-flow", SILowerControlFlowPass())
 MACHINE_FUNCTION_PASS("si-lower-sgpr-spills", SILowerSGPRSpillsPass())
 MACHINE_FUNCTION_PASS("si-lower-wwm-copies", SILowerWWMCopiesPass())
+MACHINE_FUNCTION_PASS("si-mode-register", SIModeRegisterPass())
 MACHINE_FUNCTION_PASS("si-opt-vgpr-liverange", SIOptimizeVGPRLiveRangePass())
 MACHINE_FUNCTION_PASS("si-optimize-exec-masking", SIOptimizeExecMaskingPass())
 MACHINE_FUNCTION_PASS("si-optimize-exec-masking-pre-ra", SIOptimizeExecMaskingPreRAPass())
@@ -131,7 +132,6 @@ DUMMY_MACHINE_FUNCTION_PASS("si-insert-hard-clauses", SIInsertHardClausesPass())
 DUMMY_MACHINE_FUNCTION_PASS("si-insert-waitcnts", SIInsertWaitcntsPass())
 DUMMY_MACHINE_FUNCTION_PASS("si-late-branch-lowering", SILateBranchLoweringPass())
 DUMMY_MACHINE_FUNCTION_PASS("si-memory-legalizer", SIMemoryLegalizerPass())
-DUMMY_MACHINE_FUNCTION_PASS("si-mode-register", SIModeRegisterPass())
 DUMMY_MACHINE_FUNCTION_PASS("si-pre-emit-peephole", SIPreEmitPeepholePass())
 // TODO: Move amdgpu-preload-kern-arg-prolog to MACHINE_FUNCTION_PASS since it
 // already exists.
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp b/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
index 828c1702ae07a..5414d7180a200 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
@@ -536,7 +536,7 @@ extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeAMDGPUTarget() {
   initializeAMDGPUInsertDelayAluPass(*PR);
   initializeSIInsertHardClausesPass(*PR);
   initializeSIInsertWaitcntsPass(*PR);
-  initializeSIModeRegisterPass(*PR);
+  initializeSIModeRegisterLegacyPass(*PR);
   initializeSIWholeQuadModeLegacyPass(*PR);
   initializeSILowerControlFlowLegacyPass(*PR);
   initializeSIPreEmitPeepholePass(*PR);
diff --git a/llvm/lib/Target/AMDGPU/SIModeRegister.cpp b/llvm/lib/Target/AMDGPU/SIModeRegister.cpp
index 99aea52c184d6..119de654140e6 100644
--- a/llvm/lib/Target/AMDGPU/SIModeRegister.cpp
+++ b/llvm/lib/Target/AMDGPU/SIModeRegister.cpp
@@ -18,6 +18,7 @@
 #include "MCTargetDesc/AMDGPUMCTargetDesc.h"
 #include "llvm/ADT/Statistic.h"
 #include "llvm/CodeGen/MachineFunctionPass.h"
+#include "llvm/CodeGen/MachinePassManager.h"
 #include <queue>
 
 #define DEBUG_TYPE "si-mode-register"
@@ -107,10 +108,8 @@ class BlockData {
 
 namespace {
 
-class SIModeRegister : public MachineFunctionPass {
+class SIModeRegister {
 public:
-  static char ID;
-
   std::vector<std::unique_ptr<BlockData>> BlockInfo;
   std::queue<MachineBasicBlock *> Phase2List;
 
@@ -125,15 +124,7 @@ class SIModeRegister : public MachineFunctionPass {
 
   bool Changed = false;
 
-public:
-  SIModeRegister() : MachineFunctionPass(ID) {}
-
-  bool runOnMachineFunction(MachineFunction &MF) override;
-
-  void getAnalysisUsage(AnalysisUsage &AU) const override {
-    AU.setPreservesCFG();
-    MachineFunctionPass::getAnalysisUsage(AU);
-  }
+  bool run(MachineFunction &MF);
 
   void processBlockPhase1(MachineBasicBlock &MBB, const SIInstrInfo *TII);
 
@@ -146,16 +137,32 @@ class SIModeRegister : public MachineFunctionPass {
   void insertSetreg(MachineBasicBlock &MBB, MachineInstr *I,
                     const SIInstrInfo *TII, Status InstrMode);
 };
+
+class SIModeRegisterLegacy : public MachineFunctionPass {
+public:
+  static char ID;
+
+  SIModeRegisterLegacy() : MachineFunctionPass(ID) {}
+
+  bool runOnMachineFunction(MachineFunction &MF) override;
+
+  void getAnalysisUsage(AnalysisUsage &AU) const override {
+    AU.setPreservesCFG();
+    MachineFunctionPass::getAnalysisUsage(AU);
+  }
+};
 } // End anonymous namespace.
 
-INITIALIZE_PASS(SIModeRegister, DEBUG_TYPE,
+INITIALIZE_PASS(SIModeRegisterLegacy, DEBUG_TYPE,
                 "Insert required mode register values", false, false)
 
-char SIModeRegister::ID = 0;
+char SIModeRegisterLegacy::ID = 0;
 
-char &llvm::SIModeRegisterID = SIModeRegister::ID;
+char &llvm::SIModeRegisterID = SIModeRegisterLegacy::ID;
 
-FunctionPass *llvm::createSIModeRegisterPass() { return new SIModeRegister(); }
+FunctionPass *llvm::createSIModeRegisterPass() {
+  return new SIModeRegisterLegacy();
+}
 
 // Determine the Mode register setting required for this instruction.
 // Instructions which don't use the Mode register return a null Status.
@@ -422,7 +429,20 @@ void SIModeRegister::processBlockPhase3(MachineBasicBlock &MBB,
   }
 }
 
-bool SIModeRegister::runOnMachineFunction(MachineFunction &MF) {
+bool SIModeRegisterLegacy::runOnMachineFunction(MachineFunction &MF) {
+  return SIModeRegister().run(MF);
+}
+
+PreservedAnalyses SIModeRegisterPass::run(MachineFunction &MF,
+                                          MachineFunctionAnalysisManager &AM) {
+  if (SIModeRegister().run(MF))
+    return PreservedAnalyses::none();
+  auto PA = getMachineFunctionPassPreservedAnalyses();
+  PA.preserveSet<CFGAnalyses>();
+  return PA;
+}
+
+bool SIModeRegister::run(MachineFunction &MF) {
   // Constrained FP intrinsics are used to support non-default rounding modes.
   // strictfp attribute is required to mark functions with strict FP semantics
   // having constrained FP intrinsics. This pass fixes up operations that uses
diff --git a/llvm/test/CodeGen/AMDGPU/mode-register-fptrunc.gfx11plus-fake16.mir b/llvm/test/CodeGen/AMDGPU/mode-register-fptrunc.gfx11plus-fake16.mir
index 8667934d70ff0..b3a4aa7b6c19a 100644
--- a/llvm/test/CodeGen/AMDGPU/mode-register-fptrunc.gfx11plus-fake16.mir
+++ b/llvm/test/CodeGen/AMDGPU/mode-register-fptrunc.gfx11plus-fake16.mir
@@ -1,5 +1,6 @@
 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
 # RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 -run-pass si-mode-register  %s -o - | FileCheck %s --check-prefixes=GFX11
+# RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 -passes si-mode-register  %s -o - | FileCheck %s --check-prefixes=GFX11
 
 ---
 name: ftrunc_tonearest
diff --git a/llvm/test/CodeGen/AMDGPU/mode-register.mir b/llvm/test/CodeGen/AMDGPU/mode-register.mir
index a918684056f65..aac6dcb01f3d9 100644
--- a/llvm/test/CodeGen/AMDGPU/mode-register.mir
+++ b/llvm/test/CodeGen/AMDGPU/mode-register.mir
@@ -1,4 +1,5 @@
 # RUN: llc -mtriple=amdgcn -mcpu=gfx900 -run-pass si-mode-register  %s -o - | FileCheck %s
+# RUN: llc -mtriple=amdgcn -mcpu=gfx900 -passes=si-mode-register  %s -o - | FileCheck %s
 
 ---
 # check that the mode is changed to rtz from default rtn for interp f16