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@enoskova-sc enoskova-sc commented Dec 10, 2024

Currently mir supports only one save and one restore point specification:

  savePoint:       '%bb.1'
  restorePoint:    '%bb.2'

This patch provide possibility to have multiple save and multiple restore points in mir:

  savePoints:
    - point:           '%bb.1'
  restorePoints:
    - point:           '%bb.2'

Shrink-Wrap points split Part 3.
RFC: https://discourse.llvm.org/t/shrink-wrap-save-restore-points-splitting/83581

Part 1: #117862
Part 2: #119355
Part 4: #119358
Part 5: #119359

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llvmbot commented Dec 10, 2024

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@llvm/pr-subscribers-backend-webassembly

Author: Elizaveta Noskova (enoskova-sc)

Changes

Currently mir supports only one save and one restore point specification:

  savePoint:       '%bb.1'
  restorePoint:    '%bb.2'

This patch provide possibility to have multiple save and multiple restore points in mir:

  savePoints:
    - point:           '%bb.1'
  restorePoints:
    - point:           '%bb.2'

Shrink-Wrap points split Part 3.

Part 1: #117862
Part 2: #119355


Patch is 276.31 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/119357.diff

340 Files Affected:

  • (modified) llvm/include/llvm/CodeGen/MIRYamlMapping.h (+32-7)
  • (modified) llvm/include/llvm/CodeGen/MachineDominators.h (+5)
  • (modified) llvm/lib/CodeGen/MIRParser/MIRParser.cpp (+29-14)
  • (modified) llvm/lib/CodeGen/MIRPrinter.cpp (+18-8)
  • (modified) llvm/lib/CodeGen/MachineDominators.cpp (+16)
  • (modified) llvm/lib/Target/RISCV/RISCVFrameLowering.cpp (+4)
  • (modified) llvm/test/CodeGen/AArch64/GlobalISel/store-merging-debug.mir (+2-2)
  • (modified) llvm/test/CodeGen/AArch64/aarch64-ldst-no-premature-sp-pop.mir (+2-2)
  • (modified) llvm/test/CodeGen/AArch64/aarch64-mov-debug-locs.mir (+2-2)
  • (modified) llvm/test/CodeGen/AArch64/aarch64st1.mir (+2-2)
  • (modified) llvm/test/CodeGen/AArch64/cfi-fixup-multi-block-prologue.mir (+2-2)
  • (modified) llvm/test/CodeGen/AArch64/cfi-fixup-multi-section.mir (+2-2)
  • (modified) llvm/test/CodeGen/AArch64/cfi-fixup.mir (+6-6)
  • (modified) llvm/test/CodeGen/AArch64/dont-shrink-wrap-stack-mayloadorstore.mir (+13-7)
  • (modified) llvm/test/CodeGen/AArch64/early-ifcvt-regclass-mismatch.mir (+2-2)
  • (modified) llvm/test/CodeGen/AArch64/emit_fneg_with_non_register_operand.mir (+2-2)
  • (modified) llvm/test/CodeGen/AArch64/irg-nomem.mir (+2-2)
  • (modified) llvm/test/CodeGen/AArch64/jump-table-duplicate.mir (+2-2)
  • (modified) llvm/test/CodeGen/AArch64/ldst-nopreidx-sp-redzone.mir (+6-6)
  • (modified) llvm/test/CodeGen/AArch64/live-debugvalues-sve.mir (+4-2)
  • (modified) llvm/test/CodeGen/AArch64/loop-sink-limit.mir (+2-2)
  • (modified) llvm/test/CodeGen/AArch64/loop-sink.mir (+16-16)
  • (modified) llvm/test/CodeGen/AArch64/machine-latecleanup-inlineasm.mir (+2-2)
  • (modified) llvm/test/CodeGen/AArch64/nested-iv-regalloc.mir (+2-2)
  • (modified) llvm/test/CodeGen/AArch64/regalloc-last-chance-recolor-with-split.mir (+2-2)
  • (modified) llvm/test/CodeGen/AArch64/shrinkwrap-split-restore-point.mir (+2-2)
  • (modified) llvm/test/CodeGen/AArch64/sink-and-fold-drop-dbg.mir (+2-2)
  • (modified) llvm/test/CodeGen/AArch64/sink-and-fold-illegal-shift.mir (+2-2)
  • (modified) llvm/test/CodeGen/AArch64/sink-and-fold-preserve-debugloc.mir (+4-4)
  • (modified) llvm/test/CodeGen/AArch64/split-deadloop.mir (+2-2)
  • (modified) llvm/test/CodeGen/AArch64/stack-probing-last-in-block.mir (+2-2)
  • (modified) llvm/test/CodeGen/AArch64/tail-dup-redundant-phi.mir (+2-2)
  • (modified) llvm/test/CodeGen/AArch64/taildup-addrtaken.mir (+2-2)
  • (modified) llvm/test/CodeGen/AArch64/wineh-frame-predecrement.mir (+2-2)
  • (modified) llvm/test/CodeGen/AArch64/wineh-frame-scavenge.mir (+2-2)
  • (modified) llvm/test/CodeGen/AArch64/wineh-frame1.mir (+2-2)
  • (modified) llvm/test/CodeGen/AArch64/wineh-frame2.mir (+2-2)
  • (modified) llvm/test/CodeGen/AArch64/wineh-frame3.mir (+2-2)
  • (modified) llvm/test/CodeGen/AArch64/wineh-frame4.mir (+2-2)
  • (modified) llvm/test/CodeGen/AArch64/wineh-frame5.mir (+2-2)
  • (modified) llvm/test/CodeGen/AArch64/wineh-frame6.mir (+2-2)
  • (modified) llvm/test/CodeGen/AArch64/wineh-frame7.mir (+2-2)
  • (modified) llvm/test/CodeGen/AArch64/wineh-frame8.mir (+2-2)
  • (modified) llvm/test/CodeGen/AArch64/wineh-save-lrpair1.mir (+2-2)
  • (modified) llvm/test/CodeGen/AArch64/wineh-save-lrpair2.mir (+2-2)
  • (modified) llvm/test/CodeGen/AArch64/wineh-save-lrpair3.mir (+2-2)
  • (modified) llvm/test/CodeGen/AArch64/wineh2.mir (+2-2)
  • (modified) llvm/test/CodeGen/AArch64/wineh3.mir (+2-2)
  • (modified) llvm/test/CodeGen/AArch64/wineh4.mir (+2-2)
  • (modified) llvm/test/CodeGen/AArch64/wineh5.mir (+2-2)
  • (modified) llvm/test/CodeGen/AArch64/wineh6.mir (+2-2)
  • (modified) llvm/test/CodeGen/AArch64/wineh7.mir (+2-2)
  • (modified) llvm/test/CodeGen/AArch64/wineh8.mir (+2-2)
  • (modified) llvm/test/CodeGen/AArch64/wineh9.mir (+2-2)
  • (modified) llvm/test/CodeGen/AArch64/wineh_shrinkwrap.mir (+2-2)
  • (modified) llvm/test/CodeGen/AMDGPU/memory-legalizer-multiple-mem-operands-nontemporal-1.mir (+2-2)
  • (modified) llvm/test/CodeGen/AMDGPU/memory-legalizer-multiple-mem-operands-nontemporal-2.mir (+2-2)
  • (modified) llvm/test/CodeGen/ARM/cmse-vlldm-no-reorder.mir (+2-2)
  • (modified) llvm/test/CodeGen/ARM/codesize-ifcvt.mir (+6-6)
  • (modified) llvm/test/CodeGen/ARM/constant-island-movwt.mir (+2-2)
  • (modified) llvm/test/CodeGen/ARM/constant-islands-cfg.mir (+2-2)
  • (modified) llvm/test/CodeGen/ARM/constant-islands-split-IT.mir (+2-2)
  • (modified) llvm/test/CodeGen/ARM/execute-only-save-cpsr.mir (+8-8)
  • (modified) llvm/test/CodeGen/ARM/fp16-litpool2-arm.mir (+2-2)
  • (modified) llvm/test/CodeGen/ARM/fp16-litpool3-arm.mir (+2-2)
  • (modified) llvm/test/CodeGen/ARM/inlineasmbr-if-cvt.mir (+2-2)
  • (modified) llvm/test/CodeGen/ARM/invalidated-save-point.ll (+2-2)
  • (modified) llvm/test/CodeGen/ARM/jump-table-dbg-value.mir (+2-2)
  • (modified) llvm/test/CodeGen/ARM/stack_frame_offset.mir (+6-6)
  • (modified) llvm/test/CodeGen/Hexagon/cext-opt-block-addr.mir (+4-4)
  • (modified) llvm/test/CodeGen/Hexagon/early-if-predicator.mir (+2-2)
  • (modified) llvm/test/CodeGen/Hexagon/machine-sink-float-usr.mir (+4-4)
  • (modified) llvm/test/CodeGen/Hexagon/pipeliner/swp-phi-start.mir (+2-2)
  • (modified) llvm/test/CodeGen/MIR/ARM/thumb2-sub-sp-t3.mir (+2-2)
  • (modified) llvm/test/CodeGen/MIR/Generic/frame-info.mir (+2-2)
  • (modified) llvm/test/CodeGen/MIR/Hexagon/addrmode-opt-nonreaching.mir (+2-2)
  • (modified) llvm/test/CodeGen/MIR/RISCV/machine-function-info.mir (+2-2)
  • (modified) llvm/test/CodeGen/MIR/X86/branch-folder-with-label.mir (+6-6)
  • (modified) llvm/test/CodeGen/MIR/X86/diexpr-win32.mir (+4-4)
  • (modified) llvm/test/CodeGen/MIR/X86/fake-use-tailcall.mir (+2-2)
  • (modified) llvm/test/CodeGen/MIR/X86/frame-info-save-restore-points.mir (+8-4)
  • (modified) llvm/test/CodeGen/MIR/X86/inline-asm-rm-exhaustion.mir (+6-6)
  • (modified) llvm/test/CodeGen/Mips/delay-slot-filler-bundled-insts-def-use.mir (+2-2)
  • (modified) llvm/test/CodeGen/Mips/delay-slot-filler-bundled-insts.mir (+2-2)
  • (modified) llvm/test/CodeGen/Mips/indirect-jump-hazard/guards-verify-call.mir (+2-2)
  • (modified) llvm/test/CodeGen/Mips/indirect-jump-hazard/guards-verify-tailcall.mir (+2-2)
  • (modified) llvm/test/CodeGen/Mips/instverify/dext-pos.mir (+2-2)
  • (modified) llvm/test/CodeGen/Mips/instverify/dext-size.mir (+2-2)
  • (modified) llvm/test/CodeGen/Mips/instverify/dextm-pos-size.mir (+2-2)
  • (modified) llvm/test/CodeGen/Mips/instverify/dextm-pos.mir (+2-2)
  • (modified) llvm/test/CodeGen/Mips/instverify/dextm-size.mir (+2-2)
  • (modified) llvm/test/CodeGen/Mips/instverify/dextu-pos-size.mir (+2-2)
  • (modified) llvm/test/CodeGen/Mips/instverify/dextu-pos.mir (+2-2)
  • (modified) llvm/test/CodeGen/Mips/instverify/dextu-size-valid.mir (+2-2)
  • (modified) llvm/test/CodeGen/Mips/instverify/dextu-size.mir (+2-2)
  • (modified) llvm/test/CodeGen/Mips/instverify/dins-pos-size.mir (+2-2)
  • (modified) llvm/test/CodeGen/Mips/instverify/dins-pos.mir (+2-2)
  • (modified) llvm/test/CodeGen/Mips/instverify/dins-size.mir (+2-2)
  • (modified) llvm/test/CodeGen/Mips/instverify/dinsm-pos-size.mir (+2-2)
  • (modified) llvm/test/CodeGen/Mips/instverify/dinsm-pos.mir (+2-2)
  • (modified) llvm/test/CodeGen/Mips/instverify/dinsm-size.mir (+2-2)
  • (modified) llvm/test/CodeGen/Mips/instverify/dinsu-pos-size.mir (+2-2)
  • (modified) llvm/test/CodeGen/Mips/instverify/dinsu-pos.mir (+2-2)
  • (modified) llvm/test/CodeGen/Mips/instverify/dinsu-size.mir (+2-2)
  • (modified) llvm/test/CodeGen/Mips/instverify/ext-pos-size.mir (+2-2)
  • (modified) llvm/test/CodeGen/Mips/instverify/ext-pos.mir (+2-2)
  • (modified) llvm/test/CodeGen/Mips/instverify/ext-size.mir (+2-2)
  • (modified) llvm/test/CodeGen/Mips/instverify/ins-pos-size.mir (+2-2)
  • (modified) llvm/test/CodeGen/Mips/instverify/ins-pos.mir (+2-2)
  • (modified) llvm/test/CodeGen/Mips/instverify/ins-size.mir (+2-2)
  • (modified) llvm/test/CodeGen/Mips/longbranch/branch-limits-fp-micromips.mir (+4-4)
  • (modified) llvm/test/CodeGen/Mips/longbranch/branch-limits-fp-micromipsr6.mir (+4-4)
  • (modified) llvm/test/CodeGen/Mips/longbranch/branch-limits-fp-mips.mir (+4-4)
  • (modified) llvm/test/CodeGen/Mips/longbranch/branch-limits-fp-mipsr6.mir (+4-4)
  • (modified) llvm/test/CodeGen/Mips/longbranch/branch-limits-int-microMIPS.mir (+16-16)
  • (modified) llvm/test/CodeGen/Mips/longbranch/branch-limits-int-micromipsr6.mir (+24-24)
  • (modified) llvm/test/CodeGen/Mips/longbranch/branch-limits-int-mips64.mir (+12-12)
  • (modified) llvm/test/CodeGen/Mips/longbranch/branch-limits-int-mips64r6.mir (+24-24)
  • (modified) llvm/test/CodeGen/Mips/longbranch/branch-limits-int-mipsr6.mir (+24-24)
  • (modified) llvm/test/CodeGen/Mips/longbranch/branch-limits-int.mir (+12-12)
  • (modified) llvm/test/CodeGen/Mips/longbranch/branch-limits-msa.mir (+20-20)
  • (modified) llvm/test/CodeGen/Mips/micromips-eva.mir (+4-4)
  • (modified) llvm/test/CodeGen/Mips/micromips-short-delay-slot.mir (+2-2)
  • (modified) llvm/test/CodeGen/Mips/micromips-sizereduction/micromips-lwp-swp.mir (+8-8)
  • (modified) llvm/test/CodeGen/Mips/micromips-sizereduction/micromips-no-lwp-swp.mir (+8-8)
  • (modified) llvm/test/CodeGen/Mips/mirparser/target-flags-pic-mxgot-tls.mir (+2-2)
  • (modified) llvm/test/CodeGen/Mips/mirparser/target-flags-pic-o32.mir (+2-2)
  • (modified) llvm/test/CodeGen/Mips/mirparser/target-flags-pic.mir (+2-2)
  • (modified) llvm/test/CodeGen/Mips/mirparser/target-flags-static-tls.mir (+2-2)
  • (modified) llvm/test/CodeGen/Mips/msa/emergency-spill.mir (+2-2)
  • (modified) llvm/test/CodeGen/Mips/sll-micromips-r6-encoding.mir (+2-2)
  • (modified) llvm/test/CodeGen/Mips/unaligned-memops-mapping.mir (+4-4)
  • (modified) llvm/test/CodeGen/NVPTX/proxy-reg-erasure.mir (+2-2)
  • (modified) llvm/test/CodeGen/PowerPC/DisableHoistingDueToBlockHotnessNoProfileData.mir (+2-2)
  • (modified) llvm/test/CodeGen/PowerPC/DisableHoistingDueToBlockHotnessProfileData.mir (+2-2)
  • (modified) llvm/test/CodeGen/PowerPC/NoCRFieldRedefWhenSpillingCRBIT.mir (+2-2)
  • (modified) llvm/test/CodeGen/PowerPC/alignlongjumptest.mir (+2-2)
  • (modified) llvm/test/CodeGen/PowerPC/block-placement-1.mir (+4-4)
  • (modified) llvm/test/CodeGen/PowerPC/block-placement.mir (+2-2)
  • (modified) llvm/test/CodeGen/PowerPC/collapse-rotates.mir (+2-2)
  • (modified) llvm/test/CodeGen/PowerPC/convert-rr-to-ri-instrs-R0-special-handling.mir (+14-14)
  • (modified) llvm/test/CodeGen/PowerPC/convert-rr-to-ri-instrs-out-of-range.mir (+40-40)
  • (modified) llvm/test/CodeGen/PowerPC/convert-rr-to-ri-instrs.mir (+178-178)
  • (modified) llvm/test/CodeGen/PowerPC/ctrloop-do-not-duplicate-mi.mir (+2-2)
  • (modified) llvm/test/CodeGen/PowerPC/livevars-crash2.mir (+2-2)
  • (modified) llvm/test/CodeGen/PowerPC/peephole-phi-acc.mir (+8-8)
  • (modified) llvm/test/CodeGen/PowerPC/peephole-replaceInstr-after-eliminate-extsw.mir (+2-2)
  • (modified) llvm/test/CodeGen/PowerPC/phi-eliminate.mir (+2-2)
  • (modified) llvm/test/CodeGen/PowerPC/remove-copy-crunsetcrbit.mir (+2-2)
  • (modified) llvm/test/CodeGen/PowerPC/remove-implicit-use.mir (+2-2)
  • (modified) llvm/test/CodeGen/PowerPC/remove-redundant-li-skip-imp-kill.mir (+2-2)
  • (modified) llvm/test/CodeGen/PowerPC/remove-self-copies.mir (+2-2)
  • (modified) llvm/test/CodeGen/PowerPC/rlwinm_rldicl_to_andi.mir (+12-12)
  • (modified) llvm/test/CodeGen/PowerPC/schedule-addi-load.mir (+2-2)
  • (modified) llvm/test/CodeGen/PowerPC/setcr_bc.mir (+2-2)
  • (modified) llvm/test/CodeGen/PowerPC/setcr_bc2.mir (+2-2)
  • (modified) llvm/test/CodeGen/PowerPC/setcr_bc3.mir (+2-2)
  • (modified) llvm/test/CodeGen/PowerPC/tls_get_addr_fence1.mir (+2-2)
  • (modified) llvm/test/CodeGen/PowerPC/tls_get_addr_fence2.mir (+2-2)
  • (modified) llvm/test/CodeGen/PowerPC/two-address-crash.mir (+2-2)
  • (modified) llvm/test/CodeGen/RISCV/live-sp.mir (+2-2)
  • (modified) llvm/test/CodeGen/RISCV/pr53662.mir (+4-2)
  • (modified) llvm/test/CodeGen/RISCV/rvv/addi-rvv-stack-object.mir (+2-2)
  • (modified) llvm/test/CodeGen/RISCV/rvv/emergency-slot.mir (+2-2)
  • (modified) llvm/test/CodeGen/RISCV/rvv/large-rvv-stack-size.mir (+2-2)
  • (modified) llvm/test/CodeGen/RISCV/rvv/rvv-stack-align.mir (+6-6)
  • (modified) llvm/test/CodeGen/RISCV/rvv/undef-earlyclobber-chain.mir (+2-2)
  • (modified) llvm/test/CodeGen/RISCV/rvv/wrong-stack-offset-for-rvv-object.mir (+2-2)
  • (modified) llvm/test/CodeGen/RISCV/stack-slot-coloring.mir (+2-2)
  • (modified) llvm/test/CodeGen/RISCV/zcmp-prolog-epilog-crash.mir (+4-2)
  • (modified) llvm/test/CodeGen/Thumb2/LowOverheadLoops/add_reduce.mir (+2-2)
  • (modified) llvm/test/CodeGen/Thumb2/LowOverheadLoops/begin-vpt-without-inst.mir (+2-2)
  • (modified) llvm/test/CodeGen/Thumb2/LowOverheadLoops/biquad-cascade-default.mir (+2-2)
  • (modified) llvm/test/CodeGen/Thumb2/LowOverheadLoops/biquad-cascade-optsize-strd-lr.mir (+2-2)
  • (modified) llvm/test/CodeGen/Thumb2/LowOverheadLoops/biquad-cascade-optsize.mir (+2-2)
  • (modified) llvm/test/CodeGen/Thumb2/LowOverheadLoops/cond-mov.mir (+2-2)
  • (modified) llvm/test/CodeGen/Thumb2/LowOverheadLoops/disjoint-vcmp.mir (+2-2)
  • (modified) llvm/test/CodeGen/Thumb2/LowOverheadLoops/dont-ignore-vctp.mir (+2-2)
  • (modified) llvm/test/CodeGen/Thumb2/LowOverheadLoops/dont-remove-loop-update.mir (+2-2)
  • (modified) llvm/test/CodeGen/Thumb2/LowOverheadLoops/emptyblock.mir (+2-2)
  • (modified) llvm/test/CodeGen/Thumb2/LowOverheadLoops/end-positive-offset.mir (+2-2)
  • (modified) llvm/test/CodeGen/Thumb2/LowOverheadLoops/extract-element.mir (+2-2)
  • (modified) llvm/test/CodeGen/Thumb2/LowOverheadLoops/incorrect-sub-16.mir (+2-2)
  • (modified) llvm/test/CodeGen/Thumb2/LowOverheadLoops/incorrect-sub-32.mir (+2-2)
  • (modified) llvm/test/CodeGen/Thumb2/LowOverheadLoops/incorrect-sub-8.mir (+2-2)
  • (modified) llvm/test/CodeGen/Thumb2/LowOverheadLoops/inloop-vpnot-1.mir (+2-2)
  • (modified) llvm/test/CodeGen/Thumb2/LowOverheadLoops/inloop-vpnot-2.mir (+2-2)
  • (modified) llvm/test/CodeGen/Thumb2/LowOverheadLoops/inloop-vpnot-3.mir (+2-2)
  • (modified) llvm/test/CodeGen/Thumb2/LowOverheadLoops/inloop-vpsel-1.mir (+2-2)
  • (modified) llvm/test/CodeGen/Thumb2/LowOverheadLoops/inloop-vpsel-2.mir (+2-2)
  • (modified) llvm/test/CodeGen/Thumb2/LowOverheadLoops/it-block-chain-store.mir (+4-4)
  • (modified) llvm/test/CodeGen/Thumb2/LowOverheadLoops/it-block-chain.mir (+2-2)
  • (modified) llvm/test/CodeGen/Thumb2/LowOverheadLoops/it-block-itercount.mir (+2-2)
  • (modified) llvm/test/CodeGen/Thumb2/LowOverheadLoops/it-block-random.mir (+2-2)
  • (modified) llvm/test/CodeGen/Thumb2/LowOverheadLoops/loop-dec-copy-chain.mir (+2-2)
  • (modified) llvm/test/CodeGen/Thumb2/LowOverheadLoops/loop-dec-copy-prev-iteration.mir (+2-2)
  • (modified) llvm/test/CodeGen/Thumb2/LowOverheadLoops/loop-dec-liveout.mir (+2-2)
  • (modified) llvm/test/CodeGen/Thumb2/LowOverheadLoops/lstp-insertion-position.mir (+4-4)
  • (modified) llvm/test/CodeGen/Thumb2/LowOverheadLoops/massive.mir (+2-2)
  • (modified) llvm/test/CodeGen/Thumb2/LowOverheadLoops/matrix-debug.mir (+2-2)
  • (modified) llvm/test/CodeGen/Thumb2/LowOverheadLoops/matrix.mir (+2-2)
  • (modified) llvm/test/CodeGen/Thumb2/LowOverheadLoops/mov-after-dls.mir (+2-2)
  • (modified) llvm/test/CodeGen/Thumb2/LowOverheadLoops/mov-after-dlstp.mir (+2-2)
  • (modified) llvm/test/CodeGen/Thumb2/LowOverheadLoops/mov-lr-terminator.mir (+2-2)
  • (modified) llvm/test/CodeGen/Thumb2/LowOverheadLoops/move-def-before-start.mir (+2-2)
  • (modified) llvm/test/CodeGen/Thumb2/LowOverheadLoops/move-start-after-def.mir (+2-2)
  • (modified) llvm/test/CodeGen/Thumb2/LowOverheadLoops/multiblock-massive.mir (+2-2)
  • (modified) llvm/test/CodeGen/Thumb2/LowOverheadLoops/multiple-do-loops.mir (+6-6)
  • (modified) llvm/test/CodeGen/Thumb2/LowOverheadLoops/mve-reduct-livein-arg.mir (+2-2)
  • (modified) llvm/test/CodeGen/Thumb2/LowOverheadLoops/no-dec-cbnz.mir (+2-2)
  • (modified) llvm/test/CodeGen/Thumb2/LowOverheadLoops/no-dec-reorder.mir (+2-2)
  • (modified) llvm/test/CodeGen/Thumb2/LowOverheadLoops/no-dec.mir (+2-2)
  • (modified) llvm/test/CodeGen/Thumb2/LowOverheadLoops/no-vpsel-liveout.mir (+2-2)
  • (modified) llvm/test/CodeGen/Thumb2/LowOverheadLoops/non-masked-load.mir (+2-2)
  • (modified) llvm/test/CodeGen/Thumb2/LowOverheadLoops/non-masked-store.mir (+2-2)
  • (modified) llvm/test/CodeGen/Thumb2/LowOverheadLoops/out-of-range-cbz.mir (+2-2)
  • (modified) llvm/test/CodeGen/Thumb2/LowOverheadLoops/remove-elem-moves.mir (+2-2)
  • (modified) llvm/test/CodeGen/Thumb2/LowOverheadLoops/revert-after-call.mir (+2-2)
  • (modified) llvm/test/CodeGen/Thumb2/LowOverheadLoops/revert-after-read.mir (+2-2)
  • (modified) llvm/test/CodeGen/Thumb2/LowOverheadLoops/revert-after-write.mir (+2-2)
  • (modified) llvm/test/CodeGen/Thumb2/LowOverheadLoops/revert-non-header.mir (+2-2)
  • (modified) llvm/test/CodeGen/Thumb2/LowOverheadLoops/revert-non-loop.mir (+2-2)
  • (modified) llvm/test/CodeGen/Thumb2/LowOverheadLoops/revert-while.mir (+2-2)
  • (modified) llvm/test/CodeGen/Thumb2/LowOverheadLoops/safe-def-no-mov.mir (+2-2)
  • (modified) llvm/test/CodeGen/Thumb2/LowOverheadLoops/safe-retaining.mir (+1-1)
  • (modified) llvm/test/CodeGen/Thumb2/LowOverheadLoops/size-limit.mir (+2-2)
  • (modified) llvm/test/CodeGen/Thumb2/LowOverheadLoops/skip-debug.mir (+2-2)
  • (modified) llvm/test/CodeGen/Thumb2/LowOverheadLoops/skip-vpt-debug.mir (+2-2)
  • (modified) llvm/test/CodeGen/Thumb2/LowOverheadLoops/switch.mir (+2-2)
  • (modified) llvm/test/CodeGen/Thumb2/LowOverheadLoops/unrolled-and-vector.mir (+2-2)
  • (modified) llvm/test/CodeGen/Thumb2/LowOverheadLoops/unsafe-cpsr-loop-def.mir (+2-2)
  • (modified) llvm/test/CodeGen/Thumb2/LowOverheadLoops/unsafe-cpsr-loop-use.mir (+2-2)
  • (modified) llvm/test/CodeGen/Thumb2/LowOverheadLoops/unsafe-use-after.mir (+2-2)
  • (modified) llvm/test/CodeGen/Thumb2/LowOverheadLoops/vaddv.mir (+38-38)
  • (modified) llvm/test/CodeGen/Thumb2/LowOverheadLoops/vctp-add-operand-liveout.mir (+2-2)
  • (modified) llvm/test/CodeGen/Thumb2/LowOverheadLoops/vctp-in-vpt-2.mir (+2-2)
  • (modified) llvm/test/CodeGen/Thumb2/LowOverheadLoops/vctp-in-vpt.mir (+8-8)
  • (modified) llvm/test/CodeGen/Thumb2/LowOverheadLoops/vctp-subi3.mir (+2-2)
  • (modified) llvm/test/CodeGen/Thumb2/LowOverheadLoops/vctp-subri.mir (+2-2)
  • (modified) llvm/test/CodeGen/Thumb2/LowOverheadLoops/vctp-subri12.mir (+2-2)
  • (modified) llvm/test/CodeGen/Thumb2/LowOverheadLoops/vctp16-reduce.mir (+2-2)
  • (modified) llvm/test/CodeGen/Thumb2/LowOverheadLoops/vmaxmin_vpred_r.mir (+2-2)
  • (modified) llvm/test/CodeGen/Thumb2/LowOverheadLoops/vmldava_in_vpt.mir (+2-2)
  • (modified) llvm/test/CodeGen/Thumb2/LowOverheadLoops/vpt-block-debug.mir (+2-2)
  • (modified) llvm/test/CodeGen/Thumb2/LowOverheadLoops/vpt-blocks.mir (+14-14)
  • (modified) llvm/test/CodeGen/Thumb2/LowOverheadLoops/while-negative-offset.mir (+2-2)
  • (modified) llvm/test/CodeGen/Thumb2/LowOverheadLoops/while.mir (+2-2)
  • (modified) llvm/test/CodeGen/Thumb2/LowOverheadLoops/wlstp.mir (+6-6)
  • (modified) llvm/test/CodeGen/Thumb2/LowOverheadLoops/wrong-liveout-lsr-shift.mir (+2-2)
  • (modified) llvm/test/CodeGen/Thumb2/LowOverheadLoops/wrong-vctp-opcode-liveout.mir (+2-2)
  • (modified) llvm/test/CodeGen/Thumb2/LowOverheadLoops/wrong-vctp-operand-liveout.mir (+2-2)
  • (modified) llvm/test/CodeGen/Thumb2/bti-pac-replace-1.mir (+2-2)
  • (modified) llvm/test/CodeGen/Thumb2/ifcvt-neon-deprecated.mir (+2-2)
  • (modified) llvm/test/CodeGen/Thumb2/mve-vpt-2-blocks-1-pred.mir (+2-2)
  • (modified) llvm/test/CodeGen/Thumb2/mve-vpt-2-blocks-2-preds.mir (+2-2)
  • (modified) llvm/test/CodeGen/Thumb2/mve-vpt-2-blocks-ctrl-flow.mir (+2-2)
  • (modified) llvm/test/CodeGen/Thumb2/mve-vpt-2-blocks-non-consecutive-ins.mir (+2-2)
  • (modified) llvm/test/CodeGen/Thumb2/mve-vpt-2-blocks.mir (+2-2)
  • (modified) llvm/test/CodeGen/Thumb2/mve-vpt-3-blocks-kill-vpr.mir (+2-2)
  • (modified) llvm/test/CodeGen/Thumb2/mve-vpt-block-1-ins.mir (+2-2)
  • (modified) llvm/test/CodeGen/Thumb2/mve-vpt-block-2-ins.mir (+2-2)
  • (modified) llvm/test/CodeGen/Thumb2/mve-vpt-block-4-ins.mir (+2-2)
  • (modified) llvm/test/CodeGen/Thumb2/mve-vpt-block-elses.mir (+2-2)
  • (modified) llvm/test/CodeGen/Thumb2/mve-vpt-block-fold-vcmp.mir (+2-2)
  • (modified) llvm/test/CodeGen/Thumb2/mve-vpt-block-optnone.mir (+2-2)
  • (modified) llvm/test/CodeGen/Thumb2/mve-vpt-preuse.mir (+2-2)
  • (modified) llvm/test/CodeGen/Thumb2/pipeliner-preserve-ties.mir (+2-2)
  • (modified) llvm/test/CodeGen/VE/Scalar/fold-imm-addsl.mir (+8-8)
  • (modified) llvm/test/CodeGen/VE/Scalar/fold-imm-cmpsl.mir (+4-4)
diff --git a/llvm/include/llvm/CodeGen/MIRYamlMapping.h b/llvm/include/llvm/CodeGen/MIRYamlMapping.h
index 09a6ca936fe1f4..be8a8e593ef922 100644
--- a/llvm/include/llvm/CodeGen/MIRYamlMapping.h
+++ b/llvm/include/llvm/CodeGen/MIRYamlMapping.h
@@ -610,6 +610,20 @@ LLVM_YAML_IS_SEQUENCE_VECTOR(llvm::yaml::MachineJumpTable::Entry)
 namespace llvm {
 namespace yaml {
 
+struct SRPEntry {
+  StringValue Point;
+
+  bool operator==(const SRPEntry &Other) const { return Point == Other.Point; }
+};
+
+using SaveRestorePoints = std::vector<SRPEntry>;
+
+template <> struct MappingTraits<SRPEntry> {
+  static void mapping(IO &YamlIO, SRPEntry &Entry) {
+    YamlIO.mapRequired("point", Entry.Point);
+  }
+};
+
 template <> struct MappingTraits<MachineJumpTable> {
   static void mapping(IO &YamlIO, MachineJumpTable &JT) {
     YamlIO.mapRequired("kind", JT.Kind);
@@ -618,6 +632,14 @@ template <> struct MappingTraits<MachineJumpTable> {
   }
 };
 
+} // namespace yaml
+} // namespace llvm
+
+LLVM_YAML_IS_SEQUENCE_VECTOR(llvm::yaml::SRPEntry)
+
+namespace llvm {
+namespace yaml {
+
 /// Serializable representation of MachineFrameInfo.
 ///
 /// Doesn't serialize attributes like 'StackAlignment', 'IsStackRealignable' and
@@ -645,8 +667,8 @@ struct MachineFrameInfo {
   bool HasTailCall = false;
   bool IsCalleeSavedInfoValid = false;
   unsigned LocalFrameSize = 0;
-  StringValue SavePoint;
-  StringValue RestorePoint;
+  SaveRestorePoints SavePoints;
+  SaveRestorePoints RestorePoints;
 
   bool operator==(const MachineFrameInfo &Other) const {
     return IsFrameAddressTaken == Other.IsFrameAddressTaken &&
@@ -667,7 +689,8 @@ struct MachineFrameInfo {
            HasMustTailInVarArgFunc == Other.HasMustTailInVarArgFunc &&
            HasTailCall == Other.HasTailCall &&
            LocalFrameSize == Other.LocalFrameSize &&
-           SavePoint == Other.SavePoint && RestorePoint == Other.RestorePoint &&
+           SavePoints == Other.SavePoints &&
+           RestorePoints == Other.RestorePoints &&
            IsCalleeSavedInfoValid == Other.IsCalleeSavedInfoValid;
   }
 };
@@ -699,10 +722,12 @@ template <> struct MappingTraits<MachineFrameInfo> {
     YamlIO.mapOptional("isCalleeSavedInfoValid", MFI.IsCalleeSavedInfoValid,
                        false);
     YamlIO.mapOptional("localFrameSize", MFI.LocalFrameSize, (unsigned)0);
-    YamlIO.mapOptional("savePoint", MFI.SavePoint,
-                       StringValue()); // Don't print it out when it's empty.
-    YamlIO.mapOptional("restorePoint", MFI.RestorePoint,
-                       StringValue()); // Don't print it out when it's empty.
+    YamlIO.mapOptional(
+        "savePoints", MFI.SavePoints,
+        SaveRestorePoints()); // Don't print it out when it's empty.
+    YamlIO.mapOptional(
+        "restorePoints", MFI.RestorePoints,
+        SaveRestorePoints()); // Don't print it out when it's empty.
   }
 };
 
diff --git a/llvm/include/llvm/CodeGen/MachineDominators.h b/llvm/include/llvm/CodeGen/MachineDominators.h
index 74cf94398736dd..88800d91ef51a9 100644
--- a/llvm/include/llvm/CodeGen/MachineDominators.h
+++ b/llvm/include/llvm/CodeGen/MachineDominators.h
@@ -185,6 +185,11 @@ class MachineDominatorTree : public DomTreeBase<MachineBasicBlock> {
     return Base::findNearestCommonDominator(A, B);
   }
 
+  /// Returns the nearest common dominator of the given blocks.
+  /// If that tree node is a virtual root, a nullptr will be returned.
+  MachineBasicBlock *
+  findNearestCommonDominator(ArrayRef<MachineBasicBlock *> Blocks) const;
+
   MachineDomTreeNode *operator[](MachineBasicBlock *BB) const {
     applySplitCriticalEdges();
     return Base::getNode(BB);
diff --git a/llvm/lib/CodeGen/MIRParser/MIRParser.cpp b/llvm/lib/CodeGen/MIRParser/MIRParser.cpp
index e2543f883f91ce..f7c1e162d2a96e 100644
--- a/llvm/lib/CodeGen/MIRParser/MIRParser.cpp
+++ b/llvm/lib/CodeGen/MIRParser/MIRParser.cpp
@@ -124,6 +124,10 @@ class MIRParserImpl {
   bool initializeFrameInfo(PerFunctionMIParsingState &PFS,
                            const yaml::MachineFunction &YamlMF);
 
+  bool initializeSaveRestorePoints(PerFunctionMIParsingState &PFS,
+                                   const yaml::SaveRestorePoints &YamlSRP,
+                                   bool IsSavePoints);
+
   bool initializeCallSiteInfo(PerFunctionMIParsingState &PFS,
                               const yaml::MachineFunction &YamlMF);
 
@@ -832,18 +836,9 @@ bool MIRParserImpl::initializeFrameInfo(PerFunctionMIParsingState &PFS,
   MFI.setHasTailCall(YamlMFI.HasTailCall);
   MFI.setCalleeSavedInfoValid(YamlMFI.IsCalleeSavedInfoValid);
   MFI.setLocalFrameSize(YamlMFI.LocalFrameSize);
-  if (!YamlMFI.SavePoint.Value.empty()) {
-    MachineBasicBlock *MBB = nullptr;
-    if (parseMBBReference(PFS, MBB, YamlMFI.SavePoint))
-      return true;
-    MFI.setSavePoint(MBB);
-  }
-  if (!YamlMFI.RestorePoint.Value.empty()) {
-    MachineBasicBlock *MBB = nullptr;
-    if (parseMBBReference(PFS, MBB, YamlMFI.RestorePoint))
-      return true;
-    MFI.setRestorePoint(MBB);
-  }
+  initializeSaveRestorePoints(PFS, YamlMFI.SavePoints, true /*IsSavePoints*/);
+  initializeSaveRestorePoints(PFS, YamlMFI.RestorePoints,
+                              false /*IsSavePoints*/);
 
   std::vector<CalleeSavedInfo> CSIInfo;
   // Initialize the fixed frame objects.
@@ -1058,8 +1053,28 @@ bool MIRParserImpl::initializeConstantPool(PerFunctionMIParsingState &PFS,
   return false;
 }
 
-bool MIRParserImpl::initializeJumpTableInfo(PerFunctionMIParsingState &PFS,
-    const yaml::MachineJumpTable &YamlJTI) {
+bool MIRParserImpl::initializeSaveRestorePoints(
+    PerFunctionMIParsingState &PFS, const yaml::SaveRestorePoints &YamlSRP,
+    bool IsSavePoints) {
+  MachineFunction &MF = PFS.MF;
+  MachineFrameInfo &MFI = MF.getFrameInfo();
+
+  if (!YamlSRP.empty()) {
+    const auto &Entry = YamlSRP.front();
+    const auto &MBBSource = Entry.Point;
+    MachineBasicBlock *MBB = nullptr;
+    if (parseMBBReference(PFS, MBB, MBBSource.Value))
+      return true;
+    if (IsSavePoints)
+      MFI.setSavePoint(MBB);
+    else
+      MFI.setRestorePoint(MBB);
+  }
+  return false;
+}
+
+bool MIRParserImpl::initializeJumpTableInfo(
+    PerFunctionMIParsingState &PFS, const yaml::MachineJumpTable &YamlJTI) {
   MachineJumpTableInfo *JTI = PFS.MF.getOrCreateJumpTableInfo(YamlJTI.Kind);
   for (const auto &Entry : YamlJTI.Entries) {
     std::vector<MachineBasicBlock *> Blocks;
diff --git a/llvm/lib/CodeGen/MIRPrinter.cpp b/llvm/lib/CodeGen/MIRPrinter.cpp
index c8f6341c1224d2..2d0728a6452808 100644
--- a/llvm/lib/CodeGen/MIRPrinter.cpp
+++ b/llvm/lib/CodeGen/MIRPrinter.cpp
@@ -118,6 +118,8 @@ class MIRPrinter {
                const TargetRegisterInfo *TRI);
   void convert(ModuleSlotTracker &MST, yaml::MachineFrameInfo &YamlMFI,
                const MachineFrameInfo &MFI);
+  void convert(ModuleSlotTracker &MST, yaml::SaveRestorePoints &YamlSRP,
+               MachineBasicBlock *SaveRestorePoint);
   void convert(yaml::MachineFunction &MF,
                const MachineConstantPool &ConstantPool);
   void convert(ModuleSlotTracker &MST, yaml::MachineJumpTable &YamlJTI,
@@ -392,14 +394,10 @@ void MIRPrinter::convert(ModuleSlotTracker &MST,
   YamlMFI.HasTailCall = MFI.hasTailCall();
   YamlMFI.IsCalleeSavedInfoValid = MFI.isCalleeSavedInfoValid();
   YamlMFI.LocalFrameSize = MFI.getLocalFrameSize();
-  if (MFI.getSavePoint()) {
-    raw_string_ostream StrOS(YamlMFI.SavePoint.Value);
-    StrOS << printMBBReference(*MFI.getSavePoint());
-  }
-  if (MFI.getRestorePoint()) {
-    raw_string_ostream StrOS(YamlMFI.RestorePoint.Value);
-    StrOS << printMBBReference(*MFI.getRestorePoint());
-  }
+  if (MFI.getSavePoint())
+    convert(MST, YamlMFI.SavePoints, MFI.getSavePoint());
+  if (MFI.getRestorePoint())
+    convert(MST, YamlMFI.RestorePoints, MFI.getRestorePoint());
 }
 
 void MIRPrinter::convertEntryValueObjects(yaml::MachineFunction &YMF,
@@ -618,6 +616,18 @@ void MIRPrinter::convert(yaml::MachineFunction &MF,
   }
 }
 
+void MIRPrinter::convert(ModuleSlotTracker &MST,
+                         yaml::SaveRestorePoints &YamlSRP,
+                         MachineBasicBlock *SRP) {
+  std::string Str;
+  yaml::SRPEntry Entry;
+  raw_string_ostream StrOS(Str);
+  StrOS << printMBBReference(*SRP);
+  Entry.Point = StrOS.str();
+  Str.clear();
+  YamlSRP.push_back(Entry);
+}
+
 void MIRPrinter::convert(ModuleSlotTracker &MST,
                          yaml::MachineJumpTable &YamlJTI,
                          const MachineJumpTableInfo &JTI) {
diff --git a/llvm/lib/CodeGen/MachineDominators.cpp b/llvm/lib/CodeGen/MachineDominators.cpp
index a2cc8fdfa7c9f9..384f90c6da66c0 100644
--- a/llvm/lib/CodeGen/MachineDominators.cpp
+++ b/llvm/lib/CodeGen/MachineDominators.cpp
@@ -189,3 +189,19 @@ void MachineDominatorTree::applySplitCriticalEdges() const {
   NewBBs.clear();
   CriticalEdgesToSplit.clear();
 }
+
+MachineBasicBlock *MachineDominatorTree::findNearestCommonDominator(
+    ArrayRef<MachineBasicBlock *> Blocks) const {
+  assert(!Blocks.empty());
+
+  MachineBasicBlock *NCD = Blocks.front();
+  for (MachineBasicBlock *BB : Blocks.drop_front()) {
+    NCD = Base::findNearestCommonDominator(NCD, BB);
+
+    // Stop when the root is reached.
+    if (Base::isVirtualRoot(Base::getNode(NCD)))
+      return nullptr;
+  }
+
+  return NCD;
+}
diff --git a/llvm/lib/Target/RISCV/RISCVFrameLowering.cpp b/llvm/lib/Target/RISCV/RISCVFrameLowering.cpp
index deb0b627225c64..0de1f1d821a6e2 100644
--- a/llvm/lib/Target/RISCV/RISCVFrameLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVFrameLowering.cpp
@@ -1607,6 +1607,8 @@ bool RISCVFrameLowering::assignCalleeSavedSpillSlots(
         int FrameIdx = MFI.CreateFixedSpillStackObject(Size, Offset);
         assert(FrameIdx < 0);
         CS.setFrameIdx(FrameIdx);
+        if (RISCVRegisterInfo::isRVVRegClass(RC))
+          MFI.setStackID(FrameIdx, TargetStackID::ScalableVector);
         continue;
       }
     }
@@ -1623,6 +1625,8 @@ bool RISCVFrameLowering::assignCalleeSavedSpillSlots(
     if ((unsigned)FrameIdx > MaxCSFrameIndex)
       MaxCSFrameIndex = FrameIdx;
     CS.setFrameIdx(FrameIdx);
+    if (RISCVRegisterInfo::isRVVRegClass(RC))
+      MFI.setStackID(FrameIdx, TargetStackID::ScalableVector);
   }
 
   // Allocate a fixed object that covers the full push or libcall size.
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/store-merging-debug.mir b/llvm/test/CodeGen/AArch64/GlobalISel/store-merging-debug.mir
index d52ef0f3da74c7..2e8f3c460b2fe7 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/store-merging-debug.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/store-merging-debug.mir
@@ -86,8 +86,8 @@ frameInfo:
   hasMustTailInVarArgFunc: false
   hasTailCall:     false
   localFrameSize:  0
-  savePoint:       ''
-  restorePoint:    ''
+  savePoints:      []
+  restorePoints:   []
 fixedStack:      []
 stack:           []
 callSites:       []
diff --git a/llvm/test/CodeGen/AArch64/aarch64-ldst-no-premature-sp-pop.mir b/llvm/test/CodeGen/AArch64/aarch64-ldst-no-premature-sp-pop.mir
index ba621cf77f9aed..07e80538e793f5 100644
--- a/llvm/test/CodeGen/AArch64/aarch64-ldst-no-premature-sp-pop.mir
+++ b/llvm/test/CodeGen/AArch64/aarch64-ldst-no-premature-sp-pop.mir
@@ -59,8 +59,8 @@ frameInfo:
   hasVAStart:      false
   hasMustTailInVarArgFunc: false
   localFrameSize:  16
-  savePoint:       ''
-  restorePoint:    ''
+  savePoints:      []
+  restorePoints:   []
 fixedStack:      []
 stack:
   - { id: 0, type: default, offset: -16, size: 16,
diff --git a/llvm/test/CodeGen/AArch64/aarch64-mov-debug-locs.mir b/llvm/test/CodeGen/AArch64/aarch64-mov-debug-locs.mir
index 16e2de751381ad..31589a86599ff3 100644
--- a/llvm/test/CodeGen/AArch64/aarch64-mov-debug-locs.mir
+++ b/llvm/test/CodeGen/AArch64/aarch64-mov-debug-locs.mir
@@ -157,8 +157,8 @@ frameInfo:
   hasVAStart:      false
   hasMustTailInVarArgFunc: false
   localFrameSize:  0
-  savePoint:       ''
-  restorePoint:    ''
+  savePoints:      []
+  restorePoints:   []
 fixedStack:      []
 stack:           
   - { id: 0, name: '', type: spill-slot, offset: -8, size: 8, alignment: 8, 
diff --git a/llvm/test/CodeGen/AArch64/aarch64st1.mir b/llvm/test/CodeGen/AArch64/aarch64st1.mir
index 22a024d37bc64f..439db1e97aa794 100644
--- a/llvm/test/CodeGen/AArch64/aarch64st1.mir
+++ b/llvm/test/CodeGen/AArch64/aarch64st1.mir
@@ -58,8 +58,8 @@ frameInfo:
   hasMustTailInVarArgFunc: false
   hasTailCall:     false
   localFrameSize:  0
-  savePoint:       ''
-  restorePoint:    ''
+  savePoints:      []
+  restorePoints:   []
 fixedStack:      []
 stack:
   - { id: 0, name: '', type: default, offset: 0, size: 4, alignment: 4, 
diff --git a/llvm/test/CodeGen/AArch64/cfi-fixup-multi-block-prologue.mir b/llvm/test/CodeGen/AArch64/cfi-fixup-multi-block-prologue.mir
index 31fa3832367bec..6851fdba1239a4 100644
--- a/llvm/test/CodeGen/AArch64/cfi-fixup-multi-block-prologue.mir
+++ b/llvm/test/CodeGen/AArch64/cfi-fixup-multi-block-prologue.mir
@@ -80,8 +80,8 @@ frameInfo:
   hasMustTailInVarArgFunc: false
   hasTailCall:     false
   localFrameSize:  30000
-  savePoint:       ''
-  restorePoint:    ''
+  savePoints:      []
+  restorePoints:   []
 fixedStack:      []
 stack:
   - { id: 0, name: p, type: default, offset: -30016, size: 30000, alignment: 1,
diff --git a/llvm/test/CodeGen/AArch64/cfi-fixup-multi-section.mir b/llvm/test/CodeGen/AArch64/cfi-fixup-multi-section.mir
index a24972d1388320..fe5c90a5e6dc54 100644
--- a/llvm/test/CodeGen/AArch64/cfi-fixup-multi-section.mir
+++ b/llvm/test/CodeGen/AArch64/cfi-fixup-multi-section.mir
@@ -47,8 +47,8 @@ frameInfo:
   hasMustTailInVarArgFunc: false
   hasTailCall:     false
   localFrameSize:  0
-  savePoint:       ''
-  restorePoint:    ''
+  savePoints:      []
+  restorePoints:   []
 fixedStack:      []
 stack:
   - { id: 0, name: '', type: spill-slot, offset: -16, size: 8, alignment: 16,
diff --git a/llvm/test/CodeGen/AArch64/cfi-fixup.mir b/llvm/test/CodeGen/AArch64/cfi-fixup.mir
index f522df6bb3fa06..dd75cec7f6e0be 100644
--- a/llvm/test/CodeGen/AArch64/cfi-fixup.mir
+++ b/llvm/test/CodeGen/AArch64/cfi-fixup.mir
@@ -65,8 +65,8 @@ frameInfo:
   hasMustTailInVarArgFunc: false
   hasTailCall:     false
   localFrameSize:  0
-  savePoint:       ''
-  restorePoint:    ''
+  savePoints:      []
+  restorePoints:   []
 fixedStack:      []
 stack:
   - { id: 0, name: '', type: spill-slot, offset: -16, size: 8, alignment: 16,
@@ -248,8 +248,8 @@ frameInfo:
   hasMustTailInVarArgFunc: false
   hasTailCall:     false
   localFrameSize:  0
-  savePoint:       ''
-  restorePoint:    ''
+  savePoints:      []
+  restorePoints:   []
 fixedStack:      []
 stack:
   - { id: 0, name: '', type: spill-slot, offset: -16, size: 8, alignment: 16,
@@ -403,8 +403,8 @@ frameInfo:
   hasMustTailInVarArgFunc: false
   hasTailCall:     false
   localFrameSize:  0
-  savePoint:       ''
-  restorePoint:    ''
+  savePoints:      []
+  restorePoints:   []
 fixedStack:      []
 stack:
   - { id: 0, name: '', type: spill-slot, offset: -16, size: 8, alignment: 16,
diff --git a/llvm/test/CodeGen/AArch64/dont-shrink-wrap-stack-mayloadorstore.mir b/llvm/test/CodeGen/AArch64/dont-shrink-wrap-stack-mayloadorstore.mir
index 1c4447bffd8729..85f8abcbf7fe60 100644
--- a/llvm/test/CodeGen/AArch64/dont-shrink-wrap-stack-mayloadorstore.mir
+++ b/llvm/test/CodeGen/AArch64/dont-shrink-wrap-stack-mayloadorstore.mir
@@ -6,17 +6,23 @@
  ; RUN: llc -x=mir -simplify-mir -run-pass=shrink-wrap -o - %s | FileCheck %s
  ; CHECK:      name:            compiler_pop_stack
  ; CHECK:      frameInfo:
- ; CHECK:      savePoint:       '%bb.1'
- ; CHECK:      restorePoint:    '%bb.7'
+ ; CHECK:        savePoints:
+ ; CHECK-NEXT:     - point:           '%bb.1'
+ ; CHECK:        restorePoints:
+ ; CHECK-NEXT:     - point:           '%bb.7'
  ; CHECK:      name:            compiler_pop_stack_no_memoperands
  ; CHECK:      frameInfo:
- ; CHECK:      savePoint:       '%bb.1'
- ; CHECK:      restorePoint:    '%bb.7'
+ ; CHECK:        savePoints:
+ ; CHECK-NEXT:     - point:           '%bb.1'
+ ; CHECK:        restorePoints:
+ ; CHECK-NEXT:     - point:           '%bb.7'
  ; CHECK:      name:            f
  ; CHECK:      frameInfo:
- ; CHECK:      savePoint:       '%bb.2'
- ; CHECK-NEXT: restorePoint:    '%bb.4'
- ; CHECK-NEXT: stack:
+ ; CHECK:        savePoints:
+ ; CHECK-NEXT:     - point:           '%bb.2'
+ ; CHECK:        restorePoints:
+ ; CHECK-NEXT:     - point:           '%bb.4'
+ ; CHECK:      stack:
 
   target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"
   target triple = "aarch64"
diff --git a/llvm/test/CodeGen/AArch64/early-ifcvt-regclass-mismatch.mir b/llvm/test/CodeGen/AArch64/early-ifcvt-regclass-mismatch.mir
index a7f67f8b682c3c..6324db0cb2c0ff 100644
--- a/llvm/test/CodeGen/AArch64/early-ifcvt-regclass-mismatch.mir
+++ b/llvm/test/CodeGen/AArch64/early-ifcvt-regclass-mismatch.mir
@@ -105,8 +105,8 @@ frameInfo:
   hasVAStart:      false
   hasMustTailInVarArgFunc: false
   localFrameSize:  0
-  savePoint:       ''
-  restorePoint:    ''
+  savePoints:      []
+  restorePoints:   []
 fixedStack:      []
 stack:           []
 callSites:       []
diff --git a/llvm/test/CodeGen/AArch64/emit_fneg_with_non_register_operand.mir b/llvm/test/CodeGen/AArch64/emit_fneg_with_non_register_operand.mir
index f9878adfe5e448..3c98a1a128413e 100644
--- a/llvm/test/CodeGen/AArch64/emit_fneg_with_non_register_operand.mir
+++ b/llvm/test/CodeGen/AArch64/emit_fneg_with_non_register_operand.mir
@@ -75,8 +75,8 @@ frameInfo:
   hasMustTailInVarArgFunc: false
   hasTailCall:     true
   localFrameSize:  0
-  savePoint:       ''
-  restorePoint:    ''
+  savePoints:      []
+  restorePoints:   []
 fixedStack:      []
 stack:           []
 entry_values:    []
diff --git a/llvm/test/CodeGen/AArch64/irg-nomem.mir b/llvm/test/CodeGen/AArch64/irg-nomem.mir
index 3b000fafbed46f..78438151405e66 100644
--- a/llvm/test/CodeGen/AArch64/irg-nomem.mir
+++ b/llvm/test/CodeGen/AArch64/irg-nomem.mir
@@ -47,8 +47,8 @@ frameInfo:
   hasVAStart:      false
   hasMustTailInVarArgFunc: false
   localFrameSize:  0
-  savePoint:       ''
-  restorePoint:    ''
+  savePoints:      []
+  restorePoints:   []
 fixedStack:      []
 stack:           []
 callSites:       []
diff --git a/llvm/test/CodeGen/AArch64/jump-table-duplicate.mir b/llvm/test/CodeGen/AArch64/jump-table-duplicate.mir
index a2532a854923f5..81cf5953895cab 100644
--- a/llvm/test/CodeGen/AArch64/jump-table-duplicate.mir
+++ b/llvm/test/CodeGen/AArch64/jump-table-duplicate.mir
@@ -92,8 +92,8 @@ frameInfo:
   hasVAStart:      false
   hasMustTailInVarArgFunc: false
   localFrameSize:  0
-  savePoint:       ''
-  restorePoint:    ''
+  savePoints:      []
+  restorePoints:   []
 fixedStack:      []
 stack:
   - { id: 0, name: '', type: spill-slot, offset: -8, size: 8, alignment: 8, 
diff --git a/llvm/test/CodeGen/AArch64/ldst-nopreidx-sp-redzone.mir b/llvm/test/CodeGen/AArch64/ldst-nopreidx-sp-redzone.mir
index f1f9e5fbc9b087..b431de2d9b35b3 100644
--- a/llvm/test/CodeGen/AArch64/ldst-nopreidx-sp-redzone.mir
+++ b/llvm/test/CodeGen/AArch64/ldst-nopreidx-sp-redzone.mir
@@ -103,8 +103,8 @@ frameInfo:
   hasVAStart:      false
   hasMustTailInVarArgFunc: false
   localFrameSize:  480
-  savePoint:       ''
-  restorePoint:    ''
+  savePoints:      []
+  restorePoints:   []
 fixedStack:      []
 stack:
   - { id: 0, name: StackGuardSlot, type: default, offset: -40, size: 8, 
@@ -216,8 +216,8 @@ frameInfo:
   hasVAStart:      false
   hasMustTailInVarArgFunc: false
   localFrameSize:  480
-  savePoint:       ''
-  restorePoint:    ''
+  savePoints:      []
+  restorePoints:   []
 fixedStack:      []
 stack:
   - { id: 0, name: StackGuardSlot, type: default, offset: -40, size: 8, 
@@ -327,8 +327,8 @@ frameInfo:
   hasVAStart:      false
   hasMustTailInVarArgFunc: false
   localFrameSize:  480
-  savePoint:       ''
-  restorePoint:    ''
+  savePoints:      []
+  restorePoints:   []
 fixedStack:      []
 stack:
   - { id: 0, name: StackGuardSlot, type: default, offset: -40, size: 8, 
diff --git a/llvm/test/CodeGen/AArch64/live-debugvalues-sve.mir b/llvm/test/CodeGen/AArch64/live-debugvalues-sve.mir
index 612453ab53f438..4be16228814a3b 100644
--- a/llvm/test/CodeGen/AArch64/live-debugvalues-sve.mir
+++ b/llvm/test/CodeGen/AArch64/live-debugvalues-sve.mir
@@ -120,8 +120,10 @@ frameInfo:
   adjustsStack:    true
   hasC...
[truncated]

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llvmbot commented Dec 10, 2024

@llvm/pr-subscribers-backend-aarch64

Author: Elizaveta Noskova (enoskova-sc)

Changes

Currently mir supports only one save and one restore point specification:

  savePoint:       '%bb.1'
  restorePoint:    '%bb.2'

This patch provide possibility to have multiple save and multiple restore points in mir:

  savePoints:
    - point:           '%bb.1'
  restorePoints:
    - point:           '%bb.2'

Shrink-Wrap points split Part 3.

Part 1: #117862
Part 2: #119355


Patch is 276.31 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/119357.diff

340 Files Affected:

  • (modified) llvm/include/llvm/CodeGen/MIRYamlMapping.h (+32-7)
  • (modified) llvm/include/llvm/CodeGen/MachineDominators.h (+5)
  • (modified) llvm/lib/CodeGen/MIRParser/MIRParser.cpp (+29-14)
  • (modified) llvm/lib/CodeGen/MIRPrinter.cpp (+18-8)
  • (modified) llvm/lib/CodeGen/MachineDominators.cpp (+16)
  • (modified) llvm/lib/Target/RISCV/RISCVFrameLowering.cpp (+4)
  • (modified) llvm/test/CodeGen/AArch64/GlobalISel/store-merging-debug.mir (+2-2)
  • (modified) llvm/test/CodeGen/AArch64/aarch64-ldst-no-premature-sp-pop.mir (+2-2)
  • (modified) llvm/test/CodeGen/AArch64/aarch64-mov-debug-locs.mir (+2-2)
  • (modified) llvm/test/CodeGen/AArch64/aarch64st1.mir (+2-2)
  • (modified) llvm/test/CodeGen/AArch64/cfi-fixup-multi-block-prologue.mir (+2-2)
  • (modified) llvm/test/CodeGen/AArch64/cfi-fixup-multi-section.mir (+2-2)
  • (modified) llvm/test/CodeGen/AArch64/cfi-fixup.mir (+6-6)
  • (modified) llvm/test/CodeGen/AArch64/dont-shrink-wrap-stack-mayloadorstore.mir (+13-7)
  • (modified) llvm/test/CodeGen/AArch64/early-ifcvt-regclass-mismatch.mir (+2-2)
  • (modified) llvm/test/CodeGen/AArch64/emit_fneg_with_non_register_operand.mir (+2-2)
  • (modified) llvm/test/CodeGen/AArch64/irg-nomem.mir (+2-2)
  • (modified) llvm/test/CodeGen/AArch64/jump-table-duplicate.mir (+2-2)
  • (modified) llvm/test/CodeGen/AArch64/ldst-nopreidx-sp-redzone.mir (+6-6)
  • (modified) llvm/test/CodeGen/AArch64/live-debugvalues-sve.mir (+4-2)
  • (modified) llvm/test/CodeGen/AArch64/loop-sink-limit.mir (+2-2)
  • (modified) llvm/test/CodeGen/AArch64/loop-sink.mir (+16-16)
  • (modified) llvm/test/CodeGen/AArch64/machine-latecleanup-inlineasm.mir (+2-2)
  • (modified) llvm/test/CodeGen/AArch64/nested-iv-regalloc.mir (+2-2)
  • (modified) llvm/test/CodeGen/AArch64/regalloc-last-chance-recolor-with-split.mir (+2-2)
  • (modified) llvm/test/CodeGen/AArch64/shrinkwrap-split-restore-point.mir (+2-2)
  • (modified) llvm/test/CodeGen/AArch64/sink-and-fold-drop-dbg.mir (+2-2)
  • (modified) llvm/test/CodeGen/AArch64/sink-and-fold-illegal-shift.mir (+2-2)
  • (modified) llvm/test/CodeGen/AArch64/sink-and-fold-preserve-debugloc.mir (+4-4)
  • (modified) llvm/test/CodeGen/AArch64/split-deadloop.mir (+2-2)
  • (modified) llvm/test/CodeGen/AArch64/stack-probing-last-in-block.mir (+2-2)
  • (modified) llvm/test/CodeGen/AArch64/tail-dup-redundant-phi.mir (+2-2)
  • (modified) llvm/test/CodeGen/AArch64/taildup-addrtaken.mir (+2-2)
  • (modified) llvm/test/CodeGen/AArch64/wineh-frame-predecrement.mir (+2-2)
  • (modified) llvm/test/CodeGen/AArch64/wineh-frame-scavenge.mir (+2-2)
  • (modified) llvm/test/CodeGen/AArch64/wineh-frame1.mir (+2-2)
  • (modified) llvm/test/CodeGen/AArch64/wineh-frame2.mir (+2-2)
  • (modified) llvm/test/CodeGen/AArch64/wineh-frame3.mir (+2-2)
  • (modified) llvm/test/CodeGen/AArch64/wineh-frame4.mir (+2-2)
  • (modified) llvm/test/CodeGen/AArch64/wineh-frame5.mir (+2-2)
  • (modified) llvm/test/CodeGen/AArch64/wineh-frame6.mir (+2-2)
  • (modified) llvm/test/CodeGen/AArch64/wineh-frame7.mir (+2-2)
  • (modified) llvm/test/CodeGen/AArch64/wineh-frame8.mir (+2-2)
  • (modified) llvm/test/CodeGen/AArch64/wineh-save-lrpair1.mir (+2-2)
  • (modified) llvm/test/CodeGen/AArch64/wineh-save-lrpair2.mir (+2-2)
  • (modified) llvm/test/CodeGen/AArch64/wineh-save-lrpair3.mir (+2-2)
  • (modified) llvm/test/CodeGen/AArch64/wineh2.mir (+2-2)
  • (modified) llvm/test/CodeGen/AArch64/wineh3.mir (+2-2)
  • (modified) llvm/test/CodeGen/AArch64/wineh4.mir (+2-2)
  • (modified) llvm/test/CodeGen/AArch64/wineh5.mir (+2-2)
  • (modified) llvm/test/CodeGen/AArch64/wineh6.mir (+2-2)
  • (modified) llvm/test/CodeGen/AArch64/wineh7.mir (+2-2)
  • (modified) llvm/test/CodeGen/AArch64/wineh8.mir (+2-2)
  • (modified) llvm/test/CodeGen/AArch64/wineh9.mir (+2-2)
  • (modified) llvm/test/CodeGen/AArch64/wineh_shrinkwrap.mir (+2-2)
  • (modified) llvm/test/CodeGen/AMDGPU/memory-legalizer-multiple-mem-operands-nontemporal-1.mir (+2-2)
  • (modified) llvm/test/CodeGen/AMDGPU/memory-legalizer-multiple-mem-operands-nontemporal-2.mir (+2-2)
  • (modified) llvm/test/CodeGen/ARM/cmse-vlldm-no-reorder.mir (+2-2)
  • (modified) llvm/test/CodeGen/ARM/codesize-ifcvt.mir (+6-6)
  • (modified) llvm/test/CodeGen/ARM/constant-island-movwt.mir (+2-2)
  • (modified) llvm/test/CodeGen/ARM/constant-islands-cfg.mir (+2-2)
  • (modified) llvm/test/CodeGen/ARM/constant-islands-split-IT.mir (+2-2)
  • (modified) llvm/test/CodeGen/ARM/execute-only-save-cpsr.mir (+8-8)
  • (modified) llvm/test/CodeGen/ARM/fp16-litpool2-arm.mir (+2-2)
  • (modified) llvm/test/CodeGen/ARM/fp16-litpool3-arm.mir (+2-2)
  • (modified) llvm/test/CodeGen/ARM/inlineasmbr-if-cvt.mir (+2-2)
  • (modified) llvm/test/CodeGen/ARM/invalidated-save-point.ll (+2-2)
  • (modified) llvm/test/CodeGen/ARM/jump-table-dbg-value.mir (+2-2)
  • (modified) llvm/test/CodeGen/ARM/stack_frame_offset.mir (+6-6)
  • (modified) llvm/test/CodeGen/Hexagon/cext-opt-block-addr.mir (+4-4)
  • (modified) llvm/test/CodeGen/Hexagon/early-if-predicator.mir (+2-2)
  • (modified) llvm/test/CodeGen/Hexagon/machine-sink-float-usr.mir (+4-4)
  • (modified) llvm/test/CodeGen/Hexagon/pipeliner/swp-phi-start.mir (+2-2)
  • (modified) llvm/test/CodeGen/MIR/ARM/thumb2-sub-sp-t3.mir (+2-2)
  • (modified) llvm/test/CodeGen/MIR/Generic/frame-info.mir (+2-2)
  • (modified) llvm/test/CodeGen/MIR/Hexagon/addrmode-opt-nonreaching.mir (+2-2)
  • (modified) llvm/test/CodeGen/MIR/RISCV/machine-function-info.mir (+2-2)
  • (modified) llvm/test/CodeGen/MIR/X86/branch-folder-with-label.mir (+6-6)
  • (modified) llvm/test/CodeGen/MIR/X86/diexpr-win32.mir (+4-4)
  • (modified) llvm/test/CodeGen/MIR/X86/fake-use-tailcall.mir (+2-2)
  • (modified) llvm/test/CodeGen/MIR/X86/frame-info-save-restore-points.mir (+8-4)
  • (modified) llvm/test/CodeGen/MIR/X86/inline-asm-rm-exhaustion.mir (+6-6)
  • (modified) llvm/test/CodeGen/Mips/delay-slot-filler-bundled-insts-def-use.mir (+2-2)
  • (modified) llvm/test/CodeGen/Mips/delay-slot-filler-bundled-insts.mir (+2-2)
  • (modified) llvm/test/CodeGen/Mips/indirect-jump-hazard/guards-verify-call.mir (+2-2)
  • (modified) llvm/test/CodeGen/Mips/indirect-jump-hazard/guards-verify-tailcall.mir (+2-2)
  • (modified) llvm/test/CodeGen/Mips/instverify/dext-pos.mir (+2-2)
  • (modified) llvm/test/CodeGen/Mips/instverify/dext-size.mir (+2-2)
  • (modified) llvm/test/CodeGen/Mips/instverify/dextm-pos-size.mir (+2-2)
  • (modified) llvm/test/CodeGen/Mips/instverify/dextm-pos.mir (+2-2)
  • (modified) llvm/test/CodeGen/Mips/instverify/dextm-size.mir (+2-2)
  • (modified) llvm/test/CodeGen/Mips/instverify/dextu-pos-size.mir (+2-2)
  • (modified) llvm/test/CodeGen/Mips/instverify/dextu-pos.mir (+2-2)
  • (modified) llvm/test/CodeGen/Mips/instverify/dextu-size-valid.mir (+2-2)
  • (modified) llvm/test/CodeGen/Mips/instverify/dextu-size.mir (+2-2)
  • (modified) llvm/test/CodeGen/Mips/instverify/dins-pos-size.mir (+2-2)
  • (modified) llvm/test/CodeGen/Mips/instverify/dins-pos.mir (+2-2)
  • (modified) llvm/test/CodeGen/Mips/instverify/dins-size.mir (+2-2)
  • (modified) llvm/test/CodeGen/Mips/instverify/dinsm-pos-size.mir (+2-2)
  • (modified) llvm/test/CodeGen/Mips/instverify/dinsm-pos.mir (+2-2)
  • (modified) llvm/test/CodeGen/Mips/instverify/dinsm-size.mir (+2-2)
  • (modified) llvm/test/CodeGen/Mips/instverify/dinsu-pos-size.mir (+2-2)
  • (modified) llvm/test/CodeGen/Mips/instverify/dinsu-pos.mir (+2-2)
  • (modified) llvm/test/CodeGen/Mips/instverify/dinsu-size.mir (+2-2)
  • (modified) llvm/test/CodeGen/Mips/instverify/ext-pos-size.mir (+2-2)
  • (modified) llvm/test/CodeGen/Mips/instverify/ext-pos.mir (+2-2)
  • (modified) llvm/test/CodeGen/Mips/instverify/ext-size.mir (+2-2)
  • (modified) llvm/test/CodeGen/Mips/instverify/ins-pos-size.mir (+2-2)
  • (modified) llvm/test/CodeGen/Mips/instverify/ins-pos.mir (+2-2)
  • (modified) llvm/test/CodeGen/Mips/instverify/ins-size.mir (+2-2)
  • (modified) llvm/test/CodeGen/Mips/longbranch/branch-limits-fp-micromips.mir (+4-4)
  • (modified) llvm/test/CodeGen/Mips/longbranch/branch-limits-fp-micromipsr6.mir (+4-4)
  • (modified) llvm/test/CodeGen/Mips/longbranch/branch-limits-fp-mips.mir (+4-4)
  • (modified) llvm/test/CodeGen/Mips/longbranch/branch-limits-fp-mipsr6.mir (+4-4)
  • (modified) llvm/test/CodeGen/Mips/longbranch/branch-limits-int-microMIPS.mir (+16-16)
  • (modified) llvm/test/CodeGen/Mips/longbranch/branch-limits-int-micromipsr6.mir (+24-24)
  • (modified) llvm/test/CodeGen/Mips/longbranch/branch-limits-int-mips64.mir (+12-12)
  • (modified) llvm/test/CodeGen/Mips/longbranch/branch-limits-int-mips64r6.mir (+24-24)
  • (modified) llvm/test/CodeGen/Mips/longbranch/branch-limits-int-mipsr6.mir (+24-24)
  • (modified) llvm/test/CodeGen/Mips/longbranch/branch-limits-int.mir (+12-12)
  • (modified) llvm/test/CodeGen/Mips/longbranch/branch-limits-msa.mir (+20-20)
  • (modified) llvm/test/CodeGen/Mips/micromips-eva.mir (+4-4)
  • (modified) llvm/test/CodeGen/Mips/micromips-short-delay-slot.mir (+2-2)
  • (modified) llvm/test/CodeGen/Mips/micromips-sizereduction/micromips-lwp-swp.mir (+8-8)
  • (modified) llvm/test/CodeGen/Mips/micromips-sizereduction/micromips-no-lwp-swp.mir (+8-8)
  • (modified) llvm/test/CodeGen/Mips/mirparser/target-flags-pic-mxgot-tls.mir (+2-2)
  • (modified) llvm/test/CodeGen/Mips/mirparser/target-flags-pic-o32.mir (+2-2)
  • (modified) llvm/test/CodeGen/Mips/mirparser/target-flags-pic.mir (+2-2)
  • (modified) llvm/test/CodeGen/Mips/mirparser/target-flags-static-tls.mir (+2-2)
  • (modified) llvm/test/CodeGen/Mips/msa/emergency-spill.mir (+2-2)
  • (modified) llvm/test/CodeGen/Mips/sll-micromips-r6-encoding.mir (+2-2)
  • (modified) llvm/test/CodeGen/Mips/unaligned-memops-mapping.mir (+4-4)
  • (modified) llvm/test/CodeGen/NVPTX/proxy-reg-erasure.mir (+2-2)
  • (modified) llvm/test/CodeGen/PowerPC/DisableHoistingDueToBlockHotnessNoProfileData.mir (+2-2)
  • (modified) llvm/test/CodeGen/PowerPC/DisableHoistingDueToBlockHotnessProfileData.mir (+2-2)
  • (modified) llvm/test/CodeGen/PowerPC/NoCRFieldRedefWhenSpillingCRBIT.mir (+2-2)
  • (modified) llvm/test/CodeGen/PowerPC/alignlongjumptest.mir (+2-2)
  • (modified) llvm/test/CodeGen/PowerPC/block-placement-1.mir (+4-4)
  • (modified) llvm/test/CodeGen/PowerPC/block-placement.mir (+2-2)
  • (modified) llvm/test/CodeGen/PowerPC/collapse-rotates.mir (+2-2)
  • (modified) llvm/test/CodeGen/PowerPC/convert-rr-to-ri-instrs-R0-special-handling.mir (+14-14)
  • (modified) llvm/test/CodeGen/PowerPC/convert-rr-to-ri-instrs-out-of-range.mir (+40-40)
  • (modified) llvm/test/CodeGen/PowerPC/convert-rr-to-ri-instrs.mir (+178-178)
  • (modified) llvm/test/CodeGen/PowerPC/ctrloop-do-not-duplicate-mi.mir (+2-2)
  • (modified) llvm/test/CodeGen/PowerPC/livevars-crash2.mir (+2-2)
  • (modified) llvm/test/CodeGen/PowerPC/peephole-phi-acc.mir (+8-8)
  • (modified) llvm/test/CodeGen/PowerPC/peephole-replaceInstr-after-eliminate-extsw.mir (+2-2)
  • (modified) llvm/test/CodeGen/PowerPC/phi-eliminate.mir (+2-2)
  • (modified) llvm/test/CodeGen/PowerPC/remove-copy-crunsetcrbit.mir (+2-2)
  • (modified) llvm/test/CodeGen/PowerPC/remove-implicit-use.mir (+2-2)
  • (modified) llvm/test/CodeGen/PowerPC/remove-redundant-li-skip-imp-kill.mir (+2-2)
  • (modified) llvm/test/CodeGen/PowerPC/remove-self-copies.mir (+2-2)
  • (modified) llvm/test/CodeGen/PowerPC/rlwinm_rldicl_to_andi.mir (+12-12)
  • (modified) llvm/test/CodeGen/PowerPC/schedule-addi-load.mir (+2-2)
  • (modified) llvm/test/CodeGen/PowerPC/setcr_bc.mir (+2-2)
  • (modified) llvm/test/CodeGen/PowerPC/setcr_bc2.mir (+2-2)
  • (modified) llvm/test/CodeGen/PowerPC/setcr_bc3.mir (+2-2)
  • (modified) llvm/test/CodeGen/PowerPC/tls_get_addr_fence1.mir (+2-2)
  • (modified) llvm/test/CodeGen/PowerPC/tls_get_addr_fence2.mir (+2-2)
  • (modified) llvm/test/CodeGen/PowerPC/two-address-crash.mir (+2-2)
  • (modified) llvm/test/CodeGen/RISCV/live-sp.mir (+2-2)
  • (modified) llvm/test/CodeGen/RISCV/pr53662.mir (+4-2)
  • (modified) llvm/test/CodeGen/RISCV/rvv/addi-rvv-stack-object.mir (+2-2)
  • (modified) llvm/test/CodeGen/RISCV/rvv/emergency-slot.mir (+2-2)
  • (modified) llvm/test/CodeGen/RISCV/rvv/large-rvv-stack-size.mir (+2-2)
  • (modified) llvm/test/CodeGen/RISCV/rvv/rvv-stack-align.mir (+6-6)
  • (modified) llvm/test/CodeGen/RISCV/rvv/undef-earlyclobber-chain.mir (+2-2)
  • (modified) llvm/test/CodeGen/RISCV/rvv/wrong-stack-offset-for-rvv-object.mir (+2-2)
  • (modified) llvm/test/CodeGen/RISCV/stack-slot-coloring.mir (+2-2)
  • (modified) llvm/test/CodeGen/RISCV/zcmp-prolog-epilog-crash.mir (+4-2)
  • (modified) llvm/test/CodeGen/Thumb2/LowOverheadLoops/add_reduce.mir (+2-2)
  • (modified) llvm/test/CodeGen/Thumb2/LowOverheadLoops/begin-vpt-without-inst.mir (+2-2)
  • (modified) llvm/test/CodeGen/Thumb2/LowOverheadLoops/biquad-cascade-default.mir (+2-2)
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  • (modified) llvm/test/CodeGen/Thumb2/LowOverheadLoops/cond-mov.mir (+2-2)
  • (modified) llvm/test/CodeGen/Thumb2/LowOverheadLoops/disjoint-vcmp.mir (+2-2)
  • (modified) llvm/test/CodeGen/Thumb2/LowOverheadLoops/dont-ignore-vctp.mir (+2-2)
  • (modified) llvm/test/CodeGen/Thumb2/LowOverheadLoops/dont-remove-loop-update.mir (+2-2)
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  • (modified) llvm/test/CodeGen/Thumb2/LowOverheadLoops/end-positive-offset.mir (+2-2)
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  • (modified) llvm/test/CodeGen/Thumb2/LowOverheadLoops/inloop-vpnot-1.mir (+2-2)
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  • (modified) llvm/test/CodeGen/Thumb2/LowOverheadLoops/inloop-vpsel-1.mir (+2-2)
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  • (modified) llvm/test/CodeGen/Thumb2/LowOverheadLoops/loop-dec-copy-chain.mir (+2-2)
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  • (modified) llvm/test/CodeGen/Thumb2/LowOverheadLoops/mov-after-dls.mir (+2-2)
  • (modified) llvm/test/CodeGen/Thumb2/LowOverheadLoops/mov-after-dlstp.mir (+2-2)
  • (modified) llvm/test/CodeGen/Thumb2/LowOverheadLoops/mov-lr-terminator.mir (+2-2)
  • (modified) llvm/test/CodeGen/Thumb2/LowOverheadLoops/move-def-before-start.mir (+2-2)
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  • (modified) llvm/test/CodeGen/Thumb2/LowOverheadLoops/multiple-do-loops.mir (+6-6)
  • (modified) llvm/test/CodeGen/Thumb2/LowOverheadLoops/mve-reduct-livein-arg.mir (+2-2)
  • (modified) llvm/test/CodeGen/Thumb2/LowOverheadLoops/no-dec-cbnz.mir (+2-2)
  • (modified) llvm/test/CodeGen/Thumb2/LowOverheadLoops/no-dec-reorder.mir (+2-2)
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  • (modified) llvm/test/CodeGen/Thumb2/LowOverheadLoops/non-masked-load.mir (+2-2)
  • (modified) llvm/test/CodeGen/Thumb2/LowOverheadLoops/non-masked-store.mir (+2-2)
  • (modified) llvm/test/CodeGen/Thumb2/LowOverheadLoops/out-of-range-cbz.mir (+2-2)
  • (modified) llvm/test/CodeGen/Thumb2/LowOverheadLoops/remove-elem-moves.mir (+2-2)
  • (modified) llvm/test/CodeGen/Thumb2/LowOverheadLoops/revert-after-call.mir (+2-2)
  • (modified) llvm/test/CodeGen/Thumb2/LowOverheadLoops/revert-after-read.mir (+2-2)
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  • (modified) llvm/test/CodeGen/Thumb2/LowOverheadLoops/revert-non-loop.mir (+2-2)
  • (modified) llvm/test/CodeGen/Thumb2/LowOverheadLoops/revert-while.mir (+2-2)
  • (modified) llvm/test/CodeGen/Thumb2/LowOverheadLoops/safe-def-no-mov.mir (+2-2)
  • (modified) llvm/test/CodeGen/Thumb2/LowOverheadLoops/safe-retaining.mir (+1-1)
  • (modified) llvm/test/CodeGen/Thumb2/LowOverheadLoops/size-limit.mir (+2-2)
  • (modified) llvm/test/CodeGen/Thumb2/LowOverheadLoops/skip-debug.mir (+2-2)
  • (modified) llvm/test/CodeGen/Thumb2/LowOverheadLoops/skip-vpt-debug.mir (+2-2)
  • (modified) llvm/test/CodeGen/Thumb2/LowOverheadLoops/switch.mir (+2-2)
  • (modified) llvm/test/CodeGen/Thumb2/LowOverheadLoops/unrolled-and-vector.mir (+2-2)
  • (modified) llvm/test/CodeGen/Thumb2/LowOverheadLoops/unsafe-cpsr-loop-def.mir (+2-2)
  • (modified) llvm/test/CodeGen/Thumb2/LowOverheadLoops/unsafe-cpsr-loop-use.mir (+2-2)
  • (modified) llvm/test/CodeGen/Thumb2/LowOverheadLoops/unsafe-use-after.mir (+2-2)
  • (modified) llvm/test/CodeGen/Thumb2/LowOverheadLoops/vaddv.mir (+38-38)
  • (modified) llvm/test/CodeGen/Thumb2/LowOverheadLoops/vctp-add-operand-liveout.mir (+2-2)
  • (modified) llvm/test/CodeGen/Thumb2/LowOverheadLoops/vctp-in-vpt-2.mir (+2-2)
  • (modified) llvm/test/CodeGen/Thumb2/LowOverheadLoops/vctp-in-vpt.mir (+8-8)
  • (modified) llvm/test/CodeGen/Thumb2/LowOverheadLoops/vctp-subi3.mir (+2-2)
  • (modified) llvm/test/CodeGen/Thumb2/LowOverheadLoops/vctp-subri.mir (+2-2)
  • (modified) llvm/test/CodeGen/Thumb2/LowOverheadLoops/vctp-subri12.mir (+2-2)
  • (modified) llvm/test/CodeGen/Thumb2/LowOverheadLoops/vctp16-reduce.mir (+2-2)
  • (modified) llvm/test/CodeGen/Thumb2/LowOverheadLoops/vmaxmin_vpred_r.mir (+2-2)
  • (modified) llvm/test/CodeGen/Thumb2/LowOverheadLoops/vmldava_in_vpt.mir (+2-2)
  • (modified) llvm/test/CodeGen/Thumb2/LowOverheadLoops/vpt-block-debug.mir (+2-2)
  • (modified) llvm/test/CodeGen/Thumb2/LowOverheadLoops/vpt-blocks.mir (+14-14)
  • (modified) llvm/test/CodeGen/Thumb2/LowOverheadLoops/while-negative-offset.mir (+2-2)
  • (modified) llvm/test/CodeGen/Thumb2/LowOverheadLoops/while.mir (+2-2)
  • (modified) llvm/test/CodeGen/Thumb2/LowOverheadLoops/wlstp.mir (+6-6)
  • (modified) llvm/test/CodeGen/Thumb2/LowOverheadLoops/wrong-liveout-lsr-shift.mir (+2-2)
  • (modified) llvm/test/CodeGen/Thumb2/LowOverheadLoops/wrong-vctp-opcode-liveout.mir (+2-2)
  • (modified) llvm/test/CodeGen/Thumb2/LowOverheadLoops/wrong-vctp-operand-liveout.mir (+2-2)
  • (modified) llvm/test/CodeGen/Thumb2/bti-pac-replace-1.mir (+2-2)
  • (modified) llvm/test/CodeGen/Thumb2/ifcvt-neon-deprecated.mir (+2-2)
  • (modified) llvm/test/CodeGen/Thumb2/mve-vpt-2-blocks-1-pred.mir (+2-2)
  • (modified) llvm/test/CodeGen/Thumb2/mve-vpt-2-blocks-2-preds.mir (+2-2)
  • (modified) llvm/test/CodeGen/Thumb2/mve-vpt-2-blocks-ctrl-flow.mir (+2-2)
  • (modified) llvm/test/CodeGen/Thumb2/mve-vpt-2-blocks-non-consecutive-ins.mir (+2-2)
  • (modified) llvm/test/CodeGen/Thumb2/mve-vpt-2-blocks.mir (+2-2)
  • (modified) llvm/test/CodeGen/Thumb2/mve-vpt-3-blocks-kill-vpr.mir (+2-2)
  • (modified) llvm/test/CodeGen/Thumb2/mve-vpt-block-1-ins.mir (+2-2)
  • (modified) llvm/test/CodeGen/Thumb2/mve-vpt-block-2-ins.mir (+2-2)
  • (modified) llvm/test/CodeGen/Thumb2/mve-vpt-block-4-ins.mir (+2-2)
  • (modified) llvm/test/CodeGen/Thumb2/mve-vpt-block-elses.mir (+2-2)
  • (modified) llvm/test/CodeGen/Thumb2/mve-vpt-block-fold-vcmp.mir (+2-2)
  • (modified) llvm/test/CodeGen/Thumb2/mve-vpt-block-optnone.mir (+2-2)
  • (modified) llvm/test/CodeGen/Thumb2/mve-vpt-preuse.mir (+2-2)
  • (modified) llvm/test/CodeGen/Thumb2/pipeliner-preserve-ties.mir (+2-2)
  • (modified) llvm/test/CodeGen/VE/Scalar/fold-imm-addsl.mir (+8-8)
  • (modified) llvm/test/CodeGen/VE/Scalar/fold-imm-cmpsl.mir (+4-4)
diff --git a/llvm/include/llvm/CodeGen/MIRYamlMapping.h b/llvm/include/llvm/CodeGen/MIRYamlMapping.h
index 09a6ca936fe1f4..be8a8e593ef922 100644
--- a/llvm/include/llvm/CodeGen/MIRYamlMapping.h
+++ b/llvm/include/llvm/CodeGen/MIRYamlMapping.h
@@ -610,6 +610,20 @@ LLVM_YAML_IS_SEQUENCE_VECTOR(llvm::yaml::MachineJumpTable::Entry)
 namespace llvm {
 namespace yaml {
 
+struct SRPEntry {
+  StringValue Point;
+
+  bool operator==(const SRPEntry &Other) const { return Point == Other.Point; }
+};
+
+using SaveRestorePoints = std::vector<SRPEntry>;
+
+template <> struct MappingTraits<SRPEntry> {
+  static void mapping(IO &YamlIO, SRPEntry &Entry) {
+    YamlIO.mapRequired("point", Entry.Point);
+  }
+};
+
 template <> struct MappingTraits<MachineJumpTable> {
   static void mapping(IO &YamlIO, MachineJumpTable &JT) {
     YamlIO.mapRequired("kind", JT.Kind);
@@ -618,6 +632,14 @@ template <> struct MappingTraits<MachineJumpTable> {
   }
 };
 
+} // namespace yaml
+} // namespace llvm
+
+LLVM_YAML_IS_SEQUENCE_VECTOR(llvm::yaml::SRPEntry)
+
+namespace llvm {
+namespace yaml {
+
 /// Serializable representation of MachineFrameInfo.
 ///
 /// Doesn't serialize attributes like 'StackAlignment', 'IsStackRealignable' and
@@ -645,8 +667,8 @@ struct MachineFrameInfo {
   bool HasTailCall = false;
   bool IsCalleeSavedInfoValid = false;
   unsigned LocalFrameSize = 0;
-  StringValue SavePoint;
-  StringValue RestorePoint;
+  SaveRestorePoints SavePoints;
+  SaveRestorePoints RestorePoints;
 
   bool operator==(const MachineFrameInfo &Other) const {
     return IsFrameAddressTaken == Other.IsFrameAddressTaken &&
@@ -667,7 +689,8 @@ struct MachineFrameInfo {
            HasMustTailInVarArgFunc == Other.HasMustTailInVarArgFunc &&
            HasTailCall == Other.HasTailCall &&
            LocalFrameSize == Other.LocalFrameSize &&
-           SavePoint == Other.SavePoint && RestorePoint == Other.RestorePoint &&
+           SavePoints == Other.SavePoints &&
+           RestorePoints == Other.RestorePoints &&
            IsCalleeSavedInfoValid == Other.IsCalleeSavedInfoValid;
   }
 };
@@ -699,10 +722,12 @@ template <> struct MappingTraits<MachineFrameInfo> {
     YamlIO.mapOptional("isCalleeSavedInfoValid", MFI.IsCalleeSavedInfoValid,
                        false);
     YamlIO.mapOptional("localFrameSize", MFI.LocalFrameSize, (unsigned)0);
-    YamlIO.mapOptional("savePoint", MFI.SavePoint,
-                       StringValue()); // Don't print it out when it's empty.
-    YamlIO.mapOptional("restorePoint", MFI.RestorePoint,
-                       StringValue()); // Don't print it out when it's empty.
+    YamlIO.mapOptional(
+        "savePoints", MFI.SavePoints,
+        SaveRestorePoints()); // Don't print it out when it's empty.
+    YamlIO.mapOptional(
+        "restorePoints", MFI.RestorePoints,
+        SaveRestorePoints()); // Don't print it out when it's empty.
   }
 };
 
diff --git a/llvm/include/llvm/CodeGen/MachineDominators.h b/llvm/include/llvm/CodeGen/MachineDominators.h
index 74cf94398736dd..88800d91ef51a9 100644
--- a/llvm/include/llvm/CodeGen/MachineDominators.h
+++ b/llvm/include/llvm/CodeGen/MachineDominators.h
@@ -185,6 +185,11 @@ class MachineDominatorTree : public DomTreeBase<MachineBasicBlock> {
     return Base::findNearestCommonDominator(A, B);
   }
 
+  /// Returns the nearest common dominator of the given blocks.
+  /// If that tree node is a virtual root, a nullptr will be returned.
+  MachineBasicBlock *
+  findNearestCommonDominator(ArrayRef<MachineBasicBlock *> Blocks) const;
+
   MachineDomTreeNode *operator[](MachineBasicBlock *BB) const {
     applySplitCriticalEdges();
     return Base::getNode(BB);
diff --git a/llvm/lib/CodeGen/MIRParser/MIRParser.cpp b/llvm/lib/CodeGen/MIRParser/MIRParser.cpp
index e2543f883f91ce..f7c1e162d2a96e 100644
--- a/llvm/lib/CodeGen/MIRParser/MIRParser.cpp
+++ b/llvm/lib/CodeGen/MIRParser/MIRParser.cpp
@@ -124,6 +124,10 @@ class MIRParserImpl {
   bool initializeFrameInfo(PerFunctionMIParsingState &PFS,
                            const yaml::MachineFunction &YamlMF);
 
+  bool initializeSaveRestorePoints(PerFunctionMIParsingState &PFS,
+                                   const yaml::SaveRestorePoints &YamlSRP,
+                                   bool IsSavePoints);
+
   bool initializeCallSiteInfo(PerFunctionMIParsingState &PFS,
                               const yaml::MachineFunction &YamlMF);
 
@@ -832,18 +836,9 @@ bool MIRParserImpl::initializeFrameInfo(PerFunctionMIParsingState &PFS,
   MFI.setHasTailCall(YamlMFI.HasTailCall);
   MFI.setCalleeSavedInfoValid(YamlMFI.IsCalleeSavedInfoValid);
   MFI.setLocalFrameSize(YamlMFI.LocalFrameSize);
-  if (!YamlMFI.SavePoint.Value.empty()) {
-    MachineBasicBlock *MBB = nullptr;
-    if (parseMBBReference(PFS, MBB, YamlMFI.SavePoint))
-      return true;
-    MFI.setSavePoint(MBB);
-  }
-  if (!YamlMFI.RestorePoint.Value.empty()) {
-    MachineBasicBlock *MBB = nullptr;
-    if (parseMBBReference(PFS, MBB, YamlMFI.RestorePoint))
-      return true;
-    MFI.setRestorePoint(MBB);
-  }
+  initializeSaveRestorePoints(PFS, YamlMFI.SavePoints, true /*IsSavePoints*/);
+  initializeSaveRestorePoints(PFS, YamlMFI.RestorePoints,
+                              false /*IsSavePoints*/);
 
   std::vector<CalleeSavedInfo> CSIInfo;
   // Initialize the fixed frame objects.
@@ -1058,8 +1053,28 @@ bool MIRParserImpl::initializeConstantPool(PerFunctionMIParsingState &PFS,
   return false;
 }
 
-bool MIRParserImpl::initializeJumpTableInfo(PerFunctionMIParsingState &PFS,
-    const yaml::MachineJumpTable &YamlJTI) {
+bool MIRParserImpl::initializeSaveRestorePoints(
+    PerFunctionMIParsingState &PFS, const yaml::SaveRestorePoints &YamlSRP,
+    bool IsSavePoints) {
+  MachineFunction &MF = PFS.MF;
+  MachineFrameInfo &MFI = MF.getFrameInfo();
+
+  if (!YamlSRP.empty()) {
+    const auto &Entry = YamlSRP.front();
+    const auto &MBBSource = Entry.Point;
+    MachineBasicBlock *MBB = nullptr;
+    if (parseMBBReference(PFS, MBB, MBBSource.Value))
+      return true;
+    if (IsSavePoints)
+      MFI.setSavePoint(MBB);
+    else
+      MFI.setRestorePoint(MBB);
+  }
+  return false;
+}
+
+bool MIRParserImpl::initializeJumpTableInfo(
+    PerFunctionMIParsingState &PFS, const yaml::MachineJumpTable &YamlJTI) {
   MachineJumpTableInfo *JTI = PFS.MF.getOrCreateJumpTableInfo(YamlJTI.Kind);
   for (const auto &Entry : YamlJTI.Entries) {
     std::vector<MachineBasicBlock *> Blocks;
diff --git a/llvm/lib/CodeGen/MIRPrinter.cpp b/llvm/lib/CodeGen/MIRPrinter.cpp
index c8f6341c1224d2..2d0728a6452808 100644
--- a/llvm/lib/CodeGen/MIRPrinter.cpp
+++ b/llvm/lib/CodeGen/MIRPrinter.cpp
@@ -118,6 +118,8 @@ class MIRPrinter {
                const TargetRegisterInfo *TRI);
   void convert(ModuleSlotTracker &MST, yaml::MachineFrameInfo &YamlMFI,
                const MachineFrameInfo &MFI);
+  void convert(ModuleSlotTracker &MST, yaml::SaveRestorePoints &YamlSRP,
+               MachineBasicBlock *SaveRestorePoint);
   void convert(yaml::MachineFunction &MF,
                const MachineConstantPool &ConstantPool);
   void convert(ModuleSlotTracker &MST, yaml::MachineJumpTable &YamlJTI,
@@ -392,14 +394,10 @@ void MIRPrinter::convert(ModuleSlotTracker &MST,
   YamlMFI.HasTailCall = MFI.hasTailCall();
   YamlMFI.IsCalleeSavedInfoValid = MFI.isCalleeSavedInfoValid();
   YamlMFI.LocalFrameSize = MFI.getLocalFrameSize();
-  if (MFI.getSavePoint()) {
-    raw_string_ostream StrOS(YamlMFI.SavePoint.Value);
-    StrOS << printMBBReference(*MFI.getSavePoint());
-  }
-  if (MFI.getRestorePoint()) {
-    raw_string_ostream StrOS(YamlMFI.RestorePoint.Value);
-    StrOS << printMBBReference(*MFI.getRestorePoint());
-  }
+  if (MFI.getSavePoint())
+    convert(MST, YamlMFI.SavePoints, MFI.getSavePoint());
+  if (MFI.getRestorePoint())
+    convert(MST, YamlMFI.RestorePoints, MFI.getRestorePoint());
 }
 
 void MIRPrinter::convertEntryValueObjects(yaml::MachineFunction &YMF,
@@ -618,6 +616,18 @@ void MIRPrinter::convert(yaml::MachineFunction &MF,
   }
 }
 
+void MIRPrinter::convert(ModuleSlotTracker &MST,
+                         yaml::SaveRestorePoints &YamlSRP,
+                         MachineBasicBlock *SRP) {
+  std::string Str;
+  yaml::SRPEntry Entry;
+  raw_string_ostream StrOS(Str);
+  StrOS << printMBBReference(*SRP);
+  Entry.Point = StrOS.str();
+  Str.clear();
+  YamlSRP.push_back(Entry);
+}
+
 void MIRPrinter::convert(ModuleSlotTracker &MST,
                          yaml::MachineJumpTable &YamlJTI,
                          const MachineJumpTableInfo &JTI) {
diff --git a/llvm/lib/CodeGen/MachineDominators.cpp b/llvm/lib/CodeGen/MachineDominators.cpp
index a2cc8fdfa7c9f9..384f90c6da66c0 100644
--- a/llvm/lib/CodeGen/MachineDominators.cpp
+++ b/llvm/lib/CodeGen/MachineDominators.cpp
@@ -189,3 +189,19 @@ void MachineDominatorTree::applySplitCriticalEdges() const {
   NewBBs.clear();
   CriticalEdgesToSplit.clear();
 }
+
+MachineBasicBlock *MachineDominatorTree::findNearestCommonDominator(
+    ArrayRef<MachineBasicBlock *> Blocks) const {
+  assert(!Blocks.empty());
+
+  MachineBasicBlock *NCD = Blocks.front();
+  for (MachineBasicBlock *BB : Blocks.drop_front()) {
+    NCD = Base::findNearestCommonDominator(NCD, BB);
+
+    // Stop when the root is reached.
+    if (Base::isVirtualRoot(Base::getNode(NCD)))
+      return nullptr;
+  }
+
+  return NCD;
+}
diff --git a/llvm/lib/Target/RISCV/RISCVFrameLowering.cpp b/llvm/lib/Target/RISCV/RISCVFrameLowering.cpp
index deb0b627225c64..0de1f1d821a6e2 100644
--- a/llvm/lib/Target/RISCV/RISCVFrameLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVFrameLowering.cpp
@@ -1607,6 +1607,8 @@ bool RISCVFrameLowering::assignCalleeSavedSpillSlots(
         int FrameIdx = MFI.CreateFixedSpillStackObject(Size, Offset);
         assert(FrameIdx < 0);
         CS.setFrameIdx(FrameIdx);
+        if (RISCVRegisterInfo::isRVVRegClass(RC))
+          MFI.setStackID(FrameIdx, TargetStackID::ScalableVector);
         continue;
       }
     }
@@ -1623,6 +1625,8 @@ bool RISCVFrameLowering::assignCalleeSavedSpillSlots(
     if ((unsigned)FrameIdx > MaxCSFrameIndex)
       MaxCSFrameIndex = FrameIdx;
     CS.setFrameIdx(FrameIdx);
+    if (RISCVRegisterInfo::isRVVRegClass(RC))
+      MFI.setStackID(FrameIdx, TargetStackID::ScalableVector);
   }
 
   // Allocate a fixed object that covers the full push or libcall size.
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/store-merging-debug.mir b/llvm/test/CodeGen/AArch64/GlobalISel/store-merging-debug.mir
index d52ef0f3da74c7..2e8f3c460b2fe7 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/store-merging-debug.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/store-merging-debug.mir
@@ -86,8 +86,8 @@ frameInfo:
   hasMustTailInVarArgFunc: false
   hasTailCall:     false
   localFrameSize:  0
-  savePoint:       ''
-  restorePoint:    ''
+  savePoints:      []
+  restorePoints:   []
 fixedStack:      []
 stack:           []
 callSites:       []
diff --git a/llvm/test/CodeGen/AArch64/aarch64-ldst-no-premature-sp-pop.mir b/llvm/test/CodeGen/AArch64/aarch64-ldst-no-premature-sp-pop.mir
index ba621cf77f9aed..07e80538e793f5 100644
--- a/llvm/test/CodeGen/AArch64/aarch64-ldst-no-premature-sp-pop.mir
+++ b/llvm/test/CodeGen/AArch64/aarch64-ldst-no-premature-sp-pop.mir
@@ -59,8 +59,8 @@ frameInfo:
   hasVAStart:      false
   hasMustTailInVarArgFunc: false
   localFrameSize:  16
-  savePoint:       ''
-  restorePoint:    ''
+  savePoints:      []
+  restorePoints:   []
 fixedStack:      []
 stack:
   - { id: 0, type: default, offset: -16, size: 16,
diff --git a/llvm/test/CodeGen/AArch64/aarch64-mov-debug-locs.mir b/llvm/test/CodeGen/AArch64/aarch64-mov-debug-locs.mir
index 16e2de751381ad..31589a86599ff3 100644
--- a/llvm/test/CodeGen/AArch64/aarch64-mov-debug-locs.mir
+++ b/llvm/test/CodeGen/AArch64/aarch64-mov-debug-locs.mir
@@ -157,8 +157,8 @@ frameInfo:
   hasVAStart:      false
   hasMustTailInVarArgFunc: false
   localFrameSize:  0
-  savePoint:       ''
-  restorePoint:    ''
+  savePoints:      []
+  restorePoints:   []
 fixedStack:      []
 stack:           
   - { id: 0, name: '', type: spill-slot, offset: -8, size: 8, alignment: 8, 
diff --git a/llvm/test/CodeGen/AArch64/aarch64st1.mir b/llvm/test/CodeGen/AArch64/aarch64st1.mir
index 22a024d37bc64f..439db1e97aa794 100644
--- a/llvm/test/CodeGen/AArch64/aarch64st1.mir
+++ b/llvm/test/CodeGen/AArch64/aarch64st1.mir
@@ -58,8 +58,8 @@ frameInfo:
   hasMustTailInVarArgFunc: false
   hasTailCall:     false
   localFrameSize:  0
-  savePoint:       ''
-  restorePoint:    ''
+  savePoints:      []
+  restorePoints:   []
 fixedStack:      []
 stack:
   - { id: 0, name: '', type: default, offset: 0, size: 4, alignment: 4, 
diff --git a/llvm/test/CodeGen/AArch64/cfi-fixup-multi-block-prologue.mir b/llvm/test/CodeGen/AArch64/cfi-fixup-multi-block-prologue.mir
index 31fa3832367bec..6851fdba1239a4 100644
--- a/llvm/test/CodeGen/AArch64/cfi-fixup-multi-block-prologue.mir
+++ b/llvm/test/CodeGen/AArch64/cfi-fixup-multi-block-prologue.mir
@@ -80,8 +80,8 @@ frameInfo:
   hasMustTailInVarArgFunc: false
   hasTailCall:     false
   localFrameSize:  30000
-  savePoint:       ''
-  restorePoint:    ''
+  savePoints:      []
+  restorePoints:   []
 fixedStack:      []
 stack:
   - { id: 0, name: p, type: default, offset: -30016, size: 30000, alignment: 1,
diff --git a/llvm/test/CodeGen/AArch64/cfi-fixup-multi-section.mir b/llvm/test/CodeGen/AArch64/cfi-fixup-multi-section.mir
index a24972d1388320..fe5c90a5e6dc54 100644
--- a/llvm/test/CodeGen/AArch64/cfi-fixup-multi-section.mir
+++ b/llvm/test/CodeGen/AArch64/cfi-fixup-multi-section.mir
@@ -47,8 +47,8 @@ frameInfo:
   hasMustTailInVarArgFunc: false
   hasTailCall:     false
   localFrameSize:  0
-  savePoint:       ''
-  restorePoint:    ''
+  savePoints:      []
+  restorePoints:   []
 fixedStack:      []
 stack:
   - { id: 0, name: '', type: spill-slot, offset: -16, size: 8, alignment: 16,
diff --git a/llvm/test/CodeGen/AArch64/cfi-fixup.mir b/llvm/test/CodeGen/AArch64/cfi-fixup.mir
index f522df6bb3fa06..dd75cec7f6e0be 100644
--- a/llvm/test/CodeGen/AArch64/cfi-fixup.mir
+++ b/llvm/test/CodeGen/AArch64/cfi-fixup.mir
@@ -65,8 +65,8 @@ frameInfo:
   hasMustTailInVarArgFunc: false
   hasTailCall:     false
   localFrameSize:  0
-  savePoint:       ''
-  restorePoint:    ''
+  savePoints:      []
+  restorePoints:   []
 fixedStack:      []
 stack:
   - { id: 0, name: '', type: spill-slot, offset: -16, size: 8, alignment: 16,
@@ -248,8 +248,8 @@ frameInfo:
   hasMustTailInVarArgFunc: false
   hasTailCall:     false
   localFrameSize:  0
-  savePoint:       ''
-  restorePoint:    ''
+  savePoints:      []
+  restorePoints:   []
 fixedStack:      []
 stack:
   - { id: 0, name: '', type: spill-slot, offset: -16, size: 8, alignment: 16,
@@ -403,8 +403,8 @@ frameInfo:
   hasMustTailInVarArgFunc: false
   hasTailCall:     false
   localFrameSize:  0
-  savePoint:       ''
-  restorePoint:    ''
+  savePoints:      []
+  restorePoints:   []
 fixedStack:      []
 stack:
   - { id: 0, name: '', type: spill-slot, offset: -16, size: 8, alignment: 16,
diff --git a/llvm/test/CodeGen/AArch64/dont-shrink-wrap-stack-mayloadorstore.mir b/llvm/test/CodeGen/AArch64/dont-shrink-wrap-stack-mayloadorstore.mir
index 1c4447bffd8729..85f8abcbf7fe60 100644
--- a/llvm/test/CodeGen/AArch64/dont-shrink-wrap-stack-mayloadorstore.mir
+++ b/llvm/test/CodeGen/AArch64/dont-shrink-wrap-stack-mayloadorstore.mir
@@ -6,17 +6,23 @@
  ; RUN: llc -x=mir -simplify-mir -run-pass=shrink-wrap -o - %s | FileCheck %s
  ; CHECK:      name:            compiler_pop_stack
  ; CHECK:      frameInfo:
- ; CHECK:      savePoint:       '%bb.1'
- ; CHECK:      restorePoint:    '%bb.7'
+ ; CHECK:        savePoints:
+ ; CHECK-NEXT:     - point:           '%bb.1'
+ ; CHECK:        restorePoints:
+ ; CHECK-NEXT:     - point:           '%bb.7'
  ; CHECK:      name:            compiler_pop_stack_no_memoperands
  ; CHECK:      frameInfo:
- ; CHECK:      savePoint:       '%bb.1'
- ; CHECK:      restorePoint:    '%bb.7'
+ ; CHECK:        savePoints:
+ ; CHECK-NEXT:     - point:           '%bb.1'
+ ; CHECK:        restorePoints:
+ ; CHECK-NEXT:     - point:           '%bb.7'
  ; CHECK:      name:            f
  ; CHECK:      frameInfo:
- ; CHECK:      savePoint:       '%bb.2'
- ; CHECK-NEXT: restorePoint:    '%bb.4'
- ; CHECK-NEXT: stack:
+ ; CHECK:        savePoints:
+ ; CHECK-NEXT:     - point:           '%bb.2'
+ ; CHECK:        restorePoints:
+ ; CHECK-NEXT:     - point:           '%bb.4'
+ ; CHECK:      stack:
 
   target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"
   target triple = "aarch64"
diff --git a/llvm/test/CodeGen/AArch64/early-ifcvt-regclass-mismatch.mir b/llvm/test/CodeGen/AArch64/early-ifcvt-regclass-mismatch.mir
index a7f67f8b682c3c..6324db0cb2c0ff 100644
--- a/llvm/test/CodeGen/AArch64/early-ifcvt-regclass-mismatch.mir
+++ b/llvm/test/CodeGen/AArch64/early-ifcvt-regclass-mismatch.mir
@@ -105,8 +105,8 @@ frameInfo:
   hasVAStart:      false
   hasMustTailInVarArgFunc: false
   localFrameSize:  0
-  savePoint:       ''
-  restorePoint:    ''
+  savePoints:      []
+  restorePoints:   []
 fixedStack:      []
 stack:           []
 callSites:       []
diff --git a/llvm/test/CodeGen/AArch64/emit_fneg_with_non_register_operand.mir b/llvm/test/CodeGen/AArch64/emit_fneg_with_non_register_operand.mir
index f9878adfe5e448..3c98a1a128413e 100644
--- a/llvm/test/CodeGen/AArch64/emit_fneg_with_non_register_operand.mir
+++ b/llvm/test/CodeGen/AArch64/emit_fneg_with_non_register_operand.mir
@@ -75,8 +75,8 @@ frameInfo:
   hasMustTailInVarArgFunc: false
   hasTailCall:     true
   localFrameSize:  0
-  savePoint:       ''
-  restorePoint:    ''
+  savePoints:      []
+  restorePoints:   []
 fixedStack:      []
 stack:           []
 entry_values:    []
diff --git a/llvm/test/CodeGen/AArch64/irg-nomem.mir b/llvm/test/CodeGen/AArch64/irg-nomem.mir
index 3b000fafbed46f..78438151405e66 100644
--- a/llvm/test/CodeGen/AArch64/irg-nomem.mir
+++ b/llvm/test/CodeGen/AArch64/irg-nomem.mir
@@ -47,8 +47,8 @@ frameInfo:
   hasVAStart:      false
   hasMustTailInVarArgFunc: false
   localFrameSize:  0
-  savePoint:       ''
-  restorePoint:    ''
+  savePoints:      []
+  restorePoints:   []
 fixedStack:      []
 stack:           []
 callSites:       []
diff --git a/llvm/test/CodeGen/AArch64/jump-table-duplicate.mir b/llvm/test/CodeGen/AArch64/jump-table-duplicate.mir
index a2532a854923f5..81cf5953895cab 100644
--- a/llvm/test/CodeGen/AArch64/jump-table-duplicate.mir
+++ b/llvm/test/CodeGen/AArch64/jump-table-duplicate.mir
@@ -92,8 +92,8 @@ frameInfo:
   hasVAStart:      false
   hasMustTailInVarArgFunc: false
   localFrameSize:  0
-  savePoint:       ''
-  restorePoint:    ''
+  savePoints:      []
+  restorePoints:   []
 fixedStack:      []
 stack:
   - { id: 0, name: '', type: spill-slot, offset: -8, size: 8, alignment: 8, 
diff --git a/llvm/test/CodeGen/AArch64/ldst-nopreidx-sp-redzone.mir b/llvm/test/CodeGen/AArch64/ldst-nopreidx-sp-redzone.mir
index f1f9e5fbc9b087..b431de2d9b35b3 100644
--- a/llvm/test/CodeGen/AArch64/ldst-nopreidx-sp-redzone.mir
+++ b/llvm/test/CodeGen/AArch64/ldst-nopreidx-sp-redzone.mir
@@ -103,8 +103,8 @@ frameInfo:
   hasVAStart:      false
   hasMustTailInVarArgFunc: false
   localFrameSize:  480
-  savePoint:       ''
-  restorePoint:    ''
+  savePoints:      []
+  restorePoints:   []
 fixedStack:      []
 stack:
   - { id: 0, name: StackGuardSlot, type: default, offset: -40, size: 8, 
@@ -216,8 +216,8 @@ frameInfo:
   hasVAStart:      false
   hasMustTailInVarArgFunc: false
   localFrameSize:  480
-  savePoint:       ''
-  restorePoint:    ''
+  savePoints:      []
+  restorePoints:   []
 fixedStack:      []
 stack:
   - { id: 0, name: StackGuardSlot, type: default, offset: -40, size: 8, 
@@ -327,8 +327,8 @@ frameInfo:
   hasVAStart:      false
   hasMustTailInVarArgFunc: false
   localFrameSize:  480
-  savePoint:       ''
-  restorePoint:    ''
+  savePoints:      []
+  restorePoints:   []
 fixedStack:      []
 stack:
   - { id: 0, name: StackGuardSlot, type: default, offset: -40, size: 8, 
diff --git a/llvm/test/CodeGen/AArch64/live-debugvalues-sve.mir b/llvm/test/CodeGen/AArch64/live-debugvalues-sve.mir
index 612453ab53f438..4be16228814a3b 100644
--- a/llvm/test/CodeGen/AArch64/live-debugvalues-sve.mir
+++ b/llvm/test/CodeGen/AArch64/live-debugvalues-sve.mir
@@ -120,8 +120,10 @@ frameInfo:
   adjustsStack:    true
   hasC...
[truncated]

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llvmbot commented Dec 10, 2024

@llvm/pr-subscribers-backend-nvptx

Author: Elizaveta Noskova (enoskova-sc)

Changes

Currently mir supports only one save and one restore point specification:

  savePoint:       '%bb.1'
  restorePoint:    '%bb.2'

This patch provide possibility to have multiple save and multiple restore points in mir:

  savePoints:
    - point:           '%bb.1'
  restorePoints:
    - point:           '%bb.2'

Shrink-Wrap points split Part 3.

Part 1: #117862
Part 2: #119355


Patch is 276.31 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/119357.diff

340 Files Affected:

  • (modified) llvm/include/llvm/CodeGen/MIRYamlMapping.h (+32-7)
  • (modified) llvm/include/llvm/CodeGen/MachineDominators.h (+5)
  • (modified) llvm/lib/CodeGen/MIRParser/MIRParser.cpp (+29-14)
  • (modified) llvm/lib/CodeGen/MIRPrinter.cpp (+18-8)
  • (modified) llvm/lib/CodeGen/MachineDominators.cpp (+16)
  • (modified) llvm/lib/Target/RISCV/RISCVFrameLowering.cpp (+4)
  • (modified) llvm/test/CodeGen/AArch64/GlobalISel/store-merging-debug.mir (+2-2)
  • (modified) llvm/test/CodeGen/AArch64/aarch64-ldst-no-premature-sp-pop.mir (+2-2)
  • (modified) llvm/test/CodeGen/AArch64/aarch64-mov-debug-locs.mir (+2-2)
  • (modified) llvm/test/CodeGen/AArch64/aarch64st1.mir (+2-2)
  • (modified) llvm/test/CodeGen/AArch64/cfi-fixup-multi-block-prologue.mir (+2-2)
  • (modified) llvm/test/CodeGen/AArch64/cfi-fixup-multi-section.mir (+2-2)
  • (modified) llvm/test/CodeGen/AArch64/cfi-fixup.mir (+6-6)
  • (modified) llvm/test/CodeGen/AArch64/dont-shrink-wrap-stack-mayloadorstore.mir (+13-7)
  • (modified) llvm/test/CodeGen/AArch64/early-ifcvt-regclass-mismatch.mir (+2-2)
  • (modified) llvm/test/CodeGen/AArch64/emit_fneg_with_non_register_operand.mir (+2-2)
  • (modified) llvm/test/CodeGen/AArch64/irg-nomem.mir (+2-2)
  • (modified) llvm/test/CodeGen/AArch64/jump-table-duplicate.mir (+2-2)
  • (modified) llvm/test/CodeGen/AArch64/ldst-nopreidx-sp-redzone.mir (+6-6)
  • (modified) llvm/test/CodeGen/AArch64/live-debugvalues-sve.mir (+4-2)
  • (modified) llvm/test/CodeGen/AArch64/loop-sink-limit.mir (+2-2)
  • (modified) llvm/test/CodeGen/AArch64/loop-sink.mir (+16-16)
  • (modified) llvm/test/CodeGen/AArch64/machine-latecleanup-inlineasm.mir (+2-2)
  • (modified) llvm/test/CodeGen/AArch64/nested-iv-regalloc.mir (+2-2)
  • (modified) llvm/test/CodeGen/AArch64/regalloc-last-chance-recolor-with-split.mir (+2-2)
  • (modified) llvm/test/CodeGen/AArch64/shrinkwrap-split-restore-point.mir (+2-2)
  • (modified) llvm/test/CodeGen/AArch64/sink-and-fold-drop-dbg.mir (+2-2)
  • (modified) llvm/test/CodeGen/AArch64/sink-and-fold-illegal-shift.mir (+2-2)
  • (modified) llvm/test/CodeGen/AArch64/sink-and-fold-preserve-debugloc.mir (+4-4)
  • (modified) llvm/test/CodeGen/AArch64/split-deadloop.mir (+2-2)
  • (modified) llvm/test/CodeGen/AArch64/stack-probing-last-in-block.mir (+2-2)
  • (modified) llvm/test/CodeGen/AArch64/tail-dup-redundant-phi.mir (+2-2)
  • (modified) llvm/test/CodeGen/AArch64/taildup-addrtaken.mir (+2-2)
  • (modified) llvm/test/CodeGen/AArch64/wineh-frame-predecrement.mir (+2-2)
  • (modified) llvm/test/CodeGen/AArch64/wineh-frame-scavenge.mir (+2-2)
  • (modified) llvm/test/CodeGen/AArch64/wineh-frame1.mir (+2-2)
  • (modified) llvm/test/CodeGen/AArch64/wineh-frame2.mir (+2-2)
  • (modified) llvm/test/CodeGen/AArch64/wineh-frame3.mir (+2-2)
  • (modified) llvm/test/CodeGen/AArch64/wineh-frame4.mir (+2-2)
  • (modified) llvm/test/CodeGen/AArch64/wineh-frame5.mir (+2-2)
  • (modified) llvm/test/CodeGen/AArch64/wineh-frame6.mir (+2-2)
  • (modified) llvm/test/CodeGen/AArch64/wineh-frame7.mir (+2-2)
  • (modified) llvm/test/CodeGen/AArch64/wineh-frame8.mir (+2-2)
  • (modified) llvm/test/CodeGen/AArch64/wineh-save-lrpair1.mir (+2-2)
  • (modified) llvm/test/CodeGen/AArch64/wineh-save-lrpair2.mir (+2-2)
  • (modified) llvm/test/CodeGen/AArch64/wineh-save-lrpair3.mir (+2-2)
  • (modified) llvm/test/CodeGen/AArch64/wineh2.mir (+2-2)
  • (modified) llvm/test/CodeGen/AArch64/wineh3.mir (+2-2)
  • (modified) llvm/test/CodeGen/AArch64/wineh4.mir (+2-2)
  • (modified) llvm/test/CodeGen/AArch64/wineh5.mir (+2-2)
  • (modified) llvm/test/CodeGen/AArch64/wineh6.mir (+2-2)
  • (modified) llvm/test/CodeGen/AArch64/wineh7.mir (+2-2)
  • (modified) llvm/test/CodeGen/AArch64/wineh8.mir (+2-2)
  • (modified) llvm/test/CodeGen/AArch64/wineh9.mir (+2-2)
  • (modified) llvm/test/CodeGen/AArch64/wineh_shrinkwrap.mir (+2-2)
  • (modified) llvm/test/CodeGen/AMDGPU/memory-legalizer-multiple-mem-operands-nontemporal-1.mir (+2-2)
  • (modified) llvm/test/CodeGen/AMDGPU/memory-legalizer-multiple-mem-operands-nontemporal-2.mir (+2-2)
  • (modified) llvm/test/CodeGen/ARM/cmse-vlldm-no-reorder.mir (+2-2)
  • (modified) llvm/test/CodeGen/ARM/codesize-ifcvt.mir (+6-6)
  • (modified) llvm/test/CodeGen/ARM/constant-island-movwt.mir (+2-2)
  • (modified) llvm/test/CodeGen/ARM/constant-islands-cfg.mir (+2-2)
  • (modified) llvm/test/CodeGen/ARM/constant-islands-split-IT.mir (+2-2)
  • (modified) llvm/test/CodeGen/ARM/execute-only-save-cpsr.mir (+8-8)
  • (modified) llvm/test/CodeGen/ARM/fp16-litpool2-arm.mir (+2-2)
  • (modified) llvm/test/CodeGen/ARM/fp16-litpool3-arm.mir (+2-2)
  • (modified) llvm/test/CodeGen/ARM/inlineasmbr-if-cvt.mir (+2-2)
  • (modified) llvm/test/CodeGen/ARM/invalidated-save-point.ll (+2-2)
  • (modified) llvm/test/CodeGen/ARM/jump-table-dbg-value.mir (+2-2)
  • (modified) llvm/test/CodeGen/ARM/stack_frame_offset.mir (+6-6)
  • (modified) llvm/test/CodeGen/Hexagon/cext-opt-block-addr.mir (+4-4)
  • (modified) llvm/test/CodeGen/Hexagon/early-if-predicator.mir (+2-2)
  • (modified) llvm/test/CodeGen/Hexagon/machine-sink-float-usr.mir (+4-4)
  • (modified) llvm/test/CodeGen/Hexagon/pipeliner/swp-phi-start.mir (+2-2)
  • (modified) llvm/test/CodeGen/MIR/ARM/thumb2-sub-sp-t3.mir (+2-2)
  • (modified) llvm/test/CodeGen/MIR/Generic/frame-info.mir (+2-2)
  • (modified) llvm/test/CodeGen/MIR/Hexagon/addrmode-opt-nonreaching.mir (+2-2)
  • (modified) llvm/test/CodeGen/MIR/RISCV/machine-function-info.mir (+2-2)
  • (modified) llvm/test/CodeGen/MIR/X86/branch-folder-with-label.mir (+6-6)
  • (modified) llvm/test/CodeGen/MIR/X86/diexpr-win32.mir (+4-4)
  • (modified) llvm/test/CodeGen/MIR/X86/fake-use-tailcall.mir (+2-2)
  • (modified) llvm/test/CodeGen/MIR/X86/frame-info-save-restore-points.mir (+8-4)
  • (modified) llvm/test/CodeGen/MIR/X86/inline-asm-rm-exhaustion.mir (+6-6)
  • (modified) llvm/test/CodeGen/Mips/delay-slot-filler-bundled-insts-def-use.mir (+2-2)
  • (modified) llvm/test/CodeGen/Mips/delay-slot-filler-bundled-insts.mir (+2-2)
  • (modified) llvm/test/CodeGen/Mips/indirect-jump-hazard/guards-verify-call.mir (+2-2)
  • (modified) llvm/test/CodeGen/Mips/indirect-jump-hazard/guards-verify-tailcall.mir (+2-2)
  • (modified) llvm/test/CodeGen/Mips/instverify/dext-pos.mir (+2-2)
  • (modified) llvm/test/CodeGen/Mips/instverify/dext-size.mir (+2-2)
  • (modified) llvm/test/CodeGen/Mips/instverify/dextm-pos-size.mir (+2-2)
  • (modified) llvm/test/CodeGen/Mips/instverify/dextm-pos.mir (+2-2)
  • (modified) llvm/test/CodeGen/Mips/instverify/dextm-size.mir (+2-2)
  • (modified) llvm/test/CodeGen/Mips/instverify/dextu-pos-size.mir (+2-2)
  • (modified) llvm/test/CodeGen/Mips/instverify/dextu-pos.mir (+2-2)
  • (modified) llvm/test/CodeGen/Mips/instverify/dextu-size-valid.mir (+2-2)
  • (modified) llvm/test/CodeGen/Mips/instverify/dextu-size.mir (+2-2)
  • (modified) llvm/test/CodeGen/Mips/instverify/dins-pos-size.mir (+2-2)
  • (modified) llvm/test/CodeGen/Mips/instverify/dins-pos.mir (+2-2)
  • (modified) llvm/test/CodeGen/Mips/instverify/dins-size.mir (+2-2)
  • (modified) llvm/test/CodeGen/Mips/instverify/dinsm-pos-size.mir (+2-2)
  • (modified) llvm/test/CodeGen/Mips/instverify/dinsm-pos.mir (+2-2)
  • (modified) llvm/test/CodeGen/Mips/instverify/dinsm-size.mir (+2-2)
  • (modified) llvm/test/CodeGen/Mips/instverify/dinsu-pos-size.mir (+2-2)
  • (modified) llvm/test/CodeGen/Mips/instverify/dinsu-pos.mir (+2-2)
  • (modified) llvm/test/CodeGen/Mips/instverify/dinsu-size.mir (+2-2)
  • (modified) llvm/test/CodeGen/Mips/instverify/ext-pos-size.mir (+2-2)
  • (modified) llvm/test/CodeGen/Mips/instverify/ext-pos.mir (+2-2)
  • (modified) llvm/test/CodeGen/Mips/instverify/ext-size.mir (+2-2)
  • (modified) llvm/test/CodeGen/Mips/instverify/ins-pos-size.mir (+2-2)
  • (modified) llvm/test/CodeGen/Mips/instverify/ins-pos.mir (+2-2)
  • (modified) llvm/test/CodeGen/Mips/instverify/ins-size.mir (+2-2)
  • (modified) llvm/test/CodeGen/Mips/longbranch/branch-limits-fp-micromips.mir (+4-4)
  • (modified) llvm/test/CodeGen/Mips/longbranch/branch-limits-fp-micromipsr6.mir (+4-4)
  • (modified) llvm/test/CodeGen/Mips/longbranch/branch-limits-fp-mips.mir (+4-4)
  • (modified) llvm/test/CodeGen/Mips/longbranch/branch-limits-fp-mipsr6.mir (+4-4)
  • (modified) llvm/test/CodeGen/Mips/longbranch/branch-limits-int-microMIPS.mir (+16-16)
  • (modified) llvm/test/CodeGen/Mips/longbranch/branch-limits-int-micromipsr6.mir (+24-24)
  • (modified) llvm/test/CodeGen/Mips/longbranch/branch-limits-int-mips64.mir (+12-12)
  • (modified) llvm/test/CodeGen/Mips/longbranch/branch-limits-int-mips64r6.mir (+24-24)
  • (modified) llvm/test/CodeGen/Mips/longbranch/branch-limits-int-mipsr6.mir (+24-24)
  • (modified) llvm/test/CodeGen/Mips/longbranch/branch-limits-int.mir (+12-12)
  • (modified) llvm/test/CodeGen/Mips/longbranch/branch-limits-msa.mir (+20-20)
  • (modified) llvm/test/CodeGen/Mips/micromips-eva.mir (+4-4)
  • (modified) llvm/test/CodeGen/Mips/micromips-short-delay-slot.mir (+2-2)
  • (modified) llvm/test/CodeGen/Mips/micromips-sizereduction/micromips-lwp-swp.mir (+8-8)
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  • (modified) llvm/test/CodeGen/Thumb2/LowOverheadLoops/vaddv.mir (+38-38)
  • (modified) llvm/test/CodeGen/Thumb2/LowOverheadLoops/vctp-add-operand-liveout.mir (+2-2)
  • (modified) llvm/test/CodeGen/Thumb2/LowOverheadLoops/vctp-in-vpt-2.mir (+2-2)
  • (modified) llvm/test/CodeGen/Thumb2/LowOverheadLoops/vctp-in-vpt.mir (+8-8)
  • (modified) llvm/test/CodeGen/Thumb2/LowOverheadLoops/vctp-subi3.mir (+2-2)
  • (modified) llvm/test/CodeGen/Thumb2/LowOverheadLoops/vctp-subri.mir (+2-2)
  • (modified) llvm/test/CodeGen/Thumb2/LowOverheadLoops/vctp-subri12.mir (+2-2)
  • (modified) llvm/test/CodeGen/Thumb2/LowOverheadLoops/vctp16-reduce.mir (+2-2)
  • (modified) llvm/test/CodeGen/Thumb2/LowOverheadLoops/vmaxmin_vpred_r.mir (+2-2)
  • (modified) llvm/test/CodeGen/Thumb2/LowOverheadLoops/vmldava_in_vpt.mir (+2-2)
  • (modified) llvm/test/CodeGen/Thumb2/LowOverheadLoops/vpt-block-debug.mir (+2-2)
  • (modified) llvm/test/CodeGen/Thumb2/LowOverheadLoops/vpt-blocks.mir (+14-14)
  • (modified) llvm/test/CodeGen/Thumb2/LowOverheadLoops/while-negative-offset.mir (+2-2)
  • (modified) llvm/test/CodeGen/Thumb2/LowOverheadLoops/while.mir (+2-2)
  • (modified) llvm/test/CodeGen/Thumb2/LowOverheadLoops/wlstp.mir (+6-6)
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  • (modified) llvm/test/CodeGen/Thumb2/bti-pac-replace-1.mir (+2-2)
  • (modified) llvm/test/CodeGen/Thumb2/ifcvt-neon-deprecated.mir (+2-2)
  • (modified) llvm/test/CodeGen/Thumb2/mve-vpt-2-blocks-1-pred.mir (+2-2)
  • (modified) llvm/test/CodeGen/Thumb2/mve-vpt-2-blocks-2-preds.mir (+2-2)
  • (modified) llvm/test/CodeGen/Thumb2/mve-vpt-2-blocks-ctrl-flow.mir (+2-2)
  • (modified) llvm/test/CodeGen/Thumb2/mve-vpt-2-blocks-non-consecutive-ins.mir (+2-2)
  • (modified) llvm/test/CodeGen/Thumb2/mve-vpt-2-blocks.mir (+2-2)
  • (modified) llvm/test/CodeGen/Thumb2/mve-vpt-3-blocks-kill-vpr.mir (+2-2)
  • (modified) llvm/test/CodeGen/Thumb2/mve-vpt-block-1-ins.mir (+2-2)
  • (modified) llvm/test/CodeGen/Thumb2/mve-vpt-block-2-ins.mir (+2-2)
  • (modified) llvm/test/CodeGen/Thumb2/mve-vpt-block-4-ins.mir (+2-2)
  • (modified) llvm/test/CodeGen/Thumb2/mve-vpt-block-elses.mir (+2-2)
  • (modified) llvm/test/CodeGen/Thumb2/mve-vpt-block-fold-vcmp.mir (+2-2)
  • (modified) llvm/test/CodeGen/Thumb2/mve-vpt-block-optnone.mir (+2-2)
  • (modified) llvm/test/CodeGen/Thumb2/mve-vpt-preuse.mir (+2-2)
  • (modified) llvm/test/CodeGen/Thumb2/pipeliner-preserve-ties.mir (+2-2)
  • (modified) llvm/test/CodeGen/VE/Scalar/fold-imm-addsl.mir (+8-8)
  • (modified) llvm/test/CodeGen/VE/Scalar/fold-imm-cmpsl.mir (+4-4)
diff --git a/llvm/include/llvm/CodeGen/MIRYamlMapping.h b/llvm/include/llvm/CodeGen/MIRYamlMapping.h
index 09a6ca936fe1f4..be8a8e593ef922 100644
--- a/llvm/include/llvm/CodeGen/MIRYamlMapping.h
+++ b/llvm/include/llvm/CodeGen/MIRYamlMapping.h
@@ -610,6 +610,20 @@ LLVM_YAML_IS_SEQUENCE_VECTOR(llvm::yaml::MachineJumpTable::Entry)
 namespace llvm {
 namespace yaml {
 
+struct SRPEntry {
+  StringValue Point;
+
+  bool operator==(const SRPEntry &Other) const { return Point == Other.Point; }
+};
+
+using SaveRestorePoints = std::vector<SRPEntry>;
+
+template <> struct MappingTraits<SRPEntry> {
+  static void mapping(IO &YamlIO, SRPEntry &Entry) {
+    YamlIO.mapRequired("point", Entry.Point);
+  }
+};
+
 template <> struct MappingTraits<MachineJumpTable> {
   static void mapping(IO &YamlIO, MachineJumpTable &JT) {
     YamlIO.mapRequired("kind", JT.Kind);
@@ -618,6 +632,14 @@ template <> struct MappingTraits<MachineJumpTable> {
   }
 };
 
+} // namespace yaml
+} // namespace llvm
+
+LLVM_YAML_IS_SEQUENCE_VECTOR(llvm::yaml::SRPEntry)
+
+namespace llvm {
+namespace yaml {
+
 /// Serializable representation of MachineFrameInfo.
 ///
 /// Doesn't serialize attributes like 'StackAlignment', 'IsStackRealignable' and
@@ -645,8 +667,8 @@ struct MachineFrameInfo {
   bool HasTailCall = false;
   bool IsCalleeSavedInfoValid = false;
   unsigned LocalFrameSize = 0;
-  StringValue SavePoint;
-  StringValue RestorePoint;
+  SaveRestorePoints SavePoints;
+  SaveRestorePoints RestorePoints;
 
   bool operator==(const MachineFrameInfo &Other) const {
     return IsFrameAddressTaken == Other.IsFrameAddressTaken &&
@@ -667,7 +689,8 @@ struct MachineFrameInfo {
            HasMustTailInVarArgFunc == Other.HasMustTailInVarArgFunc &&
            HasTailCall == Other.HasTailCall &&
            LocalFrameSize == Other.LocalFrameSize &&
-           SavePoint == Other.SavePoint && RestorePoint == Other.RestorePoint &&
+           SavePoints == Other.SavePoints &&
+           RestorePoints == Other.RestorePoints &&
            IsCalleeSavedInfoValid == Other.IsCalleeSavedInfoValid;
   }
 };
@@ -699,10 +722,12 @@ template <> struct MappingTraits<MachineFrameInfo> {
     YamlIO.mapOptional("isCalleeSavedInfoValid", MFI.IsCalleeSavedInfoValid,
                        false);
     YamlIO.mapOptional("localFrameSize", MFI.LocalFrameSize, (unsigned)0);
-    YamlIO.mapOptional("savePoint", MFI.SavePoint,
-                       StringValue()); // Don't print it out when it's empty.
-    YamlIO.mapOptional("restorePoint", MFI.RestorePoint,
-                       StringValue()); // Don't print it out when it's empty.
+    YamlIO.mapOptional(
+        "savePoints", MFI.SavePoints,
+        SaveRestorePoints()); // Don't print it out when it's empty.
+    YamlIO.mapOptional(
+        "restorePoints", MFI.RestorePoints,
+        SaveRestorePoints()); // Don't print it out when it's empty.
   }
 };
 
diff --git a/llvm/include/llvm/CodeGen/MachineDominators.h b/llvm/include/llvm/CodeGen/MachineDominators.h
index 74cf94398736dd..88800d91ef51a9 100644
--- a/llvm/include/llvm/CodeGen/MachineDominators.h
+++ b/llvm/include/llvm/CodeGen/MachineDominators.h
@@ -185,6 +185,11 @@ class MachineDominatorTree : public DomTreeBase<MachineBasicBlock> {
     return Base::findNearestCommonDominator(A, B);
   }
 
+  /// Returns the nearest common dominator of the given blocks.
+  /// If that tree node is a virtual root, a nullptr will be returned.
+  MachineBasicBlock *
+  findNearestCommonDominator(ArrayRef<MachineBasicBlock *> Blocks) const;
+
   MachineDomTreeNode *operator[](MachineBasicBlock *BB) const {
     applySplitCriticalEdges();
     return Base::getNode(BB);
diff --git a/llvm/lib/CodeGen/MIRParser/MIRParser.cpp b/llvm/lib/CodeGen/MIRParser/MIRParser.cpp
index e2543f883f91ce..f7c1e162d2a96e 100644
--- a/llvm/lib/CodeGen/MIRParser/MIRParser.cpp
+++ b/llvm/lib/CodeGen/MIRParser/MIRParser.cpp
@@ -124,6 +124,10 @@ class MIRParserImpl {
   bool initializeFrameInfo(PerFunctionMIParsingState &PFS,
                            const yaml::MachineFunction &YamlMF);
 
+  bool initializeSaveRestorePoints(PerFunctionMIParsingState &PFS,
+                                   const yaml::SaveRestorePoints &YamlSRP,
+                                   bool IsSavePoints);
+
   bool initializeCallSiteInfo(PerFunctionMIParsingState &PFS,
                               const yaml::MachineFunction &YamlMF);
 
@@ -832,18 +836,9 @@ bool MIRParserImpl::initializeFrameInfo(PerFunctionMIParsingState &PFS,
   MFI.setHasTailCall(YamlMFI.HasTailCall);
   MFI.setCalleeSavedInfoValid(YamlMFI.IsCalleeSavedInfoValid);
   MFI.setLocalFrameSize(YamlMFI.LocalFrameSize);
-  if (!YamlMFI.SavePoint.Value.empty()) {
-    MachineBasicBlock *MBB = nullptr;
-    if (parseMBBReference(PFS, MBB, YamlMFI.SavePoint))
-      return true;
-    MFI.setSavePoint(MBB);
-  }
-  if (!YamlMFI.RestorePoint.Value.empty()) {
-    MachineBasicBlock *MBB = nullptr;
-    if (parseMBBReference(PFS, MBB, YamlMFI.RestorePoint))
-      return true;
-    MFI.setRestorePoint(MBB);
-  }
+  initializeSaveRestorePoints(PFS, YamlMFI.SavePoints, true /*IsSavePoints*/);
+  initializeSaveRestorePoints(PFS, YamlMFI.RestorePoints,
+                              false /*IsSavePoints*/);
 
   std::vector<CalleeSavedInfo> CSIInfo;
   // Initialize the fixed frame objects.
@@ -1058,8 +1053,28 @@ bool MIRParserImpl::initializeConstantPool(PerFunctionMIParsingState &PFS,
   return false;
 }
 
-bool MIRParserImpl::initializeJumpTableInfo(PerFunctionMIParsingState &PFS,
-    const yaml::MachineJumpTable &YamlJTI) {
+bool MIRParserImpl::initializeSaveRestorePoints(
+    PerFunctionMIParsingState &PFS, const yaml::SaveRestorePoints &YamlSRP,
+    bool IsSavePoints) {
+  MachineFunction &MF = PFS.MF;
+  MachineFrameInfo &MFI = MF.getFrameInfo();
+
+  if (!YamlSRP.empty()) {
+    const auto &Entry = YamlSRP.front();
+    const auto &MBBSource = Entry.Point;
+    MachineBasicBlock *MBB = nullptr;
+    if (parseMBBReference(PFS, MBB, MBBSource.Value))
+      return true;
+    if (IsSavePoints)
+      MFI.setSavePoint(MBB);
+    else
+      MFI.setRestorePoint(MBB);
+  }
+  return false;
+}
+
+bool MIRParserImpl::initializeJumpTableInfo(
+    PerFunctionMIParsingState &PFS, const yaml::MachineJumpTable &YamlJTI) {
   MachineJumpTableInfo *JTI = PFS.MF.getOrCreateJumpTableInfo(YamlJTI.Kind);
   for (const auto &Entry : YamlJTI.Entries) {
     std::vector<MachineBasicBlock *> Blocks;
diff --git a/llvm/lib/CodeGen/MIRPrinter.cpp b/llvm/lib/CodeGen/MIRPrinter.cpp
index c8f6341c1224d2..2d0728a6452808 100644
--- a/llvm/lib/CodeGen/MIRPrinter.cpp
+++ b/llvm/lib/CodeGen/MIRPrinter.cpp
@@ -118,6 +118,8 @@ class MIRPrinter {
                const TargetRegisterInfo *TRI);
   void convert(ModuleSlotTracker &MST, yaml::MachineFrameInfo &YamlMFI,
                const MachineFrameInfo &MFI);
+  void convert(ModuleSlotTracker &MST, yaml::SaveRestorePoints &YamlSRP,
+               MachineBasicBlock *SaveRestorePoint);
   void convert(yaml::MachineFunction &MF,
                const MachineConstantPool &ConstantPool);
   void convert(ModuleSlotTracker &MST, yaml::MachineJumpTable &YamlJTI,
@@ -392,14 +394,10 @@ void MIRPrinter::convert(ModuleSlotTracker &MST,
   YamlMFI.HasTailCall = MFI.hasTailCall();
   YamlMFI.IsCalleeSavedInfoValid = MFI.isCalleeSavedInfoValid();
   YamlMFI.LocalFrameSize = MFI.getLocalFrameSize();
-  if (MFI.getSavePoint()) {
-    raw_string_ostream StrOS(YamlMFI.SavePoint.Value);
-    StrOS << printMBBReference(*MFI.getSavePoint());
-  }
-  if (MFI.getRestorePoint()) {
-    raw_string_ostream StrOS(YamlMFI.RestorePoint.Value);
-    StrOS << printMBBReference(*MFI.getRestorePoint());
-  }
+  if (MFI.getSavePoint())
+    convert(MST, YamlMFI.SavePoints, MFI.getSavePoint());
+  if (MFI.getRestorePoint())
+    convert(MST, YamlMFI.RestorePoints, MFI.getRestorePoint());
 }
 
 void MIRPrinter::convertEntryValueObjects(yaml::MachineFunction &YMF,
@@ -618,6 +616,18 @@ void MIRPrinter::convert(yaml::MachineFunction &MF,
   }
 }
 
+void MIRPrinter::convert(ModuleSlotTracker &MST,
+                         yaml::SaveRestorePoints &YamlSRP,
+                         MachineBasicBlock *SRP) {
+  std::string Str;
+  yaml::SRPEntry Entry;
+  raw_string_ostream StrOS(Str);
+  StrOS << printMBBReference(*SRP);
+  Entry.Point = StrOS.str();
+  Str.clear();
+  YamlSRP.push_back(Entry);
+}
+
 void MIRPrinter::convert(ModuleSlotTracker &MST,
                          yaml::MachineJumpTable &YamlJTI,
                          const MachineJumpTableInfo &JTI) {
diff --git a/llvm/lib/CodeGen/MachineDominators.cpp b/llvm/lib/CodeGen/MachineDominators.cpp
index a2cc8fdfa7c9f9..384f90c6da66c0 100644
--- a/llvm/lib/CodeGen/MachineDominators.cpp
+++ b/llvm/lib/CodeGen/MachineDominators.cpp
@@ -189,3 +189,19 @@ void MachineDominatorTree::applySplitCriticalEdges() const {
   NewBBs.clear();
   CriticalEdgesToSplit.clear();
 }
+
+MachineBasicBlock *MachineDominatorTree::findNearestCommonDominator(
+    ArrayRef<MachineBasicBlock *> Blocks) const {
+  assert(!Blocks.empty());
+
+  MachineBasicBlock *NCD = Blocks.front();
+  for (MachineBasicBlock *BB : Blocks.drop_front()) {
+    NCD = Base::findNearestCommonDominator(NCD, BB);
+
+    // Stop when the root is reached.
+    if (Base::isVirtualRoot(Base::getNode(NCD)))
+      return nullptr;
+  }
+
+  return NCD;
+}
diff --git a/llvm/lib/Target/RISCV/RISCVFrameLowering.cpp b/llvm/lib/Target/RISCV/RISCVFrameLowering.cpp
index deb0b627225c64..0de1f1d821a6e2 100644
--- a/llvm/lib/Target/RISCV/RISCVFrameLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVFrameLowering.cpp
@@ -1607,6 +1607,8 @@ bool RISCVFrameLowering::assignCalleeSavedSpillSlots(
         int FrameIdx = MFI.CreateFixedSpillStackObject(Size, Offset);
         assert(FrameIdx < 0);
         CS.setFrameIdx(FrameIdx);
+        if (RISCVRegisterInfo::isRVVRegClass(RC))
+          MFI.setStackID(FrameIdx, TargetStackID::ScalableVector);
         continue;
       }
     }
@@ -1623,6 +1625,8 @@ bool RISCVFrameLowering::assignCalleeSavedSpillSlots(
     if ((unsigned)FrameIdx > MaxCSFrameIndex)
       MaxCSFrameIndex = FrameIdx;
     CS.setFrameIdx(FrameIdx);
+    if (RISCVRegisterInfo::isRVVRegClass(RC))
+      MFI.setStackID(FrameIdx, TargetStackID::ScalableVector);
   }
 
   // Allocate a fixed object that covers the full push or libcall size.
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/store-merging-debug.mir b/llvm/test/CodeGen/AArch64/GlobalISel/store-merging-debug.mir
index d52ef0f3da74c7..2e8f3c460b2fe7 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/store-merging-debug.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/store-merging-debug.mir
@@ -86,8 +86,8 @@ frameInfo:
   hasMustTailInVarArgFunc: false
   hasTailCall:     false
   localFrameSize:  0
-  savePoint:       ''
-  restorePoint:    ''
+  savePoints:      []
+  restorePoints:   []
 fixedStack:      []
 stack:           []
 callSites:       []
diff --git a/llvm/test/CodeGen/AArch64/aarch64-ldst-no-premature-sp-pop.mir b/llvm/test/CodeGen/AArch64/aarch64-ldst-no-premature-sp-pop.mir
index ba621cf77f9aed..07e80538e793f5 100644
--- a/llvm/test/CodeGen/AArch64/aarch64-ldst-no-premature-sp-pop.mir
+++ b/llvm/test/CodeGen/AArch64/aarch64-ldst-no-premature-sp-pop.mir
@@ -59,8 +59,8 @@ frameInfo:
   hasVAStart:      false
   hasMustTailInVarArgFunc: false
   localFrameSize:  16
-  savePoint:       ''
-  restorePoint:    ''
+  savePoints:      []
+  restorePoints:   []
 fixedStack:      []
 stack:
   - { id: 0, type: default, offset: -16, size: 16,
diff --git a/llvm/test/CodeGen/AArch64/aarch64-mov-debug-locs.mir b/llvm/test/CodeGen/AArch64/aarch64-mov-debug-locs.mir
index 16e2de751381ad..31589a86599ff3 100644
--- a/llvm/test/CodeGen/AArch64/aarch64-mov-debug-locs.mir
+++ b/llvm/test/CodeGen/AArch64/aarch64-mov-debug-locs.mir
@@ -157,8 +157,8 @@ frameInfo:
   hasVAStart:      false
   hasMustTailInVarArgFunc: false
   localFrameSize:  0
-  savePoint:       ''
-  restorePoint:    ''
+  savePoints:      []
+  restorePoints:   []
 fixedStack:      []
 stack:           
   - { id: 0, name: '', type: spill-slot, offset: -8, size: 8, alignment: 8, 
diff --git a/llvm/test/CodeGen/AArch64/aarch64st1.mir b/llvm/test/CodeGen/AArch64/aarch64st1.mir
index 22a024d37bc64f..439db1e97aa794 100644
--- a/llvm/test/CodeGen/AArch64/aarch64st1.mir
+++ b/llvm/test/CodeGen/AArch64/aarch64st1.mir
@@ -58,8 +58,8 @@ frameInfo:
   hasMustTailInVarArgFunc: false
   hasTailCall:     false
   localFrameSize:  0
-  savePoint:       ''
-  restorePoint:    ''
+  savePoints:      []
+  restorePoints:   []
 fixedStack:      []
 stack:
   - { id: 0, name: '', type: default, offset: 0, size: 4, alignment: 4, 
diff --git a/llvm/test/CodeGen/AArch64/cfi-fixup-multi-block-prologue.mir b/llvm/test/CodeGen/AArch64/cfi-fixup-multi-block-prologue.mir
index 31fa3832367bec..6851fdba1239a4 100644
--- a/llvm/test/CodeGen/AArch64/cfi-fixup-multi-block-prologue.mir
+++ b/llvm/test/CodeGen/AArch64/cfi-fixup-multi-block-prologue.mir
@@ -80,8 +80,8 @@ frameInfo:
   hasMustTailInVarArgFunc: false
   hasTailCall:     false
   localFrameSize:  30000
-  savePoint:       ''
-  restorePoint:    ''
+  savePoints:      []
+  restorePoints:   []
 fixedStack:      []
 stack:
   - { id: 0, name: p, type: default, offset: -30016, size: 30000, alignment: 1,
diff --git a/llvm/test/CodeGen/AArch64/cfi-fixup-multi-section.mir b/llvm/test/CodeGen/AArch64/cfi-fixup-multi-section.mir
index a24972d1388320..fe5c90a5e6dc54 100644
--- a/llvm/test/CodeGen/AArch64/cfi-fixup-multi-section.mir
+++ b/llvm/test/CodeGen/AArch64/cfi-fixup-multi-section.mir
@@ -47,8 +47,8 @@ frameInfo:
   hasMustTailInVarArgFunc: false
   hasTailCall:     false
   localFrameSize:  0
-  savePoint:       ''
-  restorePoint:    ''
+  savePoints:      []
+  restorePoints:   []
 fixedStack:      []
 stack:
   - { id: 0, name: '', type: spill-slot, offset: -16, size: 8, alignment: 16,
diff --git a/llvm/test/CodeGen/AArch64/cfi-fixup.mir b/llvm/test/CodeGen/AArch64/cfi-fixup.mir
index f522df6bb3fa06..dd75cec7f6e0be 100644
--- a/llvm/test/CodeGen/AArch64/cfi-fixup.mir
+++ b/llvm/test/CodeGen/AArch64/cfi-fixup.mir
@@ -65,8 +65,8 @@ frameInfo:
   hasMustTailInVarArgFunc: false
   hasTailCall:     false
   localFrameSize:  0
-  savePoint:       ''
-  restorePoint:    ''
+  savePoints:      []
+  restorePoints:   []
 fixedStack:      []
 stack:
   - { id: 0, name: '', type: spill-slot, offset: -16, size: 8, alignment: 16,
@@ -248,8 +248,8 @@ frameInfo:
   hasMustTailInVarArgFunc: false
   hasTailCall:     false
   localFrameSize:  0
-  savePoint:       ''
-  restorePoint:    ''
+  savePoints:      []
+  restorePoints:   []
 fixedStack:      []
 stack:
   - { id: 0, name: '', type: spill-slot, offset: -16, size: 8, alignment: 16,
@@ -403,8 +403,8 @@ frameInfo:
   hasMustTailInVarArgFunc: false
   hasTailCall:     false
   localFrameSize:  0
-  savePoint:       ''
-  restorePoint:    ''
+  savePoints:      []
+  restorePoints:   []
 fixedStack:      []
 stack:
   - { id: 0, name: '', type: spill-slot, offset: -16, size: 8, alignment: 16,
diff --git a/llvm/test/CodeGen/AArch64/dont-shrink-wrap-stack-mayloadorstore.mir b/llvm/test/CodeGen/AArch64/dont-shrink-wrap-stack-mayloadorstore.mir
index 1c4447bffd8729..85f8abcbf7fe60 100644
--- a/llvm/test/CodeGen/AArch64/dont-shrink-wrap-stack-mayloadorstore.mir
+++ b/llvm/test/CodeGen/AArch64/dont-shrink-wrap-stack-mayloadorstore.mir
@@ -6,17 +6,23 @@
  ; RUN: llc -x=mir -simplify-mir -run-pass=shrink-wrap -o - %s | FileCheck %s
  ; CHECK:      name:            compiler_pop_stack
  ; CHECK:      frameInfo:
- ; CHECK:      savePoint:       '%bb.1'
- ; CHECK:      restorePoint:    '%bb.7'
+ ; CHECK:        savePoints:
+ ; CHECK-NEXT:     - point:           '%bb.1'
+ ; CHECK:        restorePoints:
+ ; CHECK-NEXT:     - point:           '%bb.7'
  ; CHECK:      name:            compiler_pop_stack_no_memoperands
  ; CHECK:      frameInfo:
- ; CHECK:      savePoint:       '%bb.1'
- ; CHECK:      restorePoint:    '%bb.7'
+ ; CHECK:        savePoints:
+ ; CHECK-NEXT:     - point:           '%bb.1'
+ ; CHECK:        restorePoints:
+ ; CHECK-NEXT:     - point:           '%bb.7'
  ; CHECK:      name:            f
  ; CHECK:      frameInfo:
- ; CHECK:      savePoint:       '%bb.2'
- ; CHECK-NEXT: restorePoint:    '%bb.4'
- ; CHECK-NEXT: stack:
+ ; CHECK:        savePoints:
+ ; CHECK-NEXT:     - point:           '%bb.2'
+ ; CHECK:        restorePoints:
+ ; CHECK-NEXT:     - point:           '%bb.4'
+ ; CHECK:      stack:
 
   target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"
   target triple = "aarch64"
diff --git a/llvm/test/CodeGen/AArch64/early-ifcvt-regclass-mismatch.mir b/llvm/test/CodeGen/AArch64/early-ifcvt-regclass-mismatch.mir
index a7f67f8b682c3c..6324db0cb2c0ff 100644
--- a/llvm/test/CodeGen/AArch64/early-ifcvt-regclass-mismatch.mir
+++ b/llvm/test/CodeGen/AArch64/early-ifcvt-regclass-mismatch.mir
@@ -105,8 +105,8 @@ frameInfo:
   hasVAStart:      false
   hasMustTailInVarArgFunc: false
   localFrameSize:  0
-  savePoint:       ''
-  restorePoint:    ''
+  savePoints:      []
+  restorePoints:   []
 fixedStack:      []
 stack:           []
 callSites:       []
diff --git a/llvm/test/CodeGen/AArch64/emit_fneg_with_non_register_operand.mir b/llvm/test/CodeGen/AArch64/emit_fneg_with_non_register_operand.mir
index f9878adfe5e448..3c98a1a128413e 100644
--- a/llvm/test/CodeGen/AArch64/emit_fneg_with_non_register_operand.mir
+++ b/llvm/test/CodeGen/AArch64/emit_fneg_with_non_register_operand.mir
@@ -75,8 +75,8 @@ frameInfo:
   hasMustTailInVarArgFunc: false
   hasTailCall:     true
   localFrameSize:  0
-  savePoint:       ''
-  restorePoint:    ''
+  savePoints:      []
+  restorePoints:   []
 fixedStack:      []
 stack:           []
 entry_values:    []
diff --git a/llvm/test/CodeGen/AArch64/irg-nomem.mir b/llvm/test/CodeGen/AArch64/irg-nomem.mir
index 3b000fafbed46f..78438151405e66 100644
--- a/llvm/test/CodeGen/AArch64/irg-nomem.mir
+++ b/llvm/test/CodeGen/AArch64/irg-nomem.mir
@@ -47,8 +47,8 @@ frameInfo:
   hasVAStart:      false
   hasMustTailInVarArgFunc: false
   localFrameSize:  0
-  savePoint:       ''
-  restorePoint:    ''
+  savePoints:      []
+  restorePoints:   []
 fixedStack:      []
 stack:           []
 callSites:       []
diff --git a/llvm/test/CodeGen/AArch64/jump-table-duplicate.mir b/llvm/test/CodeGen/AArch64/jump-table-duplicate.mir
index a2532a854923f5..81cf5953895cab 100644
--- a/llvm/test/CodeGen/AArch64/jump-table-duplicate.mir
+++ b/llvm/test/CodeGen/AArch64/jump-table-duplicate.mir
@@ -92,8 +92,8 @@ frameInfo:
   hasVAStart:      false
   hasMustTailInVarArgFunc: false
   localFrameSize:  0
-  savePoint:       ''
-  restorePoint:    ''
+  savePoints:      []
+  restorePoints:   []
 fixedStack:      []
 stack:
   - { id: 0, name: '', type: spill-slot, offset: -8, size: 8, alignment: 8, 
diff --git a/llvm/test/CodeGen/AArch64/ldst-nopreidx-sp-redzone.mir b/llvm/test/CodeGen/AArch64/ldst-nopreidx-sp-redzone.mir
index f1f9e5fbc9b087..b431de2d9b35b3 100644
--- a/llvm/test/CodeGen/AArch64/ldst-nopreidx-sp-redzone.mir
+++ b/llvm/test/CodeGen/AArch64/ldst-nopreidx-sp-redzone.mir
@@ -103,8 +103,8 @@ frameInfo:
   hasVAStart:      false
   hasMustTailInVarArgFunc: false
   localFrameSize:  480
-  savePoint:       ''
-  restorePoint:    ''
+  savePoints:      []
+  restorePoints:   []
 fixedStack:      []
 stack:
   - { id: 0, name: StackGuardSlot, type: default, offset: -40, size: 8, 
@@ -216,8 +216,8 @@ frameInfo:
   hasVAStart:      false
   hasMustTailInVarArgFunc: false
   localFrameSize:  480
-  savePoint:       ''
-  restorePoint:    ''
+  savePoints:      []
+  restorePoints:   []
 fixedStack:      []
 stack:
   - { id: 0, name: StackGuardSlot, type: default, offset: -40, size: 8, 
@@ -327,8 +327,8 @@ frameInfo:
   hasVAStart:      false
   hasMustTailInVarArgFunc: false
   localFrameSize:  480
-  savePoint:       ''
-  restorePoint:    ''
+  savePoints:      []
+  restorePoints:   []
 fixedStack:      []
 stack:
   - { id: 0, name: StackGuardSlot, type: default, offset: -40, size: 8, 
diff --git a/llvm/test/CodeGen/AArch64/live-debugvalues-sve.mir b/llvm/test/CodeGen/AArch64/live-debugvalues-sve.mir
index 612453ab53f438..4be16228814a3b 100644
--- a/llvm/test/CodeGen/AArch64/live-debugvalues-sve.mir
+++ b/llvm/test/CodeGen/AArch64/live-debugvalues-sve.mir
@@ -120,8 +120,10 @@ frameInfo:
   adjustsStack:    true
   hasC...
[truncated]

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llvmbot commented Dec 10, 2024

@llvm/pr-subscribers-backend-powerpc

Author: Elizaveta Noskova (enoskova-sc)

Changes

Currently mir supports only one save and one restore point specification:

  savePoint:       '%bb.1'
  restorePoint:    '%bb.2'

This patch provide possibility to have multiple save and multiple restore points in mir:

  savePoints:
    - point:           '%bb.1'
  restorePoints:
    - point:           '%bb.2'

Shrink-Wrap points split Part 3.

Part 1: #117862
Part 2: #119355


Patch is 276.31 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/119357.diff

340 Files Affected:

  • (modified) llvm/include/llvm/CodeGen/MIRYamlMapping.h (+32-7)
  • (modified) llvm/include/llvm/CodeGen/MachineDominators.h (+5)
  • (modified) llvm/lib/CodeGen/MIRParser/MIRParser.cpp (+29-14)
  • (modified) llvm/lib/CodeGen/MIRPrinter.cpp (+18-8)
  • (modified) llvm/lib/CodeGen/MachineDominators.cpp (+16)
  • (modified) llvm/lib/Target/RISCV/RISCVFrameLowering.cpp (+4)
  • (modified) llvm/test/CodeGen/AArch64/GlobalISel/store-merging-debug.mir (+2-2)
  • (modified) llvm/test/CodeGen/AArch64/aarch64-ldst-no-premature-sp-pop.mir (+2-2)
  • (modified) llvm/test/CodeGen/AArch64/aarch64-mov-debug-locs.mir (+2-2)
  • (modified) llvm/test/CodeGen/AArch64/aarch64st1.mir (+2-2)
  • (modified) llvm/test/CodeGen/AArch64/cfi-fixup-multi-block-prologue.mir (+2-2)
  • (modified) llvm/test/CodeGen/AArch64/cfi-fixup-multi-section.mir (+2-2)
  • (modified) llvm/test/CodeGen/AArch64/cfi-fixup.mir (+6-6)
  • (modified) llvm/test/CodeGen/AArch64/dont-shrink-wrap-stack-mayloadorstore.mir (+13-7)
  • (modified) llvm/test/CodeGen/AArch64/early-ifcvt-regclass-mismatch.mir (+2-2)
  • (modified) llvm/test/CodeGen/AArch64/emit_fneg_with_non_register_operand.mir (+2-2)
  • (modified) llvm/test/CodeGen/AArch64/irg-nomem.mir (+2-2)
  • (modified) llvm/test/CodeGen/AArch64/jump-table-duplicate.mir (+2-2)
  • (modified) llvm/test/CodeGen/AArch64/ldst-nopreidx-sp-redzone.mir (+6-6)
  • (modified) llvm/test/CodeGen/AArch64/live-debugvalues-sve.mir (+4-2)
  • (modified) llvm/test/CodeGen/AArch64/loop-sink-limit.mir (+2-2)
  • (modified) llvm/test/CodeGen/AArch64/loop-sink.mir (+16-16)
  • (modified) llvm/test/CodeGen/AArch64/machine-latecleanup-inlineasm.mir (+2-2)
  • (modified) llvm/test/CodeGen/AArch64/nested-iv-regalloc.mir (+2-2)
  • (modified) llvm/test/CodeGen/AArch64/regalloc-last-chance-recolor-with-split.mir (+2-2)
  • (modified) llvm/test/CodeGen/AArch64/shrinkwrap-split-restore-point.mir (+2-2)
  • (modified) llvm/test/CodeGen/AArch64/sink-and-fold-drop-dbg.mir (+2-2)
  • (modified) llvm/test/CodeGen/AArch64/sink-and-fold-illegal-shift.mir (+2-2)
  • (modified) llvm/test/CodeGen/AArch64/sink-and-fold-preserve-debugloc.mir (+4-4)
  • (modified) llvm/test/CodeGen/AArch64/split-deadloop.mir (+2-2)
  • (modified) llvm/test/CodeGen/AArch64/stack-probing-last-in-block.mir (+2-2)
  • (modified) llvm/test/CodeGen/AArch64/tail-dup-redundant-phi.mir (+2-2)
  • (modified) llvm/test/CodeGen/AArch64/taildup-addrtaken.mir (+2-2)
  • (modified) llvm/test/CodeGen/AArch64/wineh-frame-predecrement.mir (+2-2)
  • (modified) llvm/test/CodeGen/AArch64/wineh-frame-scavenge.mir (+2-2)
  • (modified) llvm/test/CodeGen/AArch64/wineh-frame1.mir (+2-2)
  • (modified) llvm/test/CodeGen/AArch64/wineh-frame2.mir (+2-2)
  • (modified) llvm/test/CodeGen/AArch64/wineh-frame3.mir (+2-2)
  • (modified) llvm/test/CodeGen/AArch64/wineh-frame4.mir (+2-2)
  • (modified) llvm/test/CodeGen/AArch64/wineh-frame5.mir (+2-2)
  • (modified) llvm/test/CodeGen/AArch64/wineh-frame6.mir (+2-2)
  • (modified) llvm/test/CodeGen/AArch64/wineh-frame7.mir (+2-2)
  • (modified) llvm/test/CodeGen/AArch64/wineh-frame8.mir (+2-2)
  • (modified) llvm/test/CodeGen/AArch64/wineh-save-lrpair1.mir (+2-2)
  • (modified) llvm/test/CodeGen/AArch64/wineh-save-lrpair2.mir (+2-2)
  • (modified) llvm/test/CodeGen/AArch64/wineh-save-lrpair3.mir (+2-2)
  • (modified) llvm/test/CodeGen/AArch64/wineh2.mir (+2-2)
  • (modified) llvm/test/CodeGen/AArch64/wineh3.mir (+2-2)
  • (modified) llvm/test/CodeGen/AArch64/wineh4.mir (+2-2)
  • (modified) llvm/test/CodeGen/AArch64/wineh5.mir (+2-2)
  • (modified) llvm/test/CodeGen/AArch64/wineh6.mir (+2-2)
  • (modified) llvm/test/CodeGen/AArch64/wineh7.mir (+2-2)
  • (modified) llvm/test/CodeGen/AArch64/wineh8.mir (+2-2)
  • (modified) llvm/test/CodeGen/AArch64/wineh9.mir (+2-2)
  • (modified) llvm/test/CodeGen/AArch64/wineh_shrinkwrap.mir (+2-2)
  • (modified) llvm/test/CodeGen/AMDGPU/memory-legalizer-multiple-mem-operands-nontemporal-1.mir (+2-2)
  • (modified) llvm/test/CodeGen/AMDGPU/memory-legalizer-multiple-mem-operands-nontemporal-2.mir (+2-2)
  • (modified) llvm/test/CodeGen/ARM/cmse-vlldm-no-reorder.mir (+2-2)
  • (modified) llvm/test/CodeGen/ARM/codesize-ifcvt.mir (+6-6)
  • (modified) llvm/test/CodeGen/ARM/constant-island-movwt.mir (+2-2)
  • (modified) llvm/test/CodeGen/ARM/constant-islands-cfg.mir (+2-2)
  • (modified) llvm/test/CodeGen/ARM/constant-islands-split-IT.mir (+2-2)
  • (modified) llvm/test/CodeGen/ARM/execute-only-save-cpsr.mir (+8-8)
  • (modified) llvm/test/CodeGen/ARM/fp16-litpool2-arm.mir (+2-2)
  • (modified) llvm/test/CodeGen/ARM/fp16-litpool3-arm.mir (+2-2)
  • (modified) llvm/test/CodeGen/ARM/inlineasmbr-if-cvt.mir (+2-2)
  • (modified) llvm/test/CodeGen/ARM/invalidated-save-point.ll (+2-2)
  • (modified) llvm/test/CodeGen/ARM/jump-table-dbg-value.mir (+2-2)
  • (modified) llvm/test/CodeGen/ARM/stack_frame_offset.mir (+6-6)
  • (modified) llvm/test/CodeGen/Hexagon/cext-opt-block-addr.mir (+4-4)
  • (modified) llvm/test/CodeGen/Hexagon/early-if-predicator.mir (+2-2)
  • (modified) llvm/test/CodeGen/Hexagon/machine-sink-float-usr.mir (+4-4)
  • (modified) llvm/test/CodeGen/Hexagon/pipeliner/swp-phi-start.mir (+2-2)
  • (modified) llvm/test/CodeGen/MIR/ARM/thumb2-sub-sp-t3.mir (+2-2)
  • (modified) llvm/test/CodeGen/MIR/Generic/frame-info.mir (+2-2)
  • (modified) llvm/test/CodeGen/MIR/Hexagon/addrmode-opt-nonreaching.mir (+2-2)
  • (modified) llvm/test/CodeGen/MIR/RISCV/machine-function-info.mir (+2-2)
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  • (modified) llvm/test/CodeGen/Thumb2/pipeliner-preserve-ties.mir (+2-2)
  • (modified) llvm/test/CodeGen/VE/Scalar/fold-imm-addsl.mir (+8-8)
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diff --git a/llvm/include/llvm/CodeGen/MIRYamlMapping.h b/llvm/include/llvm/CodeGen/MIRYamlMapping.h
index 09a6ca936fe1f4..be8a8e593ef922 100644
--- a/llvm/include/llvm/CodeGen/MIRYamlMapping.h
+++ b/llvm/include/llvm/CodeGen/MIRYamlMapping.h
@@ -610,6 +610,20 @@ LLVM_YAML_IS_SEQUENCE_VECTOR(llvm::yaml::MachineJumpTable::Entry)
 namespace llvm {
 namespace yaml {
 
+struct SRPEntry {
+  StringValue Point;
+
+  bool operator==(const SRPEntry &Other) const { return Point == Other.Point; }
+};
+
+using SaveRestorePoints = std::vector<SRPEntry>;
+
+template <> struct MappingTraits<SRPEntry> {
+  static void mapping(IO &YamlIO, SRPEntry &Entry) {
+    YamlIO.mapRequired("point", Entry.Point);
+  }
+};
+
 template <> struct MappingTraits<MachineJumpTable> {
   static void mapping(IO &YamlIO, MachineJumpTable &JT) {
     YamlIO.mapRequired("kind", JT.Kind);
@@ -618,6 +632,14 @@ template <> struct MappingTraits<MachineJumpTable> {
   }
 };
 
+} // namespace yaml
+} // namespace llvm
+
+LLVM_YAML_IS_SEQUENCE_VECTOR(llvm::yaml::SRPEntry)
+
+namespace llvm {
+namespace yaml {
+
 /// Serializable representation of MachineFrameInfo.
 ///
 /// Doesn't serialize attributes like 'StackAlignment', 'IsStackRealignable' and
@@ -645,8 +667,8 @@ struct MachineFrameInfo {
   bool HasTailCall = false;
   bool IsCalleeSavedInfoValid = false;
   unsigned LocalFrameSize = 0;
-  StringValue SavePoint;
-  StringValue RestorePoint;
+  SaveRestorePoints SavePoints;
+  SaveRestorePoints RestorePoints;
 
   bool operator==(const MachineFrameInfo &Other) const {
     return IsFrameAddressTaken == Other.IsFrameAddressTaken &&
@@ -667,7 +689,8 @@ struct MachineFrameInfo {
            HasMustTailInVarArgFunc == Other.HasMustTailInVarArgFunc &&
            HasTailCall == Other.HasTailCall &&
            LocalFrameSize == Other.LocalFrameSize &&
-           SavePoint == Other.SavePoint && RestorePoint == Other.RestorePoint &&
+           SavePoints == Other.SavePoints &&
+           RestorePoints == Other.RestorePoints &&
            IsCalleeSavedInfoValid == Other.IsCalleeSavedInfoValid;
   }
 };
@@ -699,10 +722,12 @@ template <> struct MappingTraits<MachineFrameInfo> {
     YamlIO.mapOptional("isCalleeSavedInfoValid", MFI.IsCalleeSavedInfoValid,
                        false);
     YamlIO.mapOptional("localFrameSize", MFI.LocalFrameSize, (unsigned)0);
-    YamlIO.mapOptional("savePoint", MFI.SavePoint,
-                       StringValue()); // Don't print it out when it's empty.
-    YamlIO.mapOptional("restorePoint", MFI.RestorePoint,
-                       StringValue()); // Don't print it out when it's empty.
+    YamlIO.mapOptional(
+        "savePoints", MFI.SavePoints,
+        SaveRestorePoints()); // Don't print it out when it's empty.
+    YamlIO.mapOptional(
+        "restorePoints", MFI.RestorePoints,
+        SaveRestorePoints()); // Don't print it out when it's empty.
   }
 };
 
diff --git a/llvm/include/llvm/CodeGen/MachineDominators.h b/llvm/include/llvm/CodeGen/MachineDominators.h
index 74cf94398736dd..88800d91ef51a9 100644
--- a/llvm/include/llvm/CodeGen/MachineDominators.h
+++ b/llvm/include/llvm/CodeGen/MachineDominators.h
@@ -185,6 +185,11 @@ class MachineDominatorTree : public DomTreeBase<MachineBasicBlock> {
     return Base::findNearestCommonDominator(A, B);
   }
 
+  /// Returns the nearest common dominator of the given blocks.
+  /// If that tree node is a virtual root, a nullptr will be returned.
+  MachineBasicBlock *
+  findNearestCommonDominator(ArrayRef<MachineBasicBlock *> Blocks) const;
+
   MachineDomTreeNode *operator[](MachineBasicBlock *BB) const {
     applySplitCriticalEdges();
     return Base::getNode(BB);
diff --git a/llvm/lib/CodeGen/MIRParser/MIRParser.cpp b/llvm/lib/CodeGen/MIRParser/MIRParser.cpp
index e2543f883f91ce..f7c1e162d2a96e 100644
--- a/llvm/lib/CodeGen/MIRParser/MIRParser.cpp
+++ b/llvm/lib/CodeGen/MIRParser/MIRParser.cpp
@@ -124,6 +124,10 @@ class MIRParserImpl {
   bool initializeFrameInfo(PerFunctionMIParsingState &PFS,
                            const yaml::MachineFunction &YamlMF);
 
+  bool initializeSaveRestorePoints(PerFunctionMIParsingState &PFS,
+                                   const yaml::SaveRestorePoints &YamlSRP,
+                                   bool IsSavePoints);
+
   bool initializeCallSiteInfo(PerFunctionMIParsingState &PFS,
                               const yaml::MachineFunction &YamlMF);
 
@@ -832,18 +836,9 @@ bool MIRParserImpl::initializeFrameInfo(PerFunctionMIParsingState &PFS,
   MFI.setHasTailCall(YamlMFI.HasTailCall);
   MFI.setCalleeSavedInfoValid(YamlMFI.IsCalleeSavedInfoValid);
   MFI.setLocalFrameSize(YamlMFI.LocalFrameSize);
-  if (!YamlMFI.SavePoint.Value.empty()) {
-    MachineBasicBlock *MBB = nullptr;
-    if (parseMBBReference(PFS, MBB, YamlMFI.SavePoint))
-      return true;
-    MFI.setSavePoint(MBB);
-  }
-  if (!YamlMFI.RestorePoint.Value.empty()) {
-    MachineBasicBlock *MBB = nullptr;
-    if (parseMBBReference(PFS, MBB, YamlMFI.RestorePoint))
-      return true;
-    MFI.setRestorePoint(MBB);
-  }
+  initializeSaveRestorePoints(PFS, YamlMFI.SavePoints, true /*IsSavePoints*/);
+  initializeSaveRestorePoints(PFS, YamlMFI.RestorePoints,
+                              false /*IsSavePoints*/);
 
   std::vector<CalleeSavedInfo> CSIInfo;
   // Initialize the fixed frame objects.
@@ -1058,8 +1053,28 @@ bool MIRParserImpl::initializeConstantPool(PerFunctionMIParsingState &PFS,
   return false;
 }
 
-bool MIRParserImpl::initializeJumpTableInfo(PerFunctionMIParsingState &PFS,
-    const yaml::MachineJumpTable &YamlJTI) {
+bool MIRParserImpl::initializeSaveRestorePoints(
+    PerFunctionMIParsingState &PFS, const yaml::SaveRestorePoints &YamlSRP,
+    bool IsSavePoints) {
+  MachineFunction &MF = PFS.MF;
+  MachineFrameInfo &MFI = MF.getFrameInfo();
+
+  if (!YamlSRP.empty()) {
+    const auto &Entry = YamlSRP.front();
+    const auto &MBBSource = Entry.Point;
+    MachineBasicBlock *MBB = nullptr;
+    if (parseMBBReference(PFS, MBB, MBBSource.Value))
+      return true;
+    if (IsSavePoints)
+      MFI.setSavePoint(MBB);
+    else
+      MFI.setRestorePoint(MBB);
+  }
+  return false;
+}
+
+bool MIRParserImpl::initializeJumpTableInfo(
+    PerFunctionMIParsingState &PFS, const yaml::MachineJumpTable &YamlJTI) {
   MachineJumpTableInfo *JTI = PFS.MF.getOrCreateJumpTableInfo(YamlJTI.Kind);
   for (const auto &Entry : YamlJTI.Entries) {
     std::vector<MachineBasicBlock *> Blocks;
diff --git a/llvm/lib/CodeGen/MIRPrinter.cpp b/llvm/lib/CodeGen/MIRPrinter.cpp
index c8f6341c1224d2..2d0728a6452808 100644
--- a/llvm/lib/CodeGen/MIRPrinter.cpp
+++ b/llvm/lib/CodeGen/MIRPrinter.cpp
@@ -118,6 +118,8 @@ class MIRPrinter {
                const TargetRegisterInfo *TRI);
   void convert(ModuleSlotTracker &MST, yaml::MachineFrameInfo &YamlMFI,
                const MachineFrameInfo &MFI);
+  void convert(ModuleSlotTracker &MST, yaml::SaveRestorePoints &YamlSRP,
+               MachineBasicBlock *SaveRestorePoint);
   void convert(yaml::MachineFunction &MF,
                const MachineConstantPool &ConstantPool);
   void convert(ModuleSlotTracker &MST, yaml::MachineJumpTable &YamlJTI,
@@ -392,14 +394,10 @@ void MIRPrinter::convert(ModuleSlotTracker &MST,
   YamlMFI.HasTailCall = MFI.hasTailCall();
   YamlMFI.IsCalleeSavedInfoValid = MFI.isCalleeSavedInfoValid();
   YamlMFI.LocalFrameSize = MFI.getLocalFrameSize();
-  if (MFI.getSavePoint()) {
-    raw_string_ostream StrOS(YamlMFI.SavePoint.Value);
-    StrOS << printMBBReference(*MFI.getSavePoint());
-  }
-  if (MFI.getRestorePoint()) {
-    raw_string_ostream StrOS(YamlMFI.RestorePoint.Value);
-    StrOS << printMBBReference(*MFI.getRestorePoint());
-  }
+  if (MFI.getSavePoint())
+    convert(MST, YamlMFI.SavePoints, MFI.getSavePoint());
+  if (MFI.getRestorePoint())
+    convert(MST, YamlMFI.RestorePoints, MFI.getRestorePoint());
 }
 
 void MIRPrinter::convertEntryValueObjects(yaml::MachineFunction &YMF,
@@ -618,6 +616,18 @@ void MIRPrinter::convert(yaml::MachineFunction &MF,
   }
 }
 
+void MIRPrinter::convert(ModuleSlotTracker &MST,
+                         yaml::SaveRestorePoints &YamlSRP,
+                         MachineBasicBlock *SRP) {
+  std::string Str;
+  yaml::SRPEntry Entry;
+  raw_string_ostream StrOS(Str);
+  StrOS << printMBBReference(*SRP);
+  Entry.Point = StrOS.str();
+  Str.clear();
+  YamlSRP.push_back(Entry);
+}
+
 void MIRPrinter::convert(ModuleSlotTracker &MST,
                          yaml::MachineJumpTable &YamlJTI,
                          const MachineJumpTableInfo &JTI) {
diff --git a/llvm/lib/CodeGen/MachineDominators.cpp b/llvm/lib/CodeGen/MachineDominators.cpp
index a2cc8fdfa7c9f9..384f90c6da66c0 100644
--- a/llvm/lib/CodeGen/MachineDominators.cpp
+++ b/llvm/lib/CodeGen/MachineDominators.cpp
@@ -189,3 +189,19 @@ void MachineDominatorTree::applySplitCriticalEdges() const {
   NewBBs.clear();
   CriticalEdgesToSplit.clear();
 }
+
+MachineBasicBlock *MachineDominatorTree::findNearestCommonDominator(
+    ArrayRef<MachineBasicBlock *> Blocks) const {
+  assert(!Blocks.empty());
+
+  MachineBasicBlock *NCD = Blocks.front();
+  for (MachineBasicBlock *BB : Blocks.drop_front()) {
+    NCD = Base::findNearestCommonDominator(NCD, BB);
+
+    // Stop when the root is reached.
+    if (Base::isVirtualRoot(Base::getNode(NCD)))
+      return nullptr;
+  }
+
+  return NCD;
+}
diff --git a/llvm/lib/Target/RISCV/RISCVFrameLowering.cpp b/llvm/lib/Target/RISCV/RISCVFrameLowering.cpp
index deb0b627225c64..0de1f1d821a6e2 100644
--- a/llvm/lib/Target/RISCV/RISCVFrameLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVFrameLowering.cpp
@@ -1607,6 +1607,8 @@ bool RISCVFrameLowering::assignCalleeSavedSpillSlots(
         int FrameIdx = MFI.CreateFixedSpillStackObject(Size, Offset);
         assert(FrameIdx < 0);
         CS.setFrameIdx(FrameIdx);
+        if (RISCVRegisterInfo::isRVVRegClass(RC))
+          MFI.setStackID(FrameIdx, TargetStackID::ScalableVector);
         continue;
       }
     }
@@ -1623,6 +1625,8 @@ bool RISCVFrameLowering::assignCalleeSavedSpillSlots(
     if ((unsigned)FrameIdx > MaxCSFrameIndex)
       MaxCSFrameIndex = FrameIdx;
     CS.setFrameIdx(FrameIdx);
+    if (RISCVRegisterInfo::isRVVRegClass(RC))
+      MFI.setStackID(FrameIdx, TargetStackID::ScalableVector);
   }
 
   // Allocate a fixed object that covers the full push or libcall size.
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/store-merging-debug.mir b/llvm/test/CodeGen/AArch64/GlobalISel/store-merging-debug.mir
index d52ef0f3da74c7..2e8f3c460b2fe7 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/store-merging-debug.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/store-merging-debug.mir
@@ -86,8 +86,8 @@ frameInfo:
   hasMustTailInVarArgFunc: false
   hasTailCall:     false
   localFrameSize:  0
-  savePoint:       ''
-  restorePoint:    ''
+  savePoints:      []
+  restorePoints:   []
 fixedStack:      []
 stack:           []
 callSites:       []
diff --git a/llvm/test/CodeGen/AArch64/aarch64-ldst-no-premature-sp-pop.mir b/llvm/test/CodeGen/AArch64/aarch64-ldst-no-premature-sp-pop.mir
index ba621cf77f9aed..07e80538e793f5 100644
--- a/llvm/test/CodeGen/AArch64/aarch64-ldst-no-premature-sp-pop.mir
+++ b/llvm/test/CodeGen/AArch64/aarch64-ldst-no-premature-sp-pop.mir
@@ -59,8 +59,8 @@ frameInfo:
   hasVAStart:      false
   hasMustTailInVarArgFunc: false
   localFrameSize:  16
-  savePoint:       ''
-  restorePoint:    ''
+  savePoints:      []
+  restorePoints:   []
 fixedStack:      []
 stack:
   - { id: 0, type: default, offset: -16, size: 16,
diff --git a/llvm/test/CodeGen/AArch64/aarch64-mov-debug-locs.mir b/llvm/test/CodeGen/AArch64/aarch64-mov-debug-locs.mir
index 16e2de751381ad..31589a86599ff3 100644
--- a/llvm/test/CodeGen/AArch64/aarch64-mov-debug-locs.mir
+++ b/llvm/test/CodeGen/AArch64/aarch64-mov-debug-locs.mir
@@ -157,8 +157,8 @@ frameInfo:
   hasVAStart:      false
   hasMustTailInVarArgFunc: false
   localFrameSize:  0
-  savePoint:       ''
-  restorePoint:    ''
+  savePoints:      []
+  restorePoints:   []
 fixedStack:      []
 stack:           
   - { id: 0, name: '', type: spill-slot, offset: -8, size: 8, alignment: 8, 
diff --git a/llvm/test/CodeGen/AArch64/aarch64st1.mir b/llvm/test/CodeGen/AArch64/aarch64st1.mir
index 22a024d37bc64f..439db1e97aa794 100644
--- a/llvm/test/CodeGen/AArch64/aarch64st1.mir
+++ b/llvm/test/CodeGen/AArch64/aarch64st1.mir
@@ -58,8 +58,8 @@ frameInfo:
   hasMustTailInVarArgFunc: false
   hasTailCall:     false
   localFrameSize:  0
-  savePoint:       ''
-  restorePoint:    ''
+  savePoints:      []
+  restorePoints:   []
 fixedStack:      []
 stack:
   - { id: 0, name: '', type: default, offset: 0, size: 4, alignment: 4, 
diff --git a/llvm/test/CodeGen/AArch64/cfi-fixup-multi-block-prologue.mir b/llvm/test/CodeGen/AArch64/cfi-fixup-multi-block-prologue.mir
index 31fa3832367bec..6851fdba1239a4 100644
--- a/llvm/test/CodeGen/AArch64/cfi-fixup-multi-block-prologue.mir
+++ b/llvm/test/CodeGen/AArch64/cfi-fixup-multi-block-prologue.mir
@@ -80,8 +80,8 @@ frameInfo:
   hasMustTailInVarArgFunc: false
   hasTailCall:     false
   localFrameSize:  30000
-  savePoint:       ''
-  restorePoint:    ''
+  savePoints:      []
+  restorePoints:   []
 fixedStack:      []
 stack:
   - { id: 0, name: p, type: default, offset: -30016, size: 30000, alignment: 1,
diff --git a/llvm/test/CodeGen/AArch64/cfi-fixup-multi-section.mir b/llvm/test/CodeGen/AArch64/cfi-fixup-multi-section.mir
index a24972d1388320..fe5c90a5e6dc54 100644
--- a/llvm/test/CodeGen/AArch64/cfi-fixup-multi-section.mir
+++ b/llvm/test/CodeGen/AArch64/cfi-fixup-multi-section.mir
@@ -47,8 +47,8 @@ frameInfo:
   hasMustTailInVarArgFunc: false
   hasTailCall:     false
   localFrameSize:  0
-  savePoint:       ''
-  restorePoint:    ''
+  savePoints:      []
+  restorePoints:   []
 fixedStack:      []
 stack:
   - { id: 0, name: '', type: spill-slot, offset: -16, size: 8, alignment: 16,
diff --git a/llvm/test/CodeGen/AArch64/cfi-fixup.mir b/llvm/test/CodeGen/AArch64/cfi-fixup.mir
index f522df6bb3fa06..dd75cec7f6e0be 100644
--- a/llvm/test/CodeGen/AArch64/cfi-fixup.mir
+++ b/llvm/test/CodeGen/AArch64/cfi-fixup.mir
@@ -65,8 +65,8 @@ frameInfo:
   hasMustTailInVarArgFunc: false
   hasTailCall:     false
   localFrameSize:  0
-  savePoint:       ''
-  restorePoint:    ''
+  savePoints:      []
+  restorePoints:   []
 fixedStack:      []
 stack:
   - { id: 0, name: '', type: spill-slot, offset: -16, size: 8, alignment: 16,
@@ -248,8 +248,8 @@ frameInfo:
   hasMustTailInVarArgFunc: false
   hasTailCall:     false
   localFrameSize:  0
-  savePoint:       ''
-  restorePoint:    ''
+  savePoints:      []
+  restorePoints:   []
 fixedStack:      []
 stack:
   - { id: 0, name: '', type: spill-slot, offset: -16, size: 8, alignment: 16,
@@ -403,8 +403,8 @@ frameInfo:
   hasMustTailInVarArgFunc: false
   hasTailCall:     false
   localFrameSize:  0
-  savePoint:       ''
-  restorePoint:    ''
+  savePoints:      []
+  restorePoints:   []
 fixedStack:      []
 stack:
   - { id: 0, name: '', type: spill-slot, offset: -16, size: 8, alignment: 16,
diff --git a/llvm/test/CodeGen/AArch64/dont-shrink-wrap-stack-mayloadorstore.mir b/llvm/test/CodeGen/AArch64/dont-shrink-wrap-stack-mayloadorstore.mir
index 1c4447bffd8729..85f8abcbf7fe60 100644
--- a/llvm/test/CodeGen/AArch64/dont-shrink-wrap-stack-mayloadorstore.mir
+++ b/llvm/test/CodeGen/AArch64/dont-shrink-wrap-stack-mayloadorstore.mir
@@ -6,17 +6,23 @@
  ; RUN: llc -x=mir -simplify-mir -run-pass=shrink-wrap -o - %s | FileCheck %s
  ; CHECK:      name:            compiler_pop_stack
  ; CHECK:      frameInfo:
- ; CHECK:      savePoint:       '%bb.1'
- ; CHECK:      restorePoint:    '%bb.7'
+ ; CHECK:        savePoints:
+ ; CHECK-NEXT:     - point:           '%bb.1'
+ ; CHECK:        restorePoints:
+ ; CHECK-NEXT:     - point:           '%bb.7'
  ; CHECK:      name:            compiler_pop_stack_no_memoperands
  ; CHECK:      frameInfo:
- ; CHECK:      savePoint:       '%bb.1'
- ; CHECK:      restorePoint:    '%bb.7'
+ ; CHECK:        savePoints:
+ ; CHECK-NEXT:     - point:           '%bb.1'
+ ; CHECK:        restorePoints:
+ ; CHECK-NEXT:     - point:           '%bb.7'
  ; CHECK:      name:            f
  ; CHECK:      frameInfo:
- ; CHECK:      savePoint:       '%bb.2'
- ; CHECK-NEXT: restorePoint:    '%bb.4'
- ; CHECK-NEXT: stack:
+ ; CHECK:        savePoints:
+ ; CHECK-NEXT:     - point:           '%bb.2'
+ ; CHECK:        restorePoints:
+ ; CHECK-NEXT:     - point:           '%bb.4'
+ ; CHECK:      stack:
 
   target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"
   target triple = "aarch64"
diff --git a/llvm/test/CodeGen/AArch64/early-ifcvt-regclass-mismatch.mir b/llvm/test/CodeGen/AArch64/early-ifcvt-regclass-mismatch.mir
index a7f67f8b682c3c..6324db0cb2c0ff 100644
--- a/llvm/test/CodeGen/AArch64/early-ifcvt-regclass-mismatch.mir
+++ b/llvm/test/CodeGen/AArch64/early-ifcvt-regclass-mismatch.mir
@@ -105,8 +105,8 @@ frameInfo:
   hasVAStart:      false
   hasMustTailInVarArgFunc: false
   localFrameSize:  0
-  savePoint:       ''
-  restorePoint:    ''
+  savePoints:      []
+  restorePoints:   []
 fixedStack:      []
 stack:           []
 callSites:       []
diff --git a/llvm/test/CodeGen/AArch64/emit_fneg_with_non_register_operand.mir b/llvm/test/CodeGen/AArch64/emit_fneg_with_non_register_operand.mir
index f9878adfe5e448..3c98a1a128413e 100644
--- a/llvm/test/CodeGen/AArch64/emit_fneg_with_non_register_operand.mir
+++ b/llvm/test/CodeGen/AArch64/emit_fneg_with_non_register_operand.mir
@@ -75,8 +75,8 @@ frameInfo:
   hasMustTailInVarArgFunc: false
   hasTailCall:     true
   localFrameSize:  0
-  savePoint:       ''
-  restorePoint:    ''
+  savePoints:      []
+  restorePoints:   []
 fixedStack:      []
 stack:           []
 entry_values:    []
diff --git a/llvm/test/CodeGen/AArch64/irg-nomem.mir b/llvm/test/CodeGen/AArch64/irg-nomem.mir
index 3b000fafbed46f..78438151405e66 100644
--- a/llvm/test/CodeGen/AArch64/irg-nomem.mir
+++ b/llvm/test/CodeGen/AArch64/irg-nomem.mir
@@ -47,8 +47,8 @@ frameInfo:
   hasVAStart:      false
   hasMustTailInVarArgFunc: false
   localFrameSize:  0
-  savePoint:       ''
-  restorePoint:    ''
+  savePoints:      []
+  restorePoints:   []
 fixedStack:      []
 stack:           []
 callSites:       []
diff --git a/llvm/test/CodeGen/AArch64/jump-table-duplicate.mir b/llvm/test/CodeGen/AArch64/jump-table-duplicate.mir
index a2532a854923f5..81cf5953895cab 100644
--- a/llvm/test/CodeGen/AArch64/jump-table-duplicate.mir
+++ b/llvm/test/CodeGen/AArch64/jump-table-duplicate.mir
@@ -92,8 +92,8 @@ frameInfo:
   hasVAStart:      false
   hasMustTailInVarArgFunc: false
   localFrameSize:  0
-  savePoint:       ''
-  restorePoint:    ''
+  savePoints:      []
+  restorePoints:   []
 fixedStack:      []
 stack:
   - { id: 0, name: '', type: spill-slot, offset: -8, size: 8, alignment: 8, 
diff --git a/llvm/test/CodeGen/AArch64/ldst-nopreidx-sp-redzone.mir b/llvm/test/CodeGen/AArch64/ldst-nopreidx-sp-redzone.mir
index f1f9e5fbc9b087..b431de2d9b35b3 100644
--- a/llvm/test/CodeGen/AArch64/ldst-nopreidx-sp-redzone.mir
+++ b/llvm/test/CodeGen/AArch64/ldst-nopreidx-sp-redzone.mir
@@ -103,8 +103,8 @@ frameInfo:
   hasVAStart:      false
   hasMustTailInVarArgFunc: false
   localFrameSize:  480
-  savePoint:       ''
-  restorePoint:    ''
+  savePoints:      []
+  restorePoints:   []
 fixedStack:      []
 stack:
   - { id: 0, name: StackGuardSlot, type: default, offset: -40, size: 8, 
@@ -216,8 +216,8 @@ frameInfo:
   hasVAStart:      false
   hasMustTailInVarArgFunc: false
   localFrameSize:  480
-  savePoint:       ''
-  restorePoint:    ''
+  savePoints:      []
+  restorePoints:   []
 fixedStack:      []
 stack:
   - { id: 0, name: StackGuardSlot, type: default, offset: -40, size: 8, 
@@ -327,8 +327,8 @@ frameInfo:
   hasVAStart:      false
   hasMustTailInVarArgFunc: false
   localFrameSize:  480
-  savePoint:       ''
-  restorePoint:    ''
+  savePoints:      []
+  restorePoints:   []
 fixedStack:      []
 stack:
   - { id: 0, name: StackGuardSlot, type: default, offset: -40, size: 8, 
diff --git a/llvm/test/CodeGen/AArch64/live-debugvalues-sve.mir b/llvm/test/CodeGen/AArch64/live-debugvalues-sve.mir
index 612453ab53f438..4be16228814a3b 100644
--- a/llvm/test/CodeGen/AArch64/live-debugvalues-sve.mir
+++ b/llvm/test/CodeGen/AArch64/live-debugvalues-sve.mir
@@ -120,8 +120,10 @@ frameInfo:
   adjustsStack:    true
   hasC...
[truncated]

@enoskova-sc
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@arsenm, could you take a look, please.

@@ -86,8 +86,8 @@ frameInfo:
hasMustTailInVarArgFunc: false
hasTailCall: false
localFrameSize: 0
savePoint: ''
restorePoint: ''
savePoints: []
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You will cut out a huge amount of spurious diff if you teach the parser to support both the singular and plural forms here.

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Аddressed. Now MIR can be consumed both in singular:
savePoint: '%bb.1'
and plural:

savePoint:
    - point:           '%bb.1'

formats.
But printed in only plural format.

MachineBasicBlock *SRP) {
std::string Str;
yaml::SRPEntry Entry;
raw_string_ostream StrOS(Str);
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raw_svector_ostream + SmallVector

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addressed

raw_string_ostream StrOS(Str);
StrOS << printMBBReference(*SRP);
Entry.Point = StrOS.str();
Str.clear();
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Don't need this

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addressed

@@ -610,6 +610,20 @@ LLVM_YAML_IS_SEQUENCE_VECTOR(llvm::yaml::MachineJumpTable::Entry)
namespace llvm {
namespace yaml {

struct SRPEntry {
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nit: rename to SaveRestorePointEntry? I don't think SRP is a common acronym. Also please add a docstring.

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addressed

raw_string_ostream StrOS(YamlMFI.RestorePoint.Value);
StrOS << printMBBReference(*MFI.getRestorePoint());
}
if (MFI.getSavePoint())
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Here we have singular getSavePoint, plural YamlMFI.SavePoints, and singular getSavePoint again. It is a little weird that we're mixing singular and plural.

This makes me think that we should get rid of SavePoint and RestorePoint and replace it entirely with the plural SavePoints and RestorePoints. By this I mean SavePoint and RestorePoint should be replaced entirely in MIR with SavePoints and RestorePoints. There plural version can do everything the singular version can and more.

This could be done in a follow up patch if others agree this would be a good direction to move in.

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I can do it it the follow up patch.

@michaelmaitland
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I think this patch is due for a rebase :)

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Reverse ping!

@enoskova-sc
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@michaelmaitland, I was on long vacations. This week I plan to return to work on this MR:)

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@michaelmaitland, I was on long vacations. This week I plan to return to work on this MR:)

Lovely, I hope you had a wonderful vacation! Excited to give review and drive this forward.

@enoskova-sc enoskova-sc force-pushed the users/enoskova-sc/multiple-save-restore-points-mir branch from 37c305d to 1daee32 Compare February 12, 2025 09:16
Currently mir supports only one save and one restore point specification:

```
  savePoint:       '%bb.1'
  restorePoint:    '%bb.2'
```

This patch provide possibility to specify multiple save and multiple restore points in mir:

```
  savePoint:
    - point:           '%bb.1'
  restorePoint:
    - point:           '%bb.2'
```
while maintaining backward compatibility.
@enoskova-sc enoskova-sc force-pushed the users/enoskova-sc/multiple-save-restore-points-mir branch from 1daee32 to baaea8d Compare February 12, 2025 13:21
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Should we have a test that shows multiple save points and multiple restore points?

@enoskova-sc
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@michaelmaitland, now multiple save and restore points are not supported in shrink-wrap. This patch only support possibility to print them in MIR. Real multiple save/restore points can appear only in #119359.

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@michaelmaitland, @preames, @arsenm, I have addressed everything. Do you have any other comments?

if (VectorRepr.empty())
return false;

const auto &Entry = VectorRepr.front();
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Unless I'm missing something from the code structure, you're only parsing the first bb reference here. Also, you don't seem to have any tests for round tripping MIR with multiple save restore points.

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Test was added, code fixed

@michaelmaitland
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@michaelmaitland, now multiple save and restore points are not supported in shrink-wrap. This patch only support possibility to print them in MIR. Real multiple save/restore points can appear only in #119359.

Can we have parser tests to show that it can consume multiple save/restore points?


--- |

define i32 @foo(i32 %a, i32 %b) {
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Is the IR section needed?

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In my new commit I added support for "multiple" save/restore points in MFI, because without it I can't create a test.
The added test is quite synthetic, but it checks the capabilities of the MIRParser and MIRPrinter.

maxAlignment: 4
hasCalls: true
savePoint:
- point: '%bb.1'
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@michaelmaitland michaelmaitland Mar 3, 2025

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Since there are now multiple save points, how do we know what gets saved in which basic block? Do you need each point to contain the basic block, and the registers saved in that block?

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Actually, true support for multiple points (with registers) is implemented in the follow-up patch, which is quite huge (#119358). Initially, this PR was intended to only contain changes, related to parsing and printing, but in such approach no test can be provided.
I can add the information about registers, but the PR will become more complicated.

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Thanks for pointing me to that follow up patch. I think I would prefer to see this PR contain information about the registers despite this PR becoming more complicated. My reasoning is based on three things:

  1. It is difficult to write a test for just this PR without it.
  2. The parsing and printing here is missing necessary information (registers) that is needed for multiple save/restore points. What does it mean to have MIR with multiple save/restore points without registers associated (garbage?)?
  3. It looks like a large portion of diff in [llvm][RISCV] Support multiple save/restore points in prolog-epilog #119358 is related to test cases, not actual code.

@preames do you have an opinion here?

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I think we should combine the two PRs.

The parsing and printing here is missing necessary information (registers) that is needed for multiple save/restore points. What does it mean to have MIR with multiple save/restore points without registers associated (garbage?)?

This point is the main reason why. This PR, without specifying which registers are saved at which restore points create an ambiguity for shrink wrapping. Currently shrink wrapping only supports save/restore to a single basic block. What does it mean for shrink wrapping when there is multiple save/restore blocks (i.e. this PR is merged)?

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Does this test need updating? What do the points correspond to? registers? frame idxs?

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test is updated, now it contains registers

@enoskova-sc
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@michaelmaitland, do you want me to update this MR, adding information about registers, or should we wait for @preames to leave an opinion?

@michaelmaitland
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@michaelmaitland, do you want me to update this MR, adding information about registers, or should we wait for @preames to leave an opinion?

I thought I responded to this. Sorry. I'd like to see it updated in this PR to avoid the listed concerns.

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@michaelmaitland, I'll do it soon.

With this patch the possibility to store multiple Save and Restore points in MachineFrameInfo appears.
As the logical consequnce of it, the notions "Save point" / "Restore point"
are no longer synonyms for "Prolog" / "Epilog". Currently, "Prolog" / "Epilog"
is the place for stack allocation / deallocation and
"Save point" / "Restore point" is the place for register spills and restores.
So, now we need to store in MachineFrameInfo not only vector of Save and vector of Restore blocks,
but Prolog and Epilog.

As we assume to have multiple Save and Restore points we need to know the list of registers,
we store / restore in each point. Threfore our SavePoint become a pair <MachineBasicBlock, std::vector<Register>>.

The full support for operating with multiple Save / Restore points is supported only in RISCV backend.
SaveRestorePoints Pts{};
for (auto &Src : SRP) {
Pts.insert(std::make_pair(BBMap.find(Src.first)->second, Src.second));
}
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Drop braces on single statement body

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addressed

return Pts;
}

void setRestorePoint(MachineBasicBlock *MBB, std::vector<Register> &Regs) {
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There are no callers of this function. Drop it?

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addressed

ArrayRef<MachineBasicBlock *> restoredIn() const { return RestoredIn; }
void addSpilledIn(MachineBasicBlock *MBB) { SpilledIn.push_back(MBB); }
void addRestoredIn(MachineBasicBlock *MBB) { RestoredIn.push_back(MBB); }
void setSpilledIn(std::vector<MachineBasicBlock *> BBV) {
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There are no callers of this function. Drop it?

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no longer actual

void setSpilledIn(std::vector<MachineBasicBlock *> BBV) {
SpilledIn = std::move(BBV);
}
void setRestoredIn(std::vector<MachineBasicBlock *> BBV) {
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There are no callers of this function. Drop it?

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addressed

@@ -37,6 +52,8 @@ class CalleeSavedInfo {
int FrameIdx;
unsigned DstReg;
};
std::vector<MachineBasicBlock *> SpilledIn;
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Should we reuse CSInfoPerSave and CSInfoPerRestore instead of duplicating this information to reduce memory footprint? I think those data structures contain MBB that is spilled in and restored in respectively.

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Adressed. Now we have one structure called SaveRestorePoints.

RestorePoints = std::move(NewRestorePoints);
}

void setSavePoint(MachineBasicBlock *MBB, const std::vector<Register> &Regs) {
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There are no callers of this function. Drop it?

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addressed

@@ -27,6 +27,21 @@ class MachineBasicBlock;
class BitVector;
class AllocaInst;

using SaveRestorePoints = DenseMap<MachineBasicBlock *, std::vector<Register>>;

class CalleeSavedInfoPerBB {
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This class is almost the same as SaveRestorePoints with some extra helper functions? Maybe we could combine the two?

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Adressed. Now we have one structure called SaveRestorePoints.

@@ -295,6 +322,10 @@ class MachineFrameInfo {
/// Has CSInfo been set yet?
bool CSIValid = false;

CalleeSavedInfoPerBB CSInfoPerSave;
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If we combine SavePoints and CalleeSavedInfoPerBB and also combine RestorePoints with CSInfoPerRestore, then we may be able to drop these objects and save memory?

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Adressed. Now we have one structure called SaveRestorePoints.

@michaelmaitland
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@enoskova-sc Thanks for combining the two PR's this is looking really great!

return false;
if (parseMBBReference(PFS, MBB, StringRepr))
return true;
SRPoints.insert(std::make_pair(MBB, Registers));
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Registers will be empty here. Will this mean that all CSRs must be spilled/restored or no CSRs must be spilled? It probably means that all CSRs must be spilled/restored in this MBB. Maybe this should be documented on the data structure definition?

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addressed

return CS.getFrameIdx() == FrameIndex;
});

if (It != CSI.end()) {
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IS it possible for this condition to be false? If so, will SpilledIn and RestoredIn be nullptr below? I think that would be an issue. If it cannot be false, maybe we should drop the if statement here.

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addressed

SpilledIn = *It->spilledIn().begin();

else if (MI.mayLoad() && !It->restoredIn().empty())
RestoredIn = *It->restoredIn().begin();
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Should this be restoredIn().end() in order to get the last basic block it needs to be restored in?

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no longer actual

@@ -1867,13 +1910,13 @@ bool RISCVFrameLowering::spillCalleeSavedRegisters(
return true;

MachineFunction *MF = MBB.getParent();
auto *RVFI = MF->getInfo<RISCVMachineFunctionInfo>();
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Is this diff related to the patch?

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addressed

// directives.
emitCFIForCSI<CFISaveRegisterEmitter>(MBB, MBBI, getUnmanagedCSI(MF, CSI));
int Distance = getUnmanagedCSI(MF, CSI).size();
if (!RVFI->isPushable(MF) && !RVFI->useSaveRestoreLibCalls(MF))
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Can you help me understand why this is needed for this patch?

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This piece of code originally aimed to skip stores of CSRs and right after these stores emit one CFI instruction for one store.
As in this patch I moved CFI instruction emission to the spillCalleeSavedRegisters (because spills can appear not only in Prolog) here we need to remove CFI emission and skip 2*(num of CSRs): 1 for spill + 1 for CFI.


// Skip to before the restores of scalar callee-saved registers
// FIXME: assumes exactly one instruction is used to restore each
// callee-saved register.
auto FirstScalarCSRRestoreInsn =
std::next(MBBI, getRVVCalleeSavedInfo(MF, CSI).size());
int Distance = getUnmanagedCSI(MF, CSI).size();
auto LastFrameDestroy = std::prev(MBBI, Distance);
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Can you help me understand why this is needed for this patch?

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no longer actual

@enoskova-sc
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@michaelmaitland, tank you for quick review and sorry for delay, I have a lot of another important tasks. I'm still working on this patch and will publish changes, as soon as possible.

Comment on lines +649 to +650
using SaveRestorePoints =
std::variant<std::vector<SaveRestorePointEntry>, StringValue>;
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I don't understand why this is a variant, and not just the vector of points

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Several comments above (#119357 (comment)) @preames suggested to make support for multiple save/restore points backward compatible with single save/restore point approach.
It helped to "cut out a huge amount of spurious diff". So, StringValue in this variant needed for backward compatibility.

YamlIO.mapOptional(
"savePoint", MFI.SavePoints,
SaveRestorePoints(
StringValue())); // Don't print it out when it's empty.
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Empty list?

void set(PointsMap CSI) { Map = std::move(CSI); }

MachineBasicBlock *findAny(const CalleeSavedInfo &Match) const {
for (auto [BB, CSIV] : Map)
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braces

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addressed

public:
const PointsMap &get() const { return Map; }

const std::vector<CalleeSavedInfo> getCSInfo(MachineBasicBlock *MBB) const {
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Avoid vector copy, just return ArrayRef?

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Lookup here returns a default constructed vector, if MBB isn't found, ref on this vector is dangling.

return Map.lookup(MBB);
}

void set(PointsMap CSI) { Map = std::move(CSI); }
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missing &&??

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addressed

Comment on lines 685 to 686
std::vector<CalleeSavedInfo> CSIV = {};
std::vector<CalleeSavedInfo> GCSIV = {};
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Suggested change
std::vector<CalleeSavedInfo> CSIV = {};
std::vector<CalleeSavedInfo> GCSIV = {};
std::vector<CalleeSavedInfo> CSIV;
std::vector<CalleeSavedInfo> GCSIV;

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addressed

Comment on lines 713 to 714
if (Inner.contains(BB)) {
Inner[BB].push_back(*RTI.second);
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Avoid the double map lookup

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addressed

for (auto BB : PrologEpilogBlocks) {
if (Inner.contains(BB)) {
Inner[BB].push_back(*RTI.second);
std::sort(Inner[BB].begin(), Inner[BB].end(),
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Quadruple map lookup

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addressed

Comment on lines 765 to 766
fillCSInfoPerBB(MFI, RegToInfo, PrologBlocks, true /* isSave */);
fillCSInfoPerBB(MFI, RegToInfo, EpilogBlocks, false /* isSave */);
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Suggested change
fillCSInfoPerBB(MFI, RegToInfo, PrologBlocks, true /* isSave */);
fillCSInfoPerBB(MFI, RegToInfo, EpilogBlocks, false /* isSave */);
fillCSInfoPerBB(MFI, RegToInfo, PrologBlocks, /*isSave=*/true);
fillCSInfoPerBB(MFI, RegToInfo, EpilogBlocks, /*isSave=*/false);

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addressed

SaveRestorePoints::PointsMap RestorePts;
for (MachineBasicBlock *EpilogBlock : EpilogBlocks)
RestorePts.insert({EpilogBlock, MFI.getCalleeSavedInfo()});
MFI.setRestorePoints(RestorePts);
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std::move, or just have MFI directly manage each insertion?

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addressed

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