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[LLDB] LoongArch has missing aliases for register
backend:loongarch
lldb
#123903
opened Jan 22, 2025 by
patryk4815
[lld][LoongArch] GOT indirection to PC relative optimization
backend:loongarch
lld:ELF
lld
#123743
opened Jan 21, 2025 by
ylzsx
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[lld][LoongArch] Support relaxation during TLSDESC GD/LD to IE/LE conversion
backend:loongarch
lld:ELF
lld
#123730
opened Jan 21, 2025 by
ylzsx
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[lld][LoongArch] Support TLSDESC GD/LD to IE/LE
backend:loongarch
lld:ELF
lld
#123715
opened Jan 21, 2025 by
ylzsx
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[lld][LoongArch] Support relaxation during IE to LE conversion
backend:loongarch
lld:ELF
lld
#123702
opened Jan 21, 2025 by
ylzsx
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[lld][LoongArch] Convert TLS IE to LE in the normal or medium code model
backend:loongarch
lld:ELF
lld
#123680
opened Jan 21, 2025 by
ylzsx
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[lld][LoongArch] Relax TLSDESC code sequence
backend:loongarch
lld:ELF
lld
#123677
opened Jan 21, 2025 by
ylzsx
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[lld][LoongArch] Relax TLS LE/GD/LD
backend:loongarch
lld:ELF
lld
#123600
opened Jan 20, 2025 by
ylzsx
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[lld][LoongArch] Relax call36/tail36: R_LARCH_CALL36
backend:loongarch
lld:ELF
lld
#123576
opened Jan 20, 2025 by
ylzsx
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[lld][LoongArch] Relax PCHi20Lo12: R_LARCH_{PCALA,GOT_PC}_{HI20,LO12}
backend:loongarch
lld:ELF
lld
#123566
opened Jan 20, 2025 by
ylzsx
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[lld][LoongArch] Default disable linker relaxation in LoongArch.
backend:loongarch
lld:ELF
lld
#123017
opened Jan 15, 2025 by
ylzsx
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[LoongArch] Merge base and offset for tls-le code sequence
backend:loongarch
#122999
opened Jan 15, 2025 by
zhaoqi5
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[LoongArch] Pre-commit tests for tls-le merge base offset. NFC
backend:loongarch
#122998
opened Jan 15, 2025 by
zhaoqi5
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DAG: Handle load in SimplifyDemandedVectorElts
backend:AArch64
backend:AMDGPU
backend:ARM
backend:loongarch
backend:NVPTX
backend:PowerPC
backend:X86
llvm:SelectionDAG
SelectionDAGISel as well
#122671
opened Jan 13, 2025 by
arsenm
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[IR][AsmParser] Revamp how floating-point literals work in LLVM IR.
backend:AArch64
backend:AMDGPU
backend:ARM
backend:DirectX
backend:Hexagon
backend:loongarch
backend:NVPTX
backend:PowerPC
backend:RISC-V
backend:SPIR-V
backend:SystemZ
backend:WebAssembly
backend:X86
clang:openmp
OpenMP related changes to Clang
clang
Clang issues not falling into any other category
debuginfo
HLSL
HLSL Language Support
llvm:adt
llvm:analysis
llvm:globalisel
llvm:instcombine
llvm:ir
llvm:support
llvm:transforms
#121838
opened Jan 6, 2025 by
jcranmer-intel
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[CodeGen] Add MachineRegisterClassInfo analysis pass
backend:AArch64
backend:AMDGPU
backend:ARM
backend:loongarch
backend:PowerPC
backend:X86
llvm:regalloc
#120690
opened Dec 20, 2024 by
wangpc-pp
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[RISC-V] Fix incorrect epilogue_begin
backend:AArch64
backend:AMDGPU
backend:ARM
backend:Hexagon
backend:loongarch
backend:m68k
backend:MSP430
backend:NVPTX
backend:PowerPC
backend:RISC-V
backend:Sparc
backend:SystemZ
backend:X86
backend:Xtensa
debuginfo
#120623
opened Dec 19, 2024 by
RamNalamothu
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Patch series to reapply #118734 and substantially improve it
backend:AArch64
backend:AMDGPU
backend:ARM
backend:DirectX
backend:Hexagon
backend:loongarch
backend:m68k
backend:MSP430
backend:PowerPC
backend:RISC-V
backend:Sparc
backend:SystemZ
backend:WebAssembly
backend:X86
backend:Xtensa
clang:codegen
clang:frontend
Language frontend issues, e.g. anything involving "Sema"
clang:static analyzer
clang
Clang issues not falling into any other category
#120534
opened Dec 19, 2024 by
chandlerc
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[TRI] Remove reserved registers in getRegPressureSetLimit
backend:AMDGPU
backend:ARM
backend:loongarch
backend:NVPTX
backend:PowerPC
backend:X86
llvm:globalisel
llvm:regalloc
llvm:transforms
tablegen
#118787
opened Dec 5, 2024 by
wangpc-pp
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[LoongArch][GlobalISel] Adding initial GlobalISel infrastructure
backend:loongarch
llvm:globalisel
#116005
opened Nov 13, 2024 by
zhaoqi5
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LLDB LoongArch support
backend:loongarch
lldb
metabug
Issue to collect references to a group of similar or related issues.
#112693
opened Oct 17, 2024 by
SixWeining
7 tasks done
flang/LoongArch "Do not know how to promote this operator" in DAG->DAG Pattern Instruction Selection
backend:loongarch
crash
Prefer [crash-on-valid] or [crash-on-invalid]
#110995
opened Oct 3, 2024 by
martin-frbg
Clang tooling generated visibility macros for Clang
backend:AArch64
backend:AMDGPU
backend:ARM
backend:Hexagon
backend:loongarch
backend:PowerPC
backend:RISC-V
backend:SystemZ
backend:WebAssembly
backend:X86
clang:analysis
clang:codegen
clang:dataflow
Clang Dataflow Analysis framework - https://clang.llvm.org/docs/DataFlowAnalysisIntro.html
clang:frontend
Language frontend issues, e.g. anything involving "Sema"
clang:modules
C++20 modules and Clang Header Modules
clang:openmp
OpenMP related changes to Clang
clang:static analyzer
clang
Clang issues not falling into any other category
clang-format
ClangIR
Anything related to the ClangIR project
HLSL
HLSL Language Support
xray
#109702
opened Sep 23, 2024 by
fsfod
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SelectionDAG: Support nofpclass
backend:AMDGPU
backend:loongarch
backend:X86
floating-point
Floating-point math
llvm:SelectionDAG
SelectionDAGISel as well
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