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Issues list

Add a high latency "feature" (hazard) for specific shift instruction operands on Alder Lake and generic x86-64 tunings backend:X86 Scheduler Models Accuracy of X86 scheduler models backend:X86
#121546 opened Jan 3, 2025 by chandlerc
10
[MCA] Inaccuracy in small snippet backend:X86 Scheduler Models Accuracy of X86 scheduler models tools:llvm-mca
#99395 opened Jul 17, 2024 by boomanaiden154
@adibiagio @boomanaiden154
4
[llvm-exegesis] Analysis reporting bad match even with exactly the same capture backend:X86 Scheduler Models Accuracy of X86 scheduler models tools:llvm-exegesis
#84776 opened Mar 11, 2024 by RKSimon
1
LLVM MCA claims Skylake can issue 6 instructions per clock backend:X86 Scheduler Models Accuracy of X86 scheduler models backend:X86
#82908 opened Feb 25, 2024 by SeeSpring
4
[X86] movb is extremely expensive on modern processors backend:X86 Scheduler Models Accuracy of X86 scheduler models backend:X86
#62948 opened May 26, 2023 by ryao
6
[llvm-mca] Add support for MCWriteProcResEntry::StartAtCycle backend:X86 Scheduler Models Accuracy of X86 scheduler models tools:llvm-mca
#62681 opened May 12, 2023 by RKSimon
1
[MCA] ADC executed when carry not generated backend:X86 Scheduler Models Accuracy of X86 scheduler models backend:X86 tools:llvm-mca
#62507 opened May 3, 2023 by 837951602
7
[X86] X86SchedAlderlakeP.td is missing dependency breaking idioms backend:X86 Scheduler Models Accuracy of X86 scheduler models backend:X86
#61003 opened Feb 26, 2023 by RKSimon
3
Add slow LEA schedule information for Intel CPUs backend:X86 Scheduler Models Accuracy of X86 scheduler models backend:X86
#60043 opened Jan 15, 2023 by phoebewang
1
[X86] Back merge some of the znver3 model features to znver1/znver2 models backend:X86 Scheduler Models Accuracy of X86 scheduler models backend:X86 bugzilla Issues migrated from bugzilla
#49704 opened May 16, 2021 by RKSimon
[MCA] Multiple Int schedulers backend:X86 Scheduler Models Accuracy of X86 scheduler models bugzilla Issues migrated from bugzilla tools:llvm-mca
#49694 opened May 15, 2021 by LebedevRI
1
FFT and Sparse matmult in Scimark2 are slower with -O2 & -O3 than -O1 backend:X86 Scheduler Models Accuracy of X86 scheduler models backend:X86 bugzilla Issues migrated from bugzilla
#42921 opened Oct 6, 2019 by llvmbot
5
[X86] Broadwell load latencies don't match similar targets backend:X86 Scheduler Models Accuracy of X86 scheduler models backend:X86 bugzilla Issues migrated from bugzilla
#38536 opened Oct 5, 2018 by RKSimon
[x86] Add RetireControlUnit/RegisterFile descriptors to scheduling models. backend:X86 Scheduler Models Accuracy of X86 scheduler models backend:X86 bugzilla Issues migrated from bugzilla
#37202 opened Jun 19, 2018 by adibiagio
[X86] Scheduler models should use UnsupportedFeatures to indicate unsupported ISAs backend:X86 Scheduler Models Accuracy of X86 scheduler models backend:X86 bugzilla Issues migrated from bugzilla
#36949 opened May 27, 2018 by RKSimon
7
Add a scheduling model for Nehalem backend:X86 Scheduler Models Accuracy of X86 scheduler models backend:X86 bugzilla Issues migrated from bugzilla
#36855 opened May 17, 2018 by jrmuizel
3
[TableGen] Add more checks to the subtarget emitter to validate scheduling information. backend:X86 Scheduler Models Accuracy of X86 scheduler models bugzilla Issues migrated from bugzilla tablegen
#36658 opened May 2, 2018 by llvmbot
2
[X86] Review current scheduler classes to minimise need for InstRW overrides backend:X86 Scheduler Models Accuracy of X86 scheduler models backend:X86 bugzilla Issues migrated from bugzilla
#36479 opened Apr 14, 2018 by RKSimon
[X86] Atom scheduler generating incorrect throughputs and latencies backend:X86 Scheduler Models Accuracy of X86 scheduler models backend:X86 bugzilla Issues migrated from bugzilla
#36243 opened Mar 26, 2018 by topperc
10
[X86] AVX512 truncate instructions marked as loads backend:X86 Scheduler Models Accuracy of X86 scheduler models backend:X86 bugzilla Issues migrated from bugzilla
#36236 opened Mar 24, 2018 by topperc
[X86] SkylakeServer scheduler model doesn't account for port 0 and 1 being joined for 512 bit operations backend:X86 Scheduler Models Accuracy of X86 scheduler models backend:X86 bugzilla Issues migrated from bugzilla
#36176 opened Mar 20, 2018 by topperc
[X86] MMX_MASKMOVQ, MMX_MASKMOVQ64, MASKMOVDQU, VMASKMOVDQU missing from Sandybrige/Haswell/Broadwell/Skylake scheduler models backend:X86 Scheduler Models Accuracy of X86 scheduler models backend:X86 bugzilla Issues migrated from bugzilla
#36128 opened Mar 18, 2018 by topperc
1
[llvm-exegesis] Evaluate Intel X86 register-register move scheduling info backend:X86 Scheduler Models Accuracy of X86 scheduler models backend:X86 bugzilla Issues migrated from bugzilla tools:llvm-exegesis
#36073 opened Mar 14, 2018 by llvmbot
2
Derive TTI instruction costs from scheduling models backend:X86 Scheduler Models Accuracy of X86 scheduler models bugzilla Issues migrated from bugzilla
#35898 opened Feb 28, 2018 by RKSimon
@RKSimon
8
[X86] Incorrect scheduler information for scalar multiplies in Znver1 scheduler model backend:X86 Scheduler Models Accuracy of X86 scheduler models backend:X86 bugzilla Issues migrated from bugzilla
#35461 opened Jan 26, 2018 by topperc
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