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Add a high latency "feature" (hazard) for specific shift instruction operands on Alder Lake and generic x86-64 tunings

backend:X86

backend:X86 Scheduler ModelsAccuracy of X86 scheduler modelsAccuracy of X86 scheduler models

Status: Open.

#121546 In llvm/llvm-project;

· chandlerc opened on Jan 3, 2025

[MCA] Inaccuracy in small snippet

backend:X86 Scheduler ModelsAccuracy of X86 scheduler modelsAccuracy of X86 scheduler models

tools:llvm-mca

Status: Open.

#99395 In llvm/llvm-project;

· boomanaiden154 opened on Jul 17, 2024

[llvm-exegesis] Analysis reporting bad match even with exactly the same capture

backend:X86 Scheduler ModelsAccuracy of X86 scheduler modelsAccuracy of X86 scheduler models

tools:llvm-exegesis

Status: Open.

#84776 In llvm/llvm-project;

· RKSimon opened on Mar 11, 2024

LLVM MCA claims Skylake can issue 6 instructions per clock

backend:X86

backend:X86 Scheduler ModelsAccuracy of X86 scheduler modelsAccuracy of X86 scheduler models

Status: Open.

#82908 In llvm/llvm-project;

· SeeSpring opened on Feb 25, 2024

[X86] movb is extremely expensive on modern processors

backend:X86

backend:X86 Scheduler ModelsAccuracy of X86 scheduler modelsAccuracy of X86 scheduler models

Status: Open.

#62948 In llvm/llvm-project;

· ryao opened on May 26, 2023

[llvm-mca] Add support for MCWriteProcResEntry::StartAtCycle

backend:X86 Scheduler ModelsAccuracy of X86 scheduler modelsAccuracy of X86 scheduler models

tools:llvm-mca

Status: Open.

#62681 In llvm/llvm-project;

· RKSimon opened on May 12, 2023

[MCA] ADC executed when carry not generated

backend:X86

backend:X86 Scheduler ModelsAccuracy of X86 scheduler modelsAccuracy of X86 scheduler models

tools:llvm-mca

Status: Open.

#62507 In llvm/llvm-project;

· 837951602 opened on May 3, 2023

[X86] X86SchedAlderlakeP.td is missing dependency breaking idioms

backend:X86

backend:X86 Scheduler ModelsAccuracy of X86 scheduler modelsAccuracy of X86 scheduler models

Status: Open.

#61003 In llvm/llvm-project;

· RKSimon opened on Feb 26, 2023

Add slow LEA schedule information for Intel CPUs

backend:X86

backend:X86 Scheduler ModelsAccuracy of X86 scheduler modelsAccuracy of X86 scheduler models

Status: Open.

#60043 In llvm/llvm-project;

· phoebewang opened on Jan 15, 2023

[X86] Back merge some of the znver3 model features to znver1/znver2 models

backend:X86

backend:X86 Scheduler ModelsAccuracy of X86 scheduler modelsAccuracy of X86 scheduler models

bugzillaIssues migrated from bugzillaIssues migrated from bugzilla

Status: Open.

#49704 In llvm/llvm-project;

· RKSimon opened on May 16, 2021

[MCA] Multiple Int schedulers

backend:X86 Scheduler ModelsAccuracy of X86 scheduler modelsAccuracy of X86 scheduler models

bugzillaIssues migrated from bugzillaIssues migrated from bugzilla

tools:llvm-mca

Status: Open.

#49694 In llvm/llvm-project;

· LebedevRI opened on May 15, 2021

FFT and Sparse matmult in Scimark2 are slower with <code>-O2</code> &amp; <code>-O3</code> than <code>-O1</code>

backend:X86

backend:X86 Scheduler ModelsAccuracy of X86 scheduler modelsAccuracy of X86 scheduler models

bugzillaIssues migrated from bugzillaIssues migrated from bugzilla

Status: Open.

#42921 In llvm/llvm-project;

· llvmbot opened on Oct 6, 2019