Search results

Vector-AND's with constant Vectors of <i64 {DDDD}, i64 poison> should not load the constant in through GPR's

backend:X86

Status: Open.

#145284 In llvm/llvm-project;

· Validark opened on Jun 23, 2025

Some <code>shufflevector</code>s should emit as a single <code>shld</code>/<code>shrd</code> instruction

backend:X86

Status: Open.

#145276 In llvm/llvm-project;

· Validark opened on Jun 23, 2025

Don't read from <code>vpcmpeqd xmm, xmm, xmm</code> and <code>vpternlogd zmm, zmm, zmm, 255</code> simultaneously

backend:X86

missed-optimization

Status: Open.

#144481 In llvm/llvm-project;

· Validark opened on Jun 17, 2025

[RISC-V V] Idea: Interleave independent op-chains by <code>vsetvli</code> category

backend:RISC-V

Status: Open.

#142814 In llvm/llvm-project;

· Validark opened on Jun 4, 2025

<code>(x &lt;&lt; 1) | 1</code> =&gt; <code>shld(x, 1, 0x80...)</code> for vectors (also <code>~(~x &lt;&lt; 1)</code> =&gt; <code>shld(x, 1, 0x80...)</code>)

missed-optimization

Status: Open.

#141710 In llvm/llvm-project;

· Validark opened on May 28, 2025

Make constant vector <code>&lt;i64 poison, i64 -9223372036854775808&gt;</code> able to reuse <code>&lt;i64 0, i64 -9223372036854775808&gt;</code>

backend:X86

Status: Open.

#141706 In llvm/llvm-project;

· Validark opened on May 28, 2025

[AVX-512] Propagating lowest bit to all bits in u64 lane should use <code>sra(sll(x, 63), 63)</code> instead of <code>neg(and(x, 1))</code>

backend:X86

missed-optimization

Status: Open.

#137575 In llvm/llvm-project;

· Validark opened on Apr 28, 2025

[AVX-512] <code>vpternlog</code> can be used even when a subexpression is consumed

backend:X86

Status: Open.

#137520 In llvm/llvm-project;

· Validark opened on Apr 27, 2025

[AVX-512] Fused-load doesn't work for <code>&lt;8 x i64&gt;{ (PowerOf2 - 1), 0, 0, 0, 0, 0, 0, 0 }</code>

backend:X86

Status: Open.

#136750 In llvm/llvm-project;

· Validark opened on Apr 22, 2025

[AVX-512] vpternlogq fails to be emitted for longer chains of bitmanipulations

backend:X86

missed-optimization

Status: Open.

#134768 In llvm/llvm-project;

· Validark opened on Apr 8, 2025

[x86-64 BMI2] Generating a bitstring with a <code>min(64, LEN)</code> 1 bits at the bottom should use <code>BZHI</code>

backend:X86

missed-optimization

Status: Open.

#132714 In llvm/llvm-project;

· Validark opened on Mar 24, 2025

[AVX-512] Consider that summing every odd element of an array can be done without gathers/perms

backend:X86

missed-optimization

Status: Open.

#132666 In llvm/llvm-project;

· Validark opened on Mar 24, 2025