Implement the `AddUint64` HLSL Function

[farzonl]

• Implement AddUint64 via use of the __builtin_addc clang builtin in hlsl_intrinsics.h
• (optional) If custom sema needed add sema checks for AddUint64 to CheckHLSLBuiltinFunctionCall in SemaHLSL.cpp
• Try to use llvm::Intrinsic::uadd_with_overflow codegen for AddUint64 in CGBuiltin.cpp
• Add codegen tests to clang/test/CodeGenHLSL/builtins/AddUint64.hlsl
• Add sema tests to clang/test/SemaHLSL/BuiltIns/AddUint64-errors.hlsl
• Create the DXILOpMapping of int_uadd_with_overflow to 44 in DXIL.td
• Create the AddUint64.ll and AddUint64_errors.ll tests in llvm/test/CodeGen/DirectX/
• Legalize int_uadd_with_overflow for SPIRV.

DirectX

DXIL Opcode	DXIL OpName	Shader Model	Shader Stages
44	UAddc	6.0	()

SPIR-V

There is no support for AddUint64 when targeting SPIR-V.

Test Case(s)

Example 1

//dxc AddUint64_test.hlsl -T lib_6_8 -enable-16bit-types -O0

export uint4 fn(uint4 p1, uint4 p2) {
    return AddUint64(p1, p2);
}

HLSL:

Syntax

uint<2> AddUint64(uint<2> a, uint<2> b);

uint<4> AddUint64(uint<4> a, uint<4> b);

Type Description

Name	Template Type	Component Type	Size
ret	vector	uint	2
a	vector	uint	2
b	vector	uint	2

Type Description

Name	Template Type	Component Type	Size
ret	vector	uint	4
a	vector	uint	4
b	vector	uint	4

Minimum Shader Model

This function is supported in the following shader models.

Shader Model	Supported
Shader Model 6 and higher shader models	yes

Shader Stages

See also

• Intrinsic Functions (DirectX HLSL)

[tex3d]

The point of this intrinsic is to implement a uint64_t add without requiring the native 64-bit feature.

This takes (one or two) pairs (low,high) of uint32 values and results in pairs (low,high) of uint32 values. It uses the UAddc (unsigned add with carry) to preserve the extra bit which it uses with zext and ordinary add instructions to implement a full uint64 add operation, resulting in the (low,high) part pairs. This intrinsic requires either a 2 or 4-length vector (so diagnostics need to be implemented for this).

; add low words with carry:
%13 = call %dx.types.i32c @dx.op.binaryWithCarryOrBorrow.i32(i32 44, i32 %5, i32 %1)  ; UAddc(a,b)
%14 = extractvalue %dx.types.i32c %13, 0 ; i32 low word result
%15 = extractvalue %dx.types.i32c %13, 1 ; i1 carry bit
%16 = zext i1 %15 to i32 ; extend carry bit to i32
%17 = add i32 %6, %2 ; add high words
%18 = add i32 %17, %16 ; add carry bit for high word result

SPIR-V has a OpIAddCarry operation which can be used in exactly the same way.
According to SPIR-V Spec: "Result is the unsigned integer addition of Operand 1 and Operand 2, including its carry."

LLVM already has an intrinsic llvm.uadd.with.overflow that we can use for IRGen, then we can just lower that to the respective DXIL or SPIR-V op in the backend.

[Icohedron]

I will work on this issue.