Closed
Description
Based on the #73424. There were several patches and issues on the vector saturating truncation operation on different platform.
For instance, #68466 for x86 and #75145 for RISC-V vector extension. I think it is better for us to do a target-independent combine for this operation, which could be expressed as a sequence of LLVM IR like:
define void @trunc_sat_i8i16(ptr %x, ptr %y) {
%1 = load <8 x i16>, ptr %x, align 16
%2 = tail call <8 x i16> @llvm.smax.v8i16(<8 x i16> %1, <8 x i16> <i16 -128, i16 -128, i16 -128, i16 -128, i16 -128, i16 -128, i16 -128, i16 -128>)
%3 = tail call <8 x i16> @llvm.smin.v8i16(<8 x i16> %2, <8 x i16> <i16 127, i16 127, i16 127, i16 127, i16 127, i16 127, i16 127, i16 127>)
%4 = trunc <8 x i16> %3 to <8 x i8>
store <8 x i8> %4, ptr %y, align 8
ret void
}
Especially, I think this combine could be done at the SelectionDAG, like the other saturating operation such as ISD::SADDSAT
. This could remove complex TableGen pattern matching and refactor each platform's CodeGen path for this operation.