thumb2, aclass, rclass, etc. ARM features not supported in clang -mcpu

[silversquirl]

Several ARM architecture features (and possibly for other archs too, but I only checked ARM) are not included in the table used to validate clang's -mcpu option. This makes it impossible to specify that, for example, thumb2 instructures are available on a CPU model that doesn't normally support them.

This is particularly annoying when using clang to compile assembly, as it will emit errors like this, while providing no way to enable thumb2 other than by running cc1as directly:

test.s:1:2: error: invalid instruction, any one of the following would fix this:
        mov r1, #0
        ^
test.s:1:10: note: operand must be a register in range [r0, r15]
        mov r1, #0
                ^
test.s:1:2: note: instruction requires: thumb2
        mov r1, #0
        ^

[davemgreen]

Can you explain more about what you are trying to do? -mcpu=cortex-m0plus+thumb2 isn't a valid combination (and I don't think should be). Depending on what you are trying to achieve, you may really want to specify a different cpu, or a different -march option that specifies an architecture with thumb2 available.

[silversquirl]

Cortex-M0+ supports a subset of the Thumb-2 instruction set - I'm trying to assemble a file that uses those instructions

[davemgreen]

The architecture is split into Armv6-m and Armv7-m. Cortex-M0+ is an Armv6-m core. Most 32bit instructions are Armv7-m. A few (BL for example, MRS and MSR, etc) are available in Armv6-m, but there are not many. This page has has an image in the "Instruction Set" section that shows some of the instructions (that are not covered up): https://community.arm.com/arm-community-blogs/b/architectures-and-processors-blog/posts/five-things-you-may-not-know-about-arm-cortex-m

MOV rn, #0 is not one of the 32bit instruction available in v6m though unfortunately, and Cortex-M0+ does not support it. It would need to use the flag setting 16bit MOVS Rn, #0 variant. If you had a Cortex-M0+ (armv6m) with thumb2 - you would just have armv7m :)

[MaskRay]

Working as intended as davemgreen explained. I think zig should specify a different -mcpu=.

[git-dimiz]

Hi,

sorry if I'm hijacking this conversation. But I think I have a similar problem. I'm trying to compile the following file:

    .code 16
    .section .text
    .global _start

_start:
    mov r0, #1

With the following compiler options:

clang -target arm-none-eabi -mcpu=cortex-m0 -mthumb -c main.s -o main.o

And get the following error:

main.s:6:5: error: invalid instruction, any one of the following would fix this:
    mov r0, #1
    ^
main.s:6:5: note: instruction requires: thumb2
    mov r0, #1
    ^
main.s:6:5: note: no flag-preserving variant of this instruction available
    mov r0, #1
    ^
main.s:6:13: note: operand must be a register in range [r0, r15]
    mov r0, #1

I didn't fully understand the answer from @davemgreen. According to the Cortex -M0 Devices Generic User Guide Which states:

The Cortex-M0 processor implements the ARMv6-M architecture, that implements the ARMv6-M Thumb instruction set, including Thumb-2 technology. This provides the exceptional performance expected of a modern 32-bit architecture, with a higher code density than other 8-bit and 16-bit microcontrollers.

And according to the ARM v6-M Architecture Reference Manual the given asm code mov r0, #1 should be valid? I don't even understand why it thinks that this is thumb2.

Am I doing something fundamentally wrong? Or is this a bug?

[davemgreen]

Hi - it sounds like you need to use a movs, not a mov. They are different instructions as movs sets conditions status flags, but providing that is OK for your use-case it should be fine. (Just make sure it is not clobbering existing flags). Unfortunately there is no mov r0, #1 (that doesn't set flags) on the cortex-m0.

[git-dimiz]

Oh wow, you are right. movs did the trick. I didn't realize that clang is more strict. Because I cross checked with the gnu binutils as. There this code worked fine and as "expected". Thanks for the quick reply and clarification!