Emit third operand for the rdhwr instruction on MIPS64 < R6 #38209
Description
| Bugzilla Link | 38861 |
| Resolution | FIXED |
| Resolved on | Nov 15, 2018 21:23 |
| Version | trunk |
| OS | All |
| Blocks | #38454 |
| CC | @jrtc27,@sylvestre,@tstellar |
| Fixed by commit(s) | r341919 r346739 |
Extended Description
MIPS ISAs before "Revision 6" do not support third operand for the rdhwr instruction. But LLVM generates three-operands version of the instruction on any MIPS64 ISAs. This is regression caused by r335162.
% cat test.ll
declare i8* @llvm.thread.pointer() nounwind readnone
define i8* @thread_pointer() {
%1 = tail call i8* @llvm.thread.pointer()
ret i8* %1
}
% llc -march=mips64 < test.ll
...
rdhwr $3, $29, 0
% llc -march=mips < test.ll
...
rdhwr $3, $29