AVX10 feature mismatch between GCC and LLVM

[sayantn]

The Intel Software Developers Manual (March 2025) specifies that AVX10.1 supports the following AVX512 instruction families (Volume 1, Table 16-2)

• AVX512F
• AVX512CD
• AVX512BW
• AVX512DQ
• AVX512VBMI
• AVX512IFMA
• AVX512VNNI
• AVX512BF16
• AVX512VPOPCNTDQ
• AVX512VBMI2
• VAES
• GFNI
• VPCLMULQDQ
• AVX512-BITALG
• AVX512-FP16

With the following additional note

VAES, VPCLMULQDQ, and GFNI EVEX instructions will be supported on Intel AVX10.1 machines but will continue to be enumerated by their existing discrete CPUID feature flags. This requires the developer to check for both the feature and Intel AVX10, e.g., {AVX10.1 AND VAES}.

GCC and LLVM agree to enable all avx512* features, but they do not seem to agree about vaes, vpclmulqdq and gfni

• Running gcc -mavx10.1-512 -Q --help=target shows that avx10.1-512 implies none of GFNI, VAES and VPCLMULQDQ
• Examining X86.td shows that avx10.1-512 implies only VAES and VPCLMULQDQ, not GFNI

Both seems to be following the Intel spec, but in different ways, which is not good for the ecosystem in general, and creates more confusion between end users. This would probably require some collaboration with GCC (and possible Intel too).

GCC version

gcc (GCC) 14.2.1 20250207
Copyright (C) 2024 Free Software Foundation, Inc.
This is free software; see the source for copying conditions.  There is NO
warranty; not even for MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.

[llvmbot]

@llvm/issue-subscribers-backend-x86

Author: Sayantan Chakraborty (sayantn)

The Intel Software Developers Manual (March 2025) specifies that AVX10.1 supports the following AVX512 instruction families (Volume 1, Table 16-2) - AVX512F - AVX512CD - AVX512BW - AVX512DQ - AVX512VBMI - AVX512IFMA - AVX512VNNI - AVX512BF16 - AVX512VPOPCNTDQ - AVX512VBMI2 - VAES - GFNI - VPCLMULQDQ - AVX512-BITALG - AVX512-FP16

With the following additional note
> VAES, VPCLMULQDQ, and GFNI EVEX instructions will be supported on Intel AVX10.1 machines but will continue to be enumerated by their existing discrete CPUID feature flags. This requires the developer to check for both the feature and Intel AVX10, e.g., {AVX10.1 AND VAES}.

GCC and LLVM agree to enable all avx512* features, but they do not seem to agree about vaes, vpclmulqdq and gfni

• Running gcc -mavx10.1-512 -Q --help=target shows that avx10.1-512 implies none of GFNI, VAES and VPCLMULQDQ
• Examining X86.td shows that avx10.1-512 implies only VAES and VPCLMULQDQ, not GFNI

Both seems to be following the Intel spec, but in different ways, which is not good for the ecosystem in general, and creates more confusion between end users. This would probably require some collaboration with GCC (and possible Intel too).

GCC version

gcc (GCC) 14.2.1 20250207
Copyright (C) 2024 Free Software Foundation, Inc.
This is free software; see the source for copying conditions.  There is NO
warranty; not even for MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.

[pinskia]

Note gcc (GCC) 14.2.1 20250207 is pre the change to AVX10 to GCC. It was backported on Feb 18th to GCC 14 branch.
So you might want to recompare again. And there was the avx10.1 change to include 512 on March 24th.

[sayantn]

Even in the current git version (see here) avx10.1-512 only implies the avx512* target features, none of vaes, vpclmulqdq and gfni

[phoebewang]

Thanks for the report! According to latest SDM, both vaes and vpclmulqdq require a second flag. I'll change it in LLVM side.