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Commits on Feb 5, 2025

• [RISCV] Enable RVV ABD tests with i64 elements (#124246)

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• [RISCV] Add test coverage for memmove (#120232)

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Commits on Jan 22, 2025

• [MCA] Use MCInstrAnalysis to analyse call/return instructions (#123882)

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• [RISCV] Add precommit test for #123882

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Commits on Jan 13, 2025

• Reapply "[RISCV] Rework memcpy test (#120364)"

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• Revert "[RISCV] Rework memcpy test" (#122662)

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• [RISCV] Rework memcpy test (#120364)

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Commits on Jan 9, 2025

• [MachineLICM] Use RegisterClassInfo::getRegPressureSetLimit (#119826)

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Commits on Jan 3, 2025

• [PowerPC] Use RegisterClassInfo::getRegPressureSetLimit (#120383)

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• [RISCV] Allow tail memcmp expansion (#121460)

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Commits on Dec 31, 2024

• [RISCV] Add missing ReadFMA16Addend in UnsupportedSchedZfh

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• [RISCV] Fix typo: vmv.x.i -> vmv.v.i

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Commits on Dec 23, 2024

• [TRI][RISCV] Add methods to get common register class of two registers (#118435)

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Commits on Dec 20, 2024

• [MachinePipeliner] Remove unused private field MF

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• [MachinePipeliner] Skip reserved registers when computing register pressure (#120694)

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• [ARM] Use RegisterClassInfo::getRegPressureSetLimit (#120377)

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Commits on Dec 19, 2024

• [RISCV][MCA] Move sifive-x280 tests to directory SiFiveX280 (#120522)

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• [RISCV] Add software pipeliner support (#117546)

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Commits on Dec 18, 2024

• Revert "[Exegesis][RISCV] Add RISCV support for llvm-exegesis (#89047)"

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• [MachinePipeliner] Use RegisterClassInfo::getRegPressureSetLimit (#119827)

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• [MachineSink] Use RegisterClassInfo::getRegPressureSetLimit (#119830)

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Commits on Dec 16, 2024

• [RISCV] Add tune info for postra scheduling direction (#115864)

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Commits on Dec 12, 2024

• [MISched] Unify the way to specify scheduling direction (#119518)

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Commits on Dec 10, 2024

• [MISched] Compare right next cluster node (#116584)

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• [RISCV] Add RUNs for different postra scheduling directions

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Commits on Dec 9, 2024

• [Hexagon][NFC] Switch regalloc-bad-undef.mir to use generated CHECKs

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Commits on Dec 6, 2024

• [RISCV] Add tune info for mem* expansion (#118439)

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Commits on Dec 5, 2024

• [Sched] Skip MemOp with unknown size when clustering (#118443)

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Commits on Nov 29, 2024

• [RISCV] Set a barrier between mask producer and user of V0 (#114012)

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Commits on Nov 28, 2024

• [RISCV] Add TuneDisableLatencySchedHeuristic

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• [RISCV] Rename some Feature* to Tune* (#117966)

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Commits on Nov 27, 2024

• [MISched] Use right boundary when trying latency heuristics (#116592)

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Commits on Nov 26, 2024

• [RISCV] Remove getPostRAMutations (#117527)

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Commits on Nov 22, 2024

• [RISCV] Support __builtin_cpu_is

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• [RISCV] Add mvendorid/marchid/mimpid to CPU definitions (#116202)

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