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[RISCV] Add SiFive X390 processor definition (#142517)
X390 is an in-order core designed for AI/ML workload, with VLEN=1024. https://www.sifive.com/cores/intelligence-x300-series Scheduling model will be added in a follow-up patch.
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‎clang/test/Driver/print-enabled-extensions/riscv-sifive-x390.c

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// RUN: %clang --target=riscv64 -mcpu=sifive-x390 -menable-experimental-extensions --print-enabled-extensions | FileCheck %s
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// REQUIRES: riscv-registered-target
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// CHECK: Name Version Description
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// CHECK-NEXT: i 2.1 'I' (Base Integer Instruction Set)
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// CHECK-NEXT: m 2.0 'M' (Integer Multiplication and Division)
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// CHECK-NEXT: a 2.1 'A' (Atomic Instructions)
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// CHECK-NEXT: f 2.2 'F' (Single-Precision Floating-Point)
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// CHECK-NEXT: d 2.2 'D' (Double-Precision Floating-Point)
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// CHECK-NEXT: c 2.0 'C' (Compressed Instructions)
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// CHECK-NEXT: b 1.0 'B' (the collection of the Zba, Zbb, Zbs extensions)
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// CHECK-NEXT: v 1.0 'V' (Vector Extension for Application Processors)
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// CHECK-NEXT: zic64b 1.0 'Zic64b' (Cache Block Size Is 64 Bytes)
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// CHECK-NEXT: zicbom 1.0 'Zicbom' (Cache-Block Management Instructions)
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// CHECK-NEXT: zicbop 1.0 'Zicbop' (Cache-Block Prefetch Instructions)
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// CHECK-NEXT: zicboz 1.0 'Zicboz' (Cache-Block Zero Instructions)
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// CHECK-NEXT: ziccamoa 1.0 'Ziccamoa' (Main Memory Supports All Atomics in A)
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// CHECK-NEXT: ziccif 1.0 'Ziccif' (Main Memory Supports Instruction Fetch with Atomicity Requirement)
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// CHECK-NEXT: ziccrse 1.0 'Ziccrse' (Main Memory Supports Forward Progress on LR/SC Sequences)
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// CHECK-NEXT: zicntr 2.0 'Zicntr' (Base Counters and Timers)
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// CHECK-NEXT: zicond 1.0 'Zicond' (Integer Conditional Operations)
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// CHECK-NEXT: zicsr 2.0 'Zicsr' (CSRs)
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// CHECK-NEXT: zifencei 2.0 'Zifencei' (fence.i)
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// CHECK-NEXT: zihintntl 1.0 'Zihintntl' (Non-Temporal Locality Hints)
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// CHECK-NEXT: zihintpause 2.0 'Zihintpause' (Pause Hint)
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// CHECK-NEXT: zihpm 2.0 'Zihpm' (Hardware Performance Counters)
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// CHECK-NEXT: zimop 1.0 'Zimop' (May-Be-Operations)
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// CHECK-NEXT: zmmul 1.0 'Zmmul' (Integer Multiplication)
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// CHECK-NEXT: za64rs 1.0 'Za64rs' (Reservation Set Size of at Most 64 Bytes)
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// CHECK-NEXT: zaamo 1.0 'Zaamo' (Atomic Memory Operations)
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// CHECK-NEXT: zalrsc 1.0 'Zalrsc' (Load-Reserved/Store-Conditional)
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// CHECK-NEXT: zawrs 1.0 'Zawrs' (Wait on Reservation Set)
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// CHECK-NEXT: zfa 1.0 'Zfa' (Additional Floating-Point)
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// CHECK-NEXT: zfbfmin 1.0 'Zfbfmin' (Scalar BF16 Converts)
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// CHECK-NEXT: zfh 1.0 'Zfh' (Half-Precision Floating-Point)
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// CHECK-NEXT: zfhmin 1.0 'Zfhmin' (Half-Precision Floating-Point Minimal)
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// CHECK-NEXT: zca 1.0 'Zca' (part of the C extension, excluding compressed floating point loads/stores)
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// CHECK-NEXT: zcb 1.0 'Zcb' (Compressed basic bit manipulation instructions)
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// CHECK-NEXT: zcd 1.0 'Zcd' (Compressed Double-Precision Floating-Point Instructions)
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// CHECK-NEXT: zcmop 1.0 'Zcmop' (Compressed May-Be-Operations)
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// CHECK-NEXT: zba 1.0 'Zba' (Address Generation Instructions)
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// CHECK-NEXT: zbb 1.0 'Zbb' (Basic Bit-Manipulation)
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// CHECK-NEXT: zbs 1.0 'Zbs' (Single-Bit Instructions)
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// CHECK-NEXT: zkr 1.0 'Zkr' (Entropy Source Extension)
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// CHECK-NEXT: zkt 1.0 'Zkt' (Data Independent Execution Latency)
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// CHECK-NEXT: zvbb 1.0 'Zvbb' (Vector basic bit-manipulation instructions)
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// CHECK-NEXT: zve32f 1.0 'Zve32f' (Vector Extensions for Embedded Processors with maximal 32 EEW and F extension)
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// CHECK-NEXT: zve32x 1.0 'Zve32x' (Vector Extensions for Embedded Processors with maximal 32 EEW)
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// CHECK-NEXT: zve64d 1.0 'Zve64d' (Vector Extensions for Embedded Processors with maximal 64 EEW, F and D extension)
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// CHECK-NEXT: zve64f 1.0 'Zve64f' (Vector Extensions for Embedded Processors with maximal 64 EEW and F extension)
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// CHECK-NEXT: zve64x 1.0 'Zve64x' (Vector Extensions for Embedded Processors with maximal 64 EEW)
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// CHECK-NEXT: zvfbfmin 1.0 'Zvfbfmin' (Vector BF16 Converts)
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// CHECK-NEXT: zvfbfwma 1.0 'Zvfbfwma' (Vector BF16 widening mul-add)
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// CHECK-NEXT: zvfh 1.0 'Zvfh' (Vector Half-Precision Floating-Point)
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// CHECK-NEXT: zvfhmin 1.0 'Zvfhmin' (Vector Half-Precision Floating-Point Minimal)
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// CHECK-NEXT: zvkb 1.0 'Zvkb' (Vector Bit-manipulation used in Cryptography)
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// CHECK-NEXT: zvkt 1.0 'Zvkt' (Vector Data-Independent Execution Latency)
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// CHECK-NEXT: zvl1024b 1.0 'Zvl1024b' (Minimum Vector Length 1024)
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// CHECK-NEXT: zvl128b 1.0 'Zvl128b' (Minimum Vector Length 128)
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// CHECK-NEXT: zvl256b 1.0 'Zvl256b' (Minimum Vector Length 256)
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// CHECK-NEXT: zvl32b 1.0 'Zvl32b' (Minimum Vector Length 32)
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// CHECK-NEXT: zvl512b 1.0 'Zvl512b' (Minimum Vector Length 512)
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// CHECK-NEXT: zvl64b 1.0 'Zvl64b' (Minimum Vector Length 64)
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// CHECK-NEXT: xsifivecdiscarddlone 1.0 'XSiFivecdiscarddlone' (SiFive sf.cdiscard.d.l1 Instruction)
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// CHECK-NEXT: xsifivecflushdlone 1.0 'XSiFivecflushdlone' (SiFive sf.cflush.d.l1 Instruction)
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// CHECK-EMPTY:
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// CHECK-NEXT: Experimental extensions
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// CHECK-NEXT: zicfilp 1.0 'Zicfilp' (Landing pad)
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// CHECK-NEXT: zicfiss 1.0 'Zicfiss' (Shadow stack)
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// CHECK-EMPTY:
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// CHECK-NEXT: ISA String: rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_b1p0_v1p0_zic64b1p0_zicbom1p0_zicbop1p0_zicboz1p0_ziccamoa1p0_ziccif1p0_ziccrse1p0_zicfilp1p0_zicfiss1p0_zicntr2p0_zicond1p0_zicsr2p0_zifencei2p0_zihintntl1p0_zihintpause2p0_zihpm2p0_zimop1p0_zmmul1p0_za64rs1p0_zaamo1p0_zalrsc1p0_zawrs1p0_zfa1p0_zfbfmin1p0_zfh1p0_zfhmin1p0_zca1p0_zcb1p0_zcd1p0_zcmop1p0_zba1p0_zbb1p0_zbs1p0_zkr1p0_zkt1p0_zvbb1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfbfmin1p0_zvfbfwma1p0_zvfh1p0_zvfhmin1p0_zvkb1p0_zvkt1p0_zvl1024b1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl512b1p0_zvl64b1p0_xsifivecdiscarddlone1p0_xsifivecflushdlone1p0

‎clang/test/Driver/riscv-cpus.c

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// MCPU-SIFIVE-X280-SAME: "-target-feature" "+zvl512b" "-target-feature" "+zvl64b"
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// MCPU-SIFIVE-X280-SAME: "-target-abi" "lp64d"
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// RUN: %clang -target riscv64 -### -c %s 2>&1 -menable-experimental-extensions -mcpu=sifive-x390 | FileCheck -check-prefix=MCPU-SIFIVE-X390 %s
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// MCPU-SIFIVE-X390: "-target-cpu" "sifive-x390"
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// COM: The list of extensions are tested in `test/Driver/print-enabled-extensions/riscv-sifive-x390.c`
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// MCPU-SIFIVE-X390-SAME: "-target-abi" "lp64d"
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// RUN: %clang -target riscv64 -### -c %s 2>&1 -mcpu=sifive-p450 | FileCheck -check-prefix=MCPU-SIFIVE-P450 %s
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// MCPU-SIFIVE-P450: "-nostdsysteminc" "-target-cpu" "sifive-p450"
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// MCPU-SIFIVE-P450-SAME: "-target-feature" "+m"

‎clang/test/Misc/target-invalid-cpu-note/riscv.c

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// RISCV64-SAME: {{^}}, sifive-u54
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// RISCV64-SAME: {{^}}, sifive-u74
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// RISCV64-SAME: {{^}}, sifive-x280
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// RISCV64-SAME: {{^}}, sifive-x390
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// RISCV64-SAME: {{^}}, spacemit-x60
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// RISCV64-SAME: {{^}}, syntacore-scr3-rv64
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// RISCV64-SAME: {{^}}, syntacore-scr4-rv64
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// TUNE-RISCV64-SAME: {{^}}, sifive-u54
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// TUNE-RISCV64-SAME: {{^}}, sifive-u74
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// TUNE-RISCV64-SAME: {{^}}, sifive-x280
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// TUNE-RISCV64-SAME: {{^}}, sifive-x390
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// TUNE-RISCV64-SAME: {{^}}, spacemit-x60
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// TUNE-RISCV64-SAME: {{^}}, syntacore-scr3-rv64
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// TUNE-RISCV64-SAME: {{^}}, syntacore-scr4-rv64

‎llvm/docs/ReleaseNotes.md

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Extensions.
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* `-mcpu=andes-a25` and `-mcpu=andes-ax25` were added.
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* The `Shlcofideleg` extension was added.
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* `-mcpu=sifive-x390` was added.
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Changes to the WebAssembly Backend
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----------------------------------

‎llvm/lib/Target/RISCV/RISCVProcessors.td

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@@ -271,10 +271,10 @@ def SIFIVE_U74 : RISCVProcessorModel<"sifive-u74",
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FeatureStdExtC],
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SiFive7TuneFeatures>;
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defvar SiFiveX280TuneFeatures = !listconcat(SiFive7TuneFeatures,
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[TuneDLenFactor2,
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TuneOptimizedZeroStrideLoad,
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TuneOptimizedNF2SegmentLoadStore]);
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defvar SiFiveIntelligenceTuneFeatures = !listconcat(SiFive7TuneFeatures,
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[TuneDLenFactor2,
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TuneOptimizedZeroStrideLoad,
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TuneOptimizedNF2SegmentLoadStore]);
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def SIFIVE_X280 : RISCVProcessorModel<"sifive-x280", SiFive7Model,
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[Feature64Bit,
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FeatureStdExtI,
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FeatureStdExtZvfh,
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FeatureStdExtZba,
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FeatureStdExtZbb],
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SiFiveX280TuneFeatures>;
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SiFiveIntelligenceTuneFeatures>;
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def SIFIVE_X390 : RISCVProcessorModel<"sifive-x390", NoSchedModel,
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[Feature64Bit,
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FeatureStdExtI,
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FeatureStdExtM,
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FeatureStdExtA,
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FeatureStdExtF,
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FeatureStdExtD,
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FeatureStdExtC,
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FeatureStdExtB,
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FeatureStdExtV,
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FeatureStdExtZic64b,
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FeatureStdExtZicbom,
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FeatureStdExtZicbop,
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FeatureStdExtZicboz,
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FeatureStdExtZiccamoa,
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FeatureStdExtZiccif,
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FeatureStdExtZiccrse,
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FeatureStdExtZicfilp,
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FeatureStdExtZicfiss,
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FeatureStdExtZicntr,
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FeatureStdExtZicond,
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FeatureStdExtZifencei,
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FeatureStdExtZihintntl,
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FeatureStdExtZihintpause,
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FeatureStdExtZihpm,
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FeatureStdExtZimop,
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FeatureStdExtZa64rs,
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FeatureStdExtZawrs,
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FeatureStdExtZfa,
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FeatureStdExtZfh,
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FeatureStdExtZcb,
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FeatureStdExtZcmop,
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FeatureStdExtZkr,
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FeatureStdExtZkt,
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FeatureStdExtZvbb,
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FeatureStdExtZvfbfmin,
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FeatureStdExtZvfbfwma,
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FeatureStdExtZvfh,
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FeatureStdExtZvkt,
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FeatureStdExtZvl1024b,
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FeatureVendorXSiFivecdiscarddlone,
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FeatureVendorXSiFivecflushdlone],
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SiFiveIntelligenceTuneFeatures>;
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defvar SiFiveP400TuneFeatures = [TuneNoDefaultUnroll,
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TuneConditionalCompressedMoveFusion,

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