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[AArch64] Remove copy in SVE/SME predicate spill and fill (#81716)
7dc20ab introduced an extra COPY when spilling and filling a PNR register, which can't be elided as the input (PNR predicate) and output (PPR predicate) register classes differ. The patch adds a new register class that covers both PPR and PNR so that STR_PXI and LDR_PXI can take either of them, removing the need for the copy.
1 parent c891704 commit fb8dbd1

12 files changed

+115
-90
lines changed

‎llvm/lib/Target/AArch64/AArch64InstrInfo.cpp

Lines changed: 12 additions & 25 deletions
Original file line numberDiff line numberDiff line change
@@ -4807,29 +4807,20 @@ void AArch64InstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
48074807
if (AArch64::FPR8RegClass.hasSubClassEq(RC))
48084808
Opc = AArch64::STRBui;
48094809
break;
4810-
case 2:
4810+
case 2: {
4811+
bool IsPNR = AArch64::PNRRegClass.hasSubClassEq(RC);
48114812
if (AArch64::FPR16RegClass.hasSubClassEq(RC))
48124813
Opc = AArch64::STRHui;
4813-
else if (AArch64::PPRRegClass.hasSubClassEq(RC)) {
4814+
else if (IsPNR || AArch64::PPRRegClass.hasSubClassEq(RC)) {
48144815
assert(Subtarget.hasSVEorSME() &&
48154816
"Unexpected register store without SVE store instructions");
4816-
Opc = AArch64::STR_PXI;
4817-
StackID = TargetStackID::ScalableVector;
4818-
} else if (AArch64::PNRRegClass.hasSubClassEq(RC)) {
4819-
assert((Subtarget.hasSVE2p1() || Subtarget.hasSME2()) &&
4817+
assert((!IsPNR || Subtarget.hasSVE2p1() || Subtarget.hasSME2()) &&
48204818
"Unexpected register store without SVE2p1 or SME2");
4821-
if (SrcReg.isVirtual()) {
4822-
auto NewSrcReg =
4823-
MF.getRegInfo().createVirtualRegister(&AArch64::PPRRegClass);
4824-
BuildMI(MBB, MBBI, DebugLoc(), get(TargetOpcode::COPY), NewSrcReg)
4825-
.addReg(SrcReg);
4826-
SrcReg = NewSrcReg;
4827-
} else
4828-
SrcReg = (SrcReg - AArch64::PN0) + AArch64::P0;
48294819
Opc = AArch64::STR_PXI;
48304820
StackID = TargetStackID::ScalableVector;
48314821
}
48324822
break;
4823+
}
48334824
case 4:
48344825
if (AArch64::GPR32allRegClass.hasSubClassEq(RC)) {
48354826
Opc = AArch64::STRWui;
@@ -4990,26 +4981,22 @@ void AArch64InstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
49904981
if (AArch64::FPR8RegClass.hasSubClassEq(RC))
49914982
Opc = AArch64::LDRBui;
49924983
break;
4993-
case 2:
4984+
case 2: {
4985+
bool IsPNR = AArch64::PNRRegClass.hasSubClassEq(RC);
49944986
if (AArch64::FPR16RegClass.hasSubClassEq(RC))
49954987
Opc = AArch64::LDRHui;
4996-
else if (AArch64::PPRRegClass.hasSubClassEq(RC)) {
4988+
else if (IsPNR || AArch64::PPRRegClass.hasSubClassEq(RC)) {
49974989
assert(Subtarget.hasSVEorSME() &&
49984990
"Unexpected register load without SVE load instructions");
4999-
Opc = AArch64::LDR_PXI;
5000-
StackID = TargetStackID::ScalableVector;
5001-
} else if (AArch64::PNRRegClass.hasSubClassEq(RC)) {
5002-
assert((Subtarget.hasSVE2p1() || Subtarget.hasSME2()) &&
4991+
assert((!IsPNR || Subtarget.hasSVE2p1() || Subtarget.hasSME2()) &&
50034992
"Unexpected register load without SVE2p1 or SME2");
5004-
PNRReg = DestReg;
5005-
if (DestReg.isVirtual())
5006-
DestReg = MF.getRegInfo().createVirtualRegister(&AArch64::PPRRegClass);
5007-
else
5008-
DestReg = (DestReg - AArch64::PN0) + AArch64::P0;
4993+
if (IsPNR)
4994+
PNRReg = DestReg;
50094995
Opc = AArch64::LDR_PXI;
50104996
StackID = TargetStackID::ScalableVector;
50114997
}
50124998
break;
4999+
}
50135000
case 4:
50145001
if (AArch64::GPR32allRegClass.hasSubClassEq(RC)) {
50155002
Opc = AArch64::LDRWui;

‎llvm/lib/Target/AArch64/AArch64RegisterInfo.td

Lines changed: 23 additions & 11 deletions
Original file line numberDiff line numberDiff line change
@@ -953,17 +953,6 @@ class PNRAsmOperand<string name, string RegClass, int Width>: AsmOperandClass {
953953
let ParserMethod = "tryParseSVEPredicateVector<RegKind::SVEPredicateAsCounter>";
954954
}
955955

956-
let RenderMethod = "addPNRasPPRRegOperands" in {
957-
def PNRasPPROpAny : PNRAsmOperand<"PNRasPPRPredicateAny", "PNR", 0>;
958-
def PNRasPPROp8 : PNRAsmOperand<"PNRasPPRPredicateB", "PNR", 8>;
959-
}
960-
961-
class PNRasPPRRegOp<string Suffix, AsmOperandClass C, ElementSizeEnum Size,
962-
RegisterClass RC> : SVERegOp<Suffix, C, Size, RC> {}
963-
964-
def PNRasPPRAny : PNRasPPRRegOp<"", PNRasPPROpAny, ElementSizeNone, PPR>;
965-
def PNRasPPR8 : PNRasPPRRegOp<"b", PNRasPPROp8, ElementSizeB, PPR>;
966-
967956
def PNRAsmOpAny: PNRAsmOperand<"PNPredicateAny", "PNR", 0>;
968957
def PNRAsmOp8 : PNRAsmOperand<"PNPredicateB", "PNR", 8>;
969958
def PNRAsmOp16 : PNRAsmOperand<"PNPredicateH", "PNR", 16>;
@@ -1004,6 +993,29 @@ let Namespace = "AArch64" in {
1004993
def psub1 : SubRegIndex<16, -1>;
1005994
}
1006995

996+
class PPRorPNRClass : RegisterClass<
997+
"AArch64",
998+
[ nxv16i1, nxv8i1, nxv4i1, nxv2i1, nxv1i1, aarch64svcount ], 16,
999+
(add PPR, PNR)> {
1000+
let Size = 16;
1001+
}
1002+
1003+
class PPRorPNRAsmOperand<string name, string RegClass, int Width>: AsmOperandClass {
1004+
let Name = "SVE" # name # "Reg";
1005+
let PredicateMethod = "isSVEPredicateOrPredicateAsCounterRegOfWidth<"
1006+
# Width # ", " # "AArch64::"
1007+
# RegClass # "RegClassID>";
1008+
let DiagnosticType = "InvalidSVE" # name # "Reg";
1009+
let RenderMethod = "addPPRorPNRRegOperands";
1010+
let ParserMethod = "tryParseSVEPredicateOrPredicateAsCounterVector";
1011+
}
1012+
1013+
def PPRorPNR : PPRorPNRClass;
1014+
def PPRorPNRAsmOp8 : PPRorPNRAsmOperand<"PPRorPNRB", "PPRorPNR", 8>;
1015+
def PPRorPNRAsmOpAny : PPRorPNRAsmOperand<"PPRorPNRAny", "PPRorPNR", 0>;
1016+
def PPRorPNRAny : PPRRegOp<"", PPRorPNRAsmOpAny, ElementSizeNone, PPRorPNR>;
1017+
def PPRorPNR8 : PPRRegOp<"b", PPRorPNRAsmOp8, ElementSizeB, PPRorPNR>;
1018+
10071019
// Pairs of SVE predicate vector registers.
10081020
def PSeqPairs : RegisterTuples<[psub0, psub1], [(rotl PPR, 0), (rotl PPR, 1)]>;
10091021

‎llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td

Lines changed: 2 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -4034,20 +4034,10 @@ let Predicates = [HasSVEorSME] in {
40344034

40354035
// Aliases for existing SVE instructions for which predicate-as-counter are
40364036
// accepted as an operand to the instruction
4037-
def : InstAlias<"ldr $Pt, [$Rn, $imm9, mul vl]",
4038-
(LDR_PXI PNRasPPRAny:$Pt, GPR64sp:$Rn, simm9:$imm9), 0>;
4039-
def : InstAlias<"ldr $Pt, [$Rn]",
4040-
(LDR_PXI PNRasPPRAny:$Pt, GPR64sp:$Rn, 0), 0>;
4041-
4042-
def : InstAlias<"str $Pt, [$Rn, $imm9, mul vl]",
4043-
(STR_PXI PNRasPPRAny:$Pt, GPR64sp:$Rn, simm9:$imm9), 0>;
4044-
def : InstAlias<"str $Pt, [$Rn]",
4045-
(STR_PXI PNRasPPRAny:$Pt, GPR64sp:$Rn, 0), 0>;
4046-
40474037
def : InstAlias<"mov $Pd, $Pn",
4048-
(ORR_PPzPP PNRasPPR8:$Pd, PNRasPPR8:$Pn, PNRasPPR8:$Pn, PNRasPPR8:$Pn), 0>;
4038+
(ORR_PPzPP PPRorPNR8:$Pd, PPRorPNR8:$Pn, PPRorPNR8:$Pn, PPRorPNR8:$Pn), 0>;
40494039

4050-
def : InstAlias<"pfalse\t$Pd", (PFALSE PNRasPPR8:$Pd), 0>;
4040+
def : InstAlias<"pfalse\t$Pd", (PFALSE PPRorPNR8:$Pd), 0>;
40514041

40524042
}
40534043

‎llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp

Lines changed: 40 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -276,6 +276,8 @@ class AArch64AsmParser : public MCTargetAsmParser {
276276
ParseStatus tryParseSVEDataVector(OperandVector &Operands);
277277
template <RegKind RK>
278278
ParseStatus tryParseSVEPredicateVector(OperandVector &Operands);
279+
ParseStatus
280+
tryParseSVEPredicateOrPredicateAsCounterVector(OperandVector &Operands);
279281
template <RegKind VectorKind>
280282
ParseStatus tryParseVectorList(OperandVector &Operands,
281283
bool ExpectMatch = false);
@@ -1241,6 +1243,7 @@ class AArch64Operand : public MCParsedAsmOperand {
12411243
case AArch64::PPR_p8to15RegClassID:
12421244
case AArch64::PNRRegClassID:
12431245
case AArch64::PNR_p8to15RegClassID:
1246+
case AArch64::PPRorPNRRegClassID:
12441247
RK = RegKind::SVEPredicateAsCounter;
12451248
break;
12461249
default:
@@ -1264,6 +1267,7 @@ class AArch64Operand : public MCParsedAsmOperand {
12641267
case AArch64::PPR_p8to15RegClassID:
12651268
case AArch64::PNRRegClassID:
12661269
case AArch64::PNR_p8to15RegClassID:
1270+
case AArch64::PPRorPNRRegClassID:
12671271
RK = RegKind::SVEPredicateVector;
12681272
break;
12691273
default:
@@ -1290,6 +1294,20 @@ class AArch64Operand : public MCParsedAsmOperand {
12901294
return DiagnosticPredicateTy::NearMatch;
12911295
}
12921296

1297+
template <int ElementWidth, unsigned Class>
1298+
DiagnosticPredicate isSVEPredicateOrPredicateAsCounterRegOfWidth() const {
1299+
if (Kind != k_Register || (Reg.Kind != RegKind::SVEPredicateAsCounter &&
1300+
Reg.Kind != RegKind::SVEPredicateVector))
1301+
return DiagnosticPredicateTy::NoMatch;
1302+
1303+
if ((isSVEPredicateAsCounterReg<Class>() ||
1304+
isSVEPredicateVectorRegOfWidth<ElementWidth, Class>()) &&
1305+
Reg.ElementWidth == ElementWidth)
1306+
return DiagnosticPredicateTy::Match;
1307+
1308+
return DiagnosticPredicateTy::NearMatch;
1309+
}
1310+
12931311
template <int ElementWidth, unsigned Class>
12941312
DiagnosticPredicate isSVEPredicateAsCounterRegOfWidth() const {
12951313
if (Kind != k_Register || Reg.Kind != RegKind::SVEPredicateAsCounter)
@@ -1770,6 +1788,15 @@ class AArch64Operand : public MCParsedAsmOperand {
17701788
Inst.addOperand(MCOperand::createReg(AArch64::Z0 + getReg() - Base));
17711789
}
17721790

1791+
void addPPRorPNRRegOperands(MCInst &Inst, unsigned N) const {
1792+
assert(N == 1 && "Invalid number of operands!");
1793+
unsigned Reg = getReg();
1794+
// Normalise to PPR
1795+
if (Reg >= AArch64::PN0 && Reg <= AArch64::PN15)
1796+
Reg = Reg - AArch64::PN0 + AArch64::P0;
1797+
Inst.addOperand(MCOperand::createReg(Reg));
1798+
}
1799+
17731800
void addPNRasPPRRegOperands(MCInst &Inst, unsigned N) const {
17741801
assert(N == 1 && "Invalid number of operands!");
17751802
Inst.addOperand(
@@ -4167,6 +4194,15 @@ ParseStatus AArch64AsmParser::tryParseVectorRegister(MCRegister &Reg,
41674194
return ParseStatus::NoMatch;
41684195
}
41694196

4197+
ParseStatus AArch64AsmParser::tryParseSVEPredicateOrPredicateAsCounterVector(
4198+
OperandVector &Operands) {
4199+
ParseStatus Status =
4200+
tryParseSVEPredicateVector<RegKind::SVEPredicateAsCounter>(Operands);
4201+
if (!Status.isSuccess())
4202+
Status = tryParseSVEPredicateVector<RegKind::SVEPredicateVector>(Operands);
4203+
return Status;
4204+
}
4205+
41704206
/// tryParseSVEPredicateVector - Parse a SVE predicate register operand.
41714207
template <RegKind RK>
41724208
ParseStatus
@@ -6019,6 +6055,8 @@ bool AArch64AsmParser::showMatchError(SMLoc Loc, unsigned ErrCode,
60196055
return Error(Loc, "Invalid restricted vector register, expected z0.d..z15.d");
60206056
case Match_InvalidSVEPattern:
60216057
return Error(Loc, "invalid predicate pattern");
6058+
case Match_InvalidSVEPPRorPNRAnyReg:
6059+
case Match_InvalidSVEPPRorPNRBReg:
60226060
case Match_InvalidSVEPredicateAnyReg:
60236061
case Match_InvalidSVEPredicateBReg:
60246062
case Match_InvalidSVEPredicateHReg:
@@ -6131,9 +6169,6 @@ bool AArch64AsmParser::showMatchError(SMLoc Loc, unsigned ErrCode,
61316169
case Match_AddSubLSLImm3ShiftLarge:
61326170
return Error(Loc,
61336171
"expected 'lsl' with optional integer in range [0, 7]");
6134-
case Match_InvalidSVEPNRasPPRPredicateBReg:
6135-
return Error(Loc,
6136-
"Expected predicate-as-counter register name with .B suffix");
61376172
default:
61386173
llvm_unreachable("unexpected error code!");
61396174
}
@@ -6653,6 +6688,8 @@ bool AArch64AsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
66536688
case Match_InvalidZPR_4b16:
66546689
case Match_InvalidZPR_4b32:
66556690
case Match_InvalidZPR_4b64:
6691+
case Match_InvalidSVEPPRorPNRAnyReg:
6692+
case Match_InvalidSVEPPRorPNRBReg:
66566693
case Match_InvalidSVEPredicateAnyReg:
66576694
case Match_InvalidSVEPattern:
66586695
case Match_InvalidSVEVecLenSpecifier:
@@ -6714,7 +6751,6 @@ bool AArch64AsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
67146751
case Match_InvalidSVEVectorListStrided4x16:
67156752
case Match_InvalidSVEVectorListStrided4x32:
67166753
case Match_InvalidSVEVectorListStrided4x64:
6717-
case Match_InvalidSVEPNRasPPRPredicateBReg:
67186754
case Match_MSR:
67196755
case Match_MRS: {
67206756
if (ErrorInfo >= Operands.size())

‎llvm/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp

Lines changed: 15 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -143,6 +143,9 @@ DecodeMatrixTileListRegisterClass(MCInst &Inst, unsigned RegMask,
143143
static DecodeStatus DecodePPRRegisterClass(MCInst &Inst, unsigned RegNo,
144144
uint64_t Address,
145145
const MCDisassembler *Decoder);
146+
static DecodeStatus DecodePPRorPNRRegisterClass(MCInst &Inst, unsigned RegNo,
147+
uint64_t Addr,
148+
const MCDisassembler *Decoder);
146149
static DecodeStatus DecodePNRRegisterClass(MCInst &Inst, unsigned RegNo,
147150
uint64_t Address,
148151
const MCDisassembler *Decoder);
@@ -741,6 +744,18 @@ static DecodeStatus DecodeMatrixTile(MCInst &Inst, unsigned RegNo,
741744
return Success;
742745
}
743746

747+
static DecodeStatus DecodePPRorPNRRegisterClass(MCInst &Inst, unsigned RegNo,
748+
uint64_t Addr,
749+
const MCDisassembler *Decoder) {
750+
if (RegNo > 15)
751+
return Fail;
752+
753+
unsigned Register =
754+
AArch64MCRegisterClasses[AArch64::PPRorPNRRegClassID].getRegister(RegNo);
755+
Inst.addOperand(MCOperand::createReg(Register));
756+
return Success;
757+
}
758+
744759
static DecodeStatus DecodePPRRegisterClass(MCInst &Inst, unsigned RegNo,
745760
uint64_t Addr,
746761
const MCDisassembler *Decoder) {

‎llvm/lib/Target/AArch64/SMEInstrFormats.td

Lines changed: 1 addition & 14 deletions
Original file line numberDiff line numberDiff line change
@@ -1301,7 +1301,7 @@ multiclass sve2_clamp<string asm, bit U, SDPatternOperator op> {
13011301
}
13021302

13031303
class sve2_int_perm_sel_p<string asm, PPRRegOp ppr_ty, Operand imm_ty>
1304-
: I<(outs PPRAny:$Pd), (ins PPRAny:$Pn, ppr_ty:$Pm,
1304+
: I<(outs PPRorPNRAny:$Pd), (ins PPRorPNRAny:$Pn, ppr_ty:$Pm,
13051305
MatrixIndexGPR32Op12_15:$Rv, imm_ty:$imm),
13061306
asm, "\t$Pd, $Pn, $Pm[$Rv, $imm]", "", []>,
13071307
Sched<[]> {
@@ -1345,19 +1345,6 @@ multiclass sve2_int_perm_sel_p<string asm, SDPatternOperator op> {
13451345
let Inst{20-18} = 0b000;
13461346
}
13471347

1348-
def : InstAlias<asm # "\t$Pd, $Pn, $Pm[$Rv, $imm]",
1349-
(!cast<Instruction>(NAME # _B) PNRasPPRAny:$Pd,
1350-
PNRasPPRAny:$Pn, PPR8:$Pm, MatrixIndexGPR32Op12_15:$Rv, sme_elm_idx0_15:$imm), 0>;
1351-
def : InstAlias<asm # "\t$Pd, $Pn, $Pm[$Rv, $imm]",
1352-
(!cast<Instruction>(NAME # _H) PNRasPPRAny:$Pd,
1353-
PNRasPPRAny:$Pn, PPR16:$Pm, MatrixIndexGPR32Op12_15:$Rv, sme_elm_idx0_7:$imm), 0>;
1354-
def : InstAlias<asm # "\t$Pd, $Pn, $Pm[$Rv, $imm]",
1355-
(!cast<Instruction>(NAME # _S) PNRasPPRAny:$Pd,
1356-
PNRasPPRAny:$Pn, PPR32:$Pm, MatrixIndexGPR32Op12_15:$Rv, sme_elm_idx0_3:$imm), 0>;
1357-
def : InstAlias<asm # "\t$Pd, $Pn, $Pm[$Rv, $imm]",
1358-
(!cast<Instruction>(NAME # _D) PNRasPPRAny:$Pd,
1359-
PNRasPPRAny:$Pn, PPR64:$Pm, MatrixIndexGPR32Op12_15:$Rv, sme_elm_idx0_1:$imm), 0>;
1360-
13611348
def : Pat<(nxv16i1 (op (nxv16i1 PPRAny:$Pn), (nxv16i1 PPR8:$Pm),
13621349
MatrixIndexGPR32Op12_15:$idx)),
13631350
(!cast<Instruction>(NAME # _B) $Pn, $Pm, $idx, 0)>;

‎llvm/lib/Target/AArch64/SVEInstrFormats.td

Lines changed: 6 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -729,7 +729,7 @@ let hasNoSchedulingInfo = 1 in {
729729
//===----------------------------------------------------------------------===//
730730

731731
class sve_int_pfalse<bits<6> opc, string asm>
732-
: I<(outs PPR8:$Pd), (ins),
732+
: I<(outs PPRorPNR8:$Pd), (ins),
733733
asm, "\t$Pd",
734734
"",
735735
[]>, Sched<[]> {
@@ -1837,7 +1837,7 @@ multiclass sve_int_sel_vvv<string asm, SDPatternOperator op> {
18371837
//===----------------------------------------------------------------------===//
18381838

18391839
class sve_int_pred_log<bits<4> opc, string asm>
1840-
: I<(outs PPR8:$Pd), (ins PPRAny:$Pg, PPR8:$Pn, PPR8:$Pm),
1840+
: I<(outs PPRorPNR8:$Pd), (ins PPRorPNRAny:$Pg, PPRorPNR8:$Pn, PPRorPNR8:$Pm),
18411841
asm, "\t$Pd, $Pg/z, $Pn, $Pm",
18421842
"",
18431843
[]>, Sched<[]> {
@@ -6664,7 +6664,7 @@ multiclass sve_mem_z_spill<string asm> {
66646664
}
66656665

66666666
class sve_mem_p_spill<string asm>
6667-
: I<(outs), (ins PPRAny:$Pt, GPR64sp:$Rn, simm9:$imm9),
6667+
: I<(outs), (ins PPRorPNRAny:$Pt, GPR64sp:$Rn, simm9:$imm9),
66686668
asm, "\t$Pt, [$Rn, $imm9, mul vl]",
66696669
"",
66706670
[]>, Sched<[]> {
@@ -6687,7 +6687,7 @@ multiclass sve_mem_p_spill<string asm> {
66876687
def NAME : sve_mem_p_spill<asm>;
66886688

66896689
def : InstAlias<asm # "\t$Pt, [$Rn]",
6690-
(!cast<Instruction>(NAME) PPRAny:$Pt, GPR64sp:$Rn, 0), 1>;
6690+
(!cast<Instruction>(NAME) PPRorPNRAny:$Pt, GPR64sp:$Rn, 0), 1>;
66916691
}
66926692

66936693
//===----------------------------------------------------------------------===//
@@ -7833,7 +7833,7 @@ multiclass sve_mem_z_fill<string asm> {
78337833
}
78347834

78357835
class sve_mem_p_fill<string asm>
7836-
: I<(outs PPRAny:$Pt), (ins GPR64sp:$Rn, simm9:$imm9),
7836+
: I<(outs PPRorPNRAny:$Pt), (ins GPR64sp:$Rn, simm9:$imm9),
78377837
asm, "\t$Pt, [$Rn, $imm9, mul vl]",
78387838
"",
78397839
[]>, Sched<[]> {
@@ -7856,7 +7856,7 @@ multiclass sve_mem_p_fill<string asm> {
78567856
def NAME : sve_mem_p_fill<asm>;
78577857

78587858
def : InstAlias<asm # "\t$Pt, [$Rn]",
7859-
(!cast<Instruction>(NAME) PPRAny:$Pt, GPR64sp:$Rn, 0), 1>;
7859+
(!cast<Instruction>(NAME) PPRorPNRAny:$Pt, GPR64sp:$Rn, 0), 1>;
78607860
}
78617861

78627862
class sve2_mem_gldnt_vs_base<bits<5> opc, dag iops, string asm,

‎llvm/test/CodeGen/AArch64/GlobalISel/regbank-inlineasm.mir

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -57,11 +57,11 @@ tracksRegLiveness: true
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body: |
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bb.1:
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; CHECK-LABEL: name: inlineasm_virt_reg_output
60-
; CHECK: INLINEASM &"mov ${0:w}, 7", 0 /* attdialect */, 1310730 /* regdef:PPR2_with_psub_in_PNR_3b_and_PPR2_with_psub1_in_PPR_p8to15 */, def %0
60+
; CHECK: INLINEASM &"mov ${0:w}, 7", 0 /* attdialect */, 1769482 /* regdef:GPR32common */, def %0
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; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr(s32) = COPY %0
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; CHECK-NEXT: $w0 = COPY [[COPY]](s32)
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; CHECK-NEXT: RET_ReallyLR implicit $w0
64-
INLINEASM &"mov ${0:w}, 7", 0 /* attdialect */, 1310730 /* regdef:GPR32common */, def %0:gpr32common
64+
INLINEASM &"mov ${0:w}, 7", 0 /* attdialect */, 1769482 /* regdef:GPR32common */, def %0:gpr32common
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%1:_(s32) = COPY %0
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$w0 = COPY %1(s32)
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RET_ReallyLR implicit $w0
@@ -75,12 +75,12 @@ tracksRegLiveness: true
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body: |
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bb.1:
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; CHECK-LABEL: name: inlineasm_virt_mixed_types
78-
; CHECK: INLINEASM &"mov $0, #0; mov $1, #0", 0 /* attdialect */, 1310730 /* regdef:PPR2_with_psub_in_PNR_3b_and_PPR2_with_psub1_in_PPR_p8to15 */, def %0, 2162698 /* regdef:WSeqPairsClass */, def %1
78+
; CHECK: INLINEASM &"mov $0, #0; mov $1, #0", 0 /* attdialect */, 1769482 /* regdef:GPR32common */, def %0, {{[0-9]+}} /* regdef:FPR64 */, def %1
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; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr(s32) = COPY %0
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; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr(s64) = COPY %1
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; CHECK-NEXT: $d0 = COPY [[COPY1]](s64)
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; CHECK-NEXT: RET_ReallyLR implicit $d0
83-
INLINEASM &"mov $0, #0; mov $1, #0", 0 /* attdialect */, 1310730 /* regdef:GPR32common */, def %0:gpr32common, 2162698 /* regdef:FPR64 */, def %1:fpr64
83+
INLINEASM &"mov $0, #0; mov $1, #0", 0 /* attdialect */, 1769482 /* regdef:GPR32common */, def %0:gpr32common, 2621450 /* regdef:FPR64 */, def %1:fpr64
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%3:_(s32) = COPY %0
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%4:_(s64) = COPY %1
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$d0 = COPY %4(s64)

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