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[X86][CodeGen] Add a dag pattern to fix #64323
After recent patch D30189, #64323's error message become a new one. When DAGCombiner was optimizing `(vextract (scalar_to_vector val, 0) -> val`, it didn't consider the possibility that the inserted value type has less bit than the dest type. This patch fixes that. Reviewed By: pengfei Differential Revision: https://reviews.llvm.org/D158355
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2 | ||
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; RUN: llc < %s -mtriple=x86_64 -mcpu=icelake-server | FileCheck %s | ||
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define <1 x i1> @f(<1 x float> %0) nounwind { | ||
; CHECK-LABEL: f: | ||
; CHECK: # %bb.0: | ||
; CHECK-NEXT: pushq %rax | ||
; CHECK-NEXT: vcmpeqss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k0 | ||
; CHECK-NEXT: kmovd %k0, %edi | ||
; CHECK-NEXT: callq g@PLT | ||
; CHECK-NEXT: popq %rcx | ||
; CHECK-NEXT: retq | ||
%A = fcmp oeq <1 x float> %0, <float 0x36A0000000000000> | ||
%B = call <1 x i1> @g(<1 x i1> %A) | ||
ret <1 x i1> %B | ||
} | ||
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declare <1 x i1> @g(<1 x i1> %0) nounwind |