Skip to content

Commit e276000

Browse files
AmrDeveloperAmrDeveloper
authored
[CIR] Implement logical not for VectorType (#160762)
This change implements logical not for VectorType
1 parent 8fb2e2a commit e276000

File tree

3 files changed

+88
-6
lines changed

3 files changed

+88
-6
lines changed

‎clang/lib/CIR/CodeGen/CIRGenExprScalar.cpp‎

Lines changed: 8 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -2085,9 +2085,13 @@ mlir::Value ScalarExprEmitter::VisitUnaryLNot(const UnaryOperator *e) {
20852085
if (e->getType()->isVectorType() &&
20862086
e->getType()->castAs<VectorType>()->getVectorKind() ==
20872087
VectorKind::Generic) {
2088-
assert(!cir::MissingFeatures::vectorType());
2089-
cgf.cgm.errorNYI(e->getSourceRange(), "vector logical not");
2090-
return {};
2088+
mlir::Value oper = Visit(e->getSubExpr());
2089+
mlir::Location loc = cgf.getLoc(e->getExprLoc());
2090+
auto operVecTy = mlir::cast<cir::VectorType>(oper.getType());
2091+
auto exprVecTy = mlir::cast<cir::VectorType>(cgf.convertType(e->getType()));
2092+
mlir::Value zeroVec = builder.getNullValue(operVecTy, loc);
2093+
return cir::VecCmpOp::create(builder, loc, exprVecTy, cir::CmpOpKind::eq,
2094+
oper, zeroVec);
20912095
}
20922096

20932097
// Compare operand to zero.
@@ -2361,4 +2365,4 @@ mlir::Value CIRGenFunction::emitScalarPrePostIncDec(const UnaryOperator *e,
23612365
bool isPre) {
23622366
return ScalarExprEmitter(*this, builder)
23632367
.emitScalarPrePostIncDec(e, lv, kind, isPre);
2364-
}
2368+
}

‎clang/test/CIR/CodeGen/vector-ext.cpp‎

Lines changed: 27 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1295,4 +1295,30 @@ void foo23() {
12951295
// OGCG: %[[NE_B_ZERO:.*]] = icmp ne <4 x i32> %[[TMP_B]], zeroinitializer
12961296
// OGCG: %[[VEC_OR:.*]] = and <4 x i1> %[[NE_A_ZERO]], %[[NE_B_ZERO]]
12971297
// OGCG: %[[RESULT:.*]] = sext <4 x i1> %[[VEC_OR]] to <4 x i32>
1298-
// OGCG: store <4 x i32> %[[RESULT]], ptr %[[C_ADDR]], align 16
1298+
// OGCG: store <4 x i32> %[[RESULT]], ptr %[[C_ADDR]], align 16
1299+
1300+
void logical_not() {
1301+
vi4 a;
1302+
vi4 b = !a;
1303+
}
1304+
1305+
// CIR: %[[A_ADDR:.*]] = cir.alloca !cir.vector<4 x !s32i>, !cir.ptr<!cir.vector<4 x !s32i>>, ["a"]
1306+
// CIR: %[[B_ADDR:.*]] = cir.alloca !cir.vector<4 x !s32i>, !cir.ptr<!cir.vector<4 x !s32i>>, ["b", init]
1307+
// CIR: %[[TMP_A:.*]] = cir.load{{.*}}) %[[A_ADDR]] : !cir.ptr<!cir.vector<4 x !s32i>>, !cir.vector<4 x !s32i>
1308+
// CIR: %[[CONST_V0:.*]] = cir.const #cir.zero : !cir.vector<4 x !s32i>
1309+
// CIR: %[[RESULT:.*]] = cir.vec.cmp(eq, %[[TMP_A]], %[[CONST_V0]]) : !cir.vector<4 x !s32i>, !cir.vector<4 x !s32i>
1310+
// CIR: cir.store{{.*}} %[[RESULT]], %[[B_ADDR]] : !cir.vector<4 x !s32i>, !cir.ptr<!cir.vector<4 x !s32i>>
1311+
1312+
// LLVM: %[[A_ADDR:.*]] = alloca <4 x i32>, i64 1, align 16
1313+
// LLVM: %[[B_ADDR:.*]] = alloca <4 x i32>, i64 1, align 16
1314+
// LLVM: %[[TMP_A:.*]] = load <4 x i32>, ptr %[[A_ADDR]], align 16
1315+
// LLVM: %[[RESULT:.*]] = icmp eq <4 x i32> %[[TMP_A]], zeroinitializer
1316+
// LLVM: %[[RESULT_VI4:.*]] = sext <4 x i1> %[[RESULT]] to <4 x i32>
1317+
// LLVM: store <4 x i32> %[[RESULT_VI4]], ptr %[[B_ADDR]], align 16
1318+
1319+
// OGCG: %[[A_ADDR:.*]] = alloca <4 x i32>, align 16
1320+
// OGCG: %[[B_ADDR:.*]] = alloca <4 x i32>, align 16
1321+
// OGCG: %[[TMP_A:.*]] = load <4 x i32>, ptr %[[A_ADDR]], align 16
1322+
// OGCG: %[[RESULT:.*]] = icmp eq <4 x i32> %[[TMP_A]], zeroinitializer
1323+
// OGCG: %[[RESULT_VI4:.*]] = sext <4 x i1> %[[RESULT]] to <4 x i32>
1324+
// OGCG: store <4 x i32> %[[RESULT_VI4]], ptr %[[B_ADDR]], align 16

‎clang/test/CIR/CodeGen/vector.cpp‎

Lines changed: 53 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1337,4 +1337,56 @@ void foo26() {
13371337
// OGCG: %[[NE_B_ZERO:.*]] = icmp ne <4 x i32> %[[TMP_B]], zeroinitializer
13381338
// OGCG: %[[VEC_OR:.*]] = and <4 x i1> %[[NE_A_ZERO]], %[[NE_B_ZERO]]
13391339
// OGCG: %[[RESULT:.*]] = sext <4 x i1> %[[VEC_OR]] to <4 x i32>
1340-
// OGCG: store <4 x i32> %[[RESULT]], ptr %[[C_ADDR]], align 16
1340+
// OGCG: store <4 x i32> %[[RESULT]], ptr %[[C_ADDR]], align 16
1341+
1342+
void logical_not() {
1343+
vi4 a;
1344+
vi4 b = !a;
1345+
}
1346+
1347+
// CIR: %[[A_ADDR:.*]] = cir.alloca !cir.vector<4 x !s32i>, !cir.ptr<!cir.vector<4 x !s32i>>, ["a"]
1348+
// CIR: %[[B_ADDR:.*]] = cir.alloca !cir.vector<4 x !s32i>, !cir.ptr<!cir.vector<4 x !s32i>>, ["b", init]
1349+
// CIR: %[[TMP_A:.*]] = cir.load{{.*}}) %[[A_ADDR]] : !cir.ptr<!cir.vector<4 x !s32i>>, !cir.vector<4 x !s32i>
1350+
// CIR: %[[CONST_V0:.*]] = cir.const #cir.zero : !cir.vector<4 x !s32i>
1351+
// CIR: %[[RESULT:.*]] = cir.vec.cmp(eq, %[[TMP_A]], %[[CONST_V0]]) : !cir.vector<4 x !s32i>, !cir.vector<4 x !s32i>
1352+
// CIR: cir.store{{.*}} %[[RESULT]], %[[B_ADDR]] : !cir.vector<4 x !s32i>, !cir.ptr<!cir.vector<4 x !s32i>>
1353+
1354+
// LLVM: %[[A_ADDR:.*]] = alloca <4 x i32>, i64 1, align 16
1355+
// LLVM: %[[B_ADDR:.*]] = alloca <4 x i32>, i64 1, align 16
1356+
// LLVM: %[[TMP_A:.*]] = load <4 x i32>, ptr %[[A_ADDR]], align 16
1357+
// LLVM: %[[RESULT:.*]] = icmp eq <4 x i32> %[[TMP_A]], zeroinitializer
1358+
// LLVM: %[[RESULT_VI4:.*]] = sext <4 x i1> %[[RESULT]] to <4 x i32>
1359+
// LLVM: store <4 x i32> %[[RESULT_VI4]], ptr %[[B_ADDR]], align 16
1360+
1361+
// OGCG: %[[A_ADDR:.*]] = alloca <4 x i32>, align 16
1362+
// OGCG: %[[B_ADDR:.*]] = alloca <4 x i32>, align 16
1363+
// OGCG: %[[TMP_A:.*]] = load <4 x i32>, ptr %[[A_ADDR]], align 16
1364+
// OGCG: %[[RESULT:.*]] = icmp eq <4 x i32> %[[TMP_A]], zeroinitializer
1365+
// OGCG: %[[RESULT_VI4:.*]] = sext <4 x i1> %[[RESULT]] to <4 x i32>
1366+
// OGCG: store <4 x i32> %[[RESULT_VI4]], ptr %[[B_ADDR]], align 16
1367+
1368+
void logical_not_float() {
1369+
vf4 a;
1370+
vi4 b = !a;
1371+
}
1372+
1373+
// CIR: %[[A_ADDR:.*]] = cir.alloca !cir.vector<4 x !cir.float>, !cir.ptr<!cir.vector<4 x !cir.float>>, ["a"]
1374+
// CIR: %[[B_ADDR:.*]] = cir.alloca !cir.vector<4 x !s32i>, !cir.ptr<!cir.vector<4 x !s32i>>, ["b", init]
1375+
// CIR: %[[TMP_A:.*]] = cir.load{{.*}} %[[A_ADDR]] : !cir.ptr<!cir.vector<4 x !cir.float>>, !cir.vector<4 x !cir.float>
1376+
// CIR: %[[CONST_V0:.*]] = cir.const #cir.zero : !cir.vector<4 x !cir.float>
1377+
// CIR: %[[RESULT:.*]] = cir.vec.cmp(eq, %[[TMP_A]], %[[CONST_V0]]) : !cir.vector<4 x !cir.float>, !cir.vector<4 x !s32i>
1378+
// CIR: cir.store{{.*}} %[[RESULT]], %[[B_ADDR]] : !cir.vector<4 x !s32i>, !cir.ptr<!cir.vector<4 x !s32i>>
1379+
1380+
// LLVM: %[[A_ADDR:.*]] = alloca <4 x float>, i64 1, align 16
1381+
// LLVM: %[[B_ADDR:.*]] = alloca <4 x i32>, i64 1, align 16
1382+
// LLVM: %[[TMP_A:.*]] = load <4 x float>, ptr %[[A_ADDR]], align 16
1383+
// LLVM: %[[RESULT:.*]] = fcmp oeq <4 x float> %[[TMP_A]], zeroinitializer
1384+
// LLVM: %[[RESULT_VI4:.*]] = sext <4 x i1> %[[RESULT]] to <4 x i32>
1385+
// LLVM: store <4 x i32> %[[RESULT_VI4]], ptr %[[B_ADDR]], align 16
1386+
1387+
// OGCG: %[[A_ADDR:.*]] = alloca <4 x float>, align 16
1388+
// OGCG: %[[B_ADDR:.*]] = alloca <4 x i32>, align 16
1389+
// OGCG: %[[TMP_A:.*]] = load <4 x float>, ptr %[[A_ADDR]], align 16
1390+
// OGCG: %[[RESULT:.*]] = fcmp oeq <4 x float> %[[TMP_A]], zeroinitializer
1391+
// OGCG: %[[RESULT_VI4:.*]] = sext <4 x i1> %[[RESULT]] to <4 x i32>
1392+
// OGCG: store <4 x i32> %[[RESULT_VI4]], ptr %[[B_ADDR]], align 16

0 commit comments

Comments
 (0)