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13 | 13 | //===----------------------------------------------------------------------===// |
14 | 14 |
|
15 | 15 | #include "X86RegisterInfo.h" |
| 16 | +#include "MCTargetDesc/X86BaseInfo.h" |
16 | 17 | #include "X86FrameLowering.h" |
17 | 18 | #include "X86MachineFunctionInfo.h" |
18 | 19 | #include "X86Subtarget.h" |
|
24 | 25 | #include "llvm/CodeGen/MachineFunction.h" |
25 | 26 | #include "llvm/CodeGen/MachineFunctionPass.h" |
26 | 27 | #include "llvm/CodeGen/MachineRegisterInfo.h" |
| 28 | +#include "llvm/CodeGen/RegisterScavenging.h" |
27 | 29 | #include "llvm/CodeGen/TargetFrameLowering.h" |
28 | 30 | #include "llvm/CodeGen/TargetInstrInfo.h" |
29 | 31 | #include "llvm/CodeGen/TileShapeInfo.h" |
@@ -900,7 +902,7 @@ X86RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II, |
900 | 902 | int FrameIndex = MI.getOperand(FIOperandNum).getIndex(); |
901 | 903 |
|
902 | 904 | // Determine base register and offset. |
903 | | - int FIOffset; |
| 905 | + int64_t FIOffset; |
904 | 906 | Register BasePtr; |
905 | 907 | if (MI.isReturn()) { |
906 | 908 | assert((!hasStackRealignment(MF) || |
@@ -951,11 +953,36 @@ X86RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II, |
951 | 953 | } |
952 | 954 |
|
953 | 955 | if (MI.getOperand(FIOperandNum+3).isImm()) { |
954 | | - // Offset is a 32-bit integer. |
955 | | - int Imm = (int)(MI.getOperand(FIOperandNum + 3).getImm()); |
956 | | - int Offset = FIOffset + Imm; |
957 | | - assert((!Is64Bit || isInt<32>((long long)FIOffset + Imm)) && |
958 | | - "Requesting 64-bit offset in 32-bit immediate!"); |
| 956 | + int64_t Imm = MI.getOperand(FIOperandNum + 3).getImm(); |
| 957 | + int64_t Offset = FIOffset + Imm; |
| 958 | + bool FitsIn32Bits = isInt<32>(Offset); |
| 959 | + // If the offset will not fit in a 32-bit displacement, |
| 960 | + // then for 64-bit targets, scavenge a register to hold it. |
| 961 | + // Otherwise, for 32-bit targets, this is a bug! |
| 962 | + if (Is64Bit && !FitsIn32Bits) { |
| 963 | + assert(RS && "RegisterScavenger was NULL"); |
| 964 | + const X86InstrInfo *TII = MF.getSubtarget<X86Subtarget>().getInstrInfo(); |
| 965 | + const DebugLoc &DL = MI.getDebugLoc(); |
| 966 | + |
| 967 | + RS->enterBasicBlockEnd(MBB); |
| 968 | + RS->backward(std::next(II)); |
| 969 | + |
| 970 | + Register ScratchReg = RS->scavengeRegisterBackwards( |
| 971 | + X86::GR64RegClass, II, /* RestoreAfter */ false, /* SPAdj */ 0, |
| 972 | + /* AllowSpill */ true); |
| 973 | + assert(ScratchReg != 0 && "scratch reg was 0"); |
| 974 | + RS->setRegUsed(ScratchReg); |
| 975 | + |
| 976 | + BuildMI(MBB, II, DL, TII->get(X86::MOV64ri), ScratchReg).addImm(Offset); |
| 977 | + |
| 978 | + MI.getOperand(FIOperandNum + 3).setImm(0); |
| 979 | + MI.getOperand(FIOperandNum + 2).setReg(ScratchReg); |
| 980 | + |
| 981 | + return false; |
| 982 | + } |
| 983 | + if (!Is64Bit) { |
| 984 | + assert(FitsIn32Bits && "Requesting 64-bit offset in 32-bit immediate!"); |
| 985 | + } |
959 | 986 | if (Offset != 0 || !tryOptimizeLEAtoMOV(II)) |
960 | 987 | MI.getOperand(FIOperandNum + 3).ChangeToImmediate(Offset); |
961 | 988 | } else { |
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