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[MIPS] LLVM data layout give i128 an alignment of 16 for mips64
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Fix parts of #102783.
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@yingopq
yingopq committed Nov 6, 2024
1 parent ae5ee97 commit d6065cc
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Showing 7 changed files with 90 additions and 17 deletions.
4 changes: 2 additions & 2 deletions clang/lib/Basic/Targets/Mips.h
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Expand Up @@ -28,9 +28,9 @@ class LLVM_LIBRARY_VISIBILITY MipsTargetInfo : public TargetInfo {
if (ABI == "o32")
Layout = "m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32-S64";
else if (ABI == "n32")
Layout = "m:e-p:32:32-i8:8:32-i16:16:32-i64:64-n32:64-S128";
Layout = "m:e-p:32:32-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128";
else if (ABI == "n64")
Layout = "m:e-i8:8:32-i16:16:32-i64:64-n32:64-S128";
Layout = "m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128";
else
llvm_unreachable("Invalid ABI");

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8 changes: 4 additions & 4 deletions clang/test/CodeGen/target-data.c
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Expand Up @@ -54,7 +54,7 @@
// RUN: FileCheck %s -check-prefix=MIPS-64EL
// RUN: %clang_cc1 -triple mipsisa64r6el-linux-gnuabi64 -o - -emit-llvm %s | \
// RUN: FileCheck %s -check-prefix=MIPS-64EL
// MIPS-64EL: target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-n32:64-S128"
// MIPS-64EL: target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"

// RUN: %clang_cc1 -triple mips64el-linux-gnu -o - -emit-llvm -target-abi n32 \
// RUN: %s | FileCheck %s -check-prefix=MIPS-64EL-N32
Expand All @@ -64,7 +64,7 @@
// RUN: %s | FileCheck %s -check-prefix=MIPS-64EL-N32
// RUN: %clang_cc1 -triple mipsisa64r6el-linux-gnuabin32 -o - -emit-llvm \
// RUN: %s | FileCheck %s -check-prefix=MIPS-64EL-N32
// MIPS-64EL-N32: target datalayout = "e-m:e-p:32:32-i8:8:32-i16:16:32-i64:64-n32:64-S128"
// MIPS-64EL-N32: target datalayout = "e-m:e-p:32:32-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"

// RUN: %clang_cc1 -triple mips64-linux-gnu -o - -emit-llvm %s | \
// RUN: FileCheck %s -check-prefix=MIPS-64EB
Expand All @@ -74,7 +74,7 @@
// RUN: FileCheck %s -check-prefix=MIPS-64EB
// RUN: %clang_cc1 -triple mipsisa64r6-linux-gnuabi64 -o - -emit-llvm %s | \
// RUN: FileCheck %s -check-prefix=MIPS-64EB
// MIPS-64EB: target datalayout = "E-m:e-i8:8:32-i16:16:32-i64:64-n32:64-S128"
// MIPS-64EB: target datalayout = "E-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"

// RUN: %clang_cc1 -triple mips64-linux-gnu -o - -emit-llvm %s -target-abi n32 \
// RUN: | FileCheck %s -check-prefix=MIPS-64EB-N32
Expand All @@ -84,7 +84,7 @@
// RUN: | FileCheck %s -check-prefix=MIPS-64EB-N32
// RUN: %clang_cc1 -triple mipsisa64r6-linux-gnuabin32 -o - -emit-llvm %s \
// RUN: | FileCheck %s -check-prefix=MIPS-64EB-N32
// MIPS-64EB-N32: target datalayout = "E-m:e-p:32:32-i8:8:32-i16:16:32-i64:64-n32:64-S128"
// MIPS-64EB-N32: target datalayout = "E-m:e-p:32:32-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"

// RUN: %clang_cc1 -triple powerpc64-lv2 -o - -emit-llvm %s | \
// RUN: FileCheck %s -check-prefix=PS3
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3 changes: 2 additions & 1 deletion llvm/lib/IR/AutoUpgrade.cpp
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Expand Up @@ -5566,7 +5566,8 @@ std::string llvm::UpgradeDataLayoutString(StringRef DL, StringRef TT) {
return Res;
}

if (T.isSPARC()) {
if (T.isSPARC() || (T.isMIPS64() && !DL.contains("m:m"))) {
// Mips64 with o32 ABI did not add "-i128:128".
// Add "-i128:128"
std::string I64 = "-i64:64";
std::string I128 = "-i128:128";
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2 changes: 1 addition & 1 deletion llvm/lib/Target/Mips/MipsTargetMachine.cpp
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Expand Up @@ -99,7 +99,7 @@ static std::string computeDataLayout(const Triple &TT, StringRef CPU,
// aligned. On N64 64 bit registers are also available and the stack is
// 128 bit aligned.
if (ABI.IsN64() || ABI.IsN32())
Ret += "-n32:64-S128";
Ret += "-i128:128-n32:64-S128";
else
Ret += "-n32-S64";

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60 changes: 60 additions & 0 deletions llvm/test/CodeGen/Mips/data-layout.ll
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@@ -0,0 +1,60 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
; RUN: llc -mtriple=mips64-linux-gnuabi64 -mcpu=mips64 < %s | FileCheck %s -check-prefix=MIPS64
; RUN: llc -mtriple=mips64el-linux-gnuabi64 -mcpu=mips64 < %s | FileCheck %s -check-prefix=MIPS64EL

; MIPS64: .p2align 2, 0x0
; MIPS64-NEXT: Li8:
; MIPS64-NEXT: .byte 10 # 0xa
; MIPS64-NEXT: .size .Li8, 1

; MIPS64EL: .p2align 2, 0x0
; MIPS64EL-NEXT: Li8:
; MIPS64EL-NEXT: .byte 10 # 0xa
; MIPS64EL-NEXT: .size .Li8, 1
@i8 = private constant i8 10

; MIPS64: .p2align 2, 0x0
; MIPS64-NEXT: .Li16:
; MIPS64-NEXT: .2byte 10 # 0xa
; MIPS64-NEXT: .size .Li16, 2

; MIPS64EL: .p2align 2, 0x0
; MIPS64EL-NEXT: .Li16:
; MIPS64EL-NEXT: .2byte 10 # 0xa
; MIPS64EL-NEXT: .size .Li16, 2
@i16 = private constant i16 10

; MIPS64: .p2align 2, 0x0
; MIPS64-NEXT: .Li32:
; MIPS64-NEXT: .4byte 10 # 0xa
; MIPS64-NEXT: .size .Li32, 4

; MIPS64EL: .p2align 2, 0x0
; MIPS64EL-NEXT: .Li32:
; MIPS64EL-NEXT: .4byte 10 # 0xa
; MIPS64EL-NEXT: .size .Li32, 4
@i32 = private constant i32 10

; MIPS64: .p2align 3, 0x0
; MIPS64-NEXT: .Li64:
; MIPS64-NEXT: .8byte 10 # 0xa
; MIPS64-NEXT: .size .Li64, 8

; MIPS64EL: .p2align 3, 0x0
; MIPS64EL-NEXT: .Li64:
; MIPS64EL-NEXT: .8byte 10 # 0xa
; MIPS64EL-NEXT: .size .Li64, 8
@i64 = private constant i64 10

; MIPS64: .p2align 4, 0x0
; MIPS64-NEXT: .Li128:
; MIPS64-NEXT: .8byte 0
; MIPS64-NEXT: .8byte 10
; MIPS64-NEXT: .size .Li128, 16

; MIPS64EL: .p2align 4, 0x0
; MIPS64EL-NEXT: .Li128:
; MIPS64EL-NEXT: .8byte 10
; MIPS64EL-NEXT: .8byte 0
; MIPS64EL-NEXT: .size .Li128, 16
@i128 = private constant i128 10
18 changes: 9 additions & 9 deletions llvm/test/CodeGen/Mips/implicit-sret.ll
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Expand Up @@ -11,21 +11,21 @@ declare dso_local { i32, i128, i64 } @implicit_sret_decl() unnamed_addr
define internal void @test() unnamed_addr nounwind {
; CHECK-LABEL: test:
; CHECK: # %bb.0: # %start
; CHECK-NEXT: daddiu $sp, $sp, -48
; CHECK-NEXT: sd $ra, 40($sp) # 8-byte Folded Spill
; CHECK-NEXT: daddiu $4, $sp, 8
; CHECK-NEXT: daddiu $sp, $sp, -64
; CHECK-NEXT: sd $ra, 56($sp) # 8-byte Folded Spill
; CHECK-NEXT: daddiu $4, $sp, 0
; CHECK-NEXT: jal implicit_sret_decl
; CHECK-NEXT: nop
; CHECK-NEXT: ld $6, 24($sp)
; CHECK-NEXT: ld $5, 16($sp)
; CHECK-NEXT: ld $7, 32($sp)
; CHECK-NEXT: lw $1, 8($sp)
; CHECK-NEXT: lw $1, 0($sp)
; CHECK-NEXT: # implicit-def: $a0_64
; CHECK-NEXT: move $4, $1
; CHECK-NEXT: jal use_sret
; CHECK-NEXT: nop
; CHECK-NEXT: ld $ra, 40($sp) # 8-byte Folded Reload
; CHECK-NEXT: daddiu $sp, $sp, 48
; CHECK-NEXT: ld $ra, 56($sp) # 8-byte Folded Reload
; CHECK-NEXT: daddiu $sp, $sp, 64
; CHECK-NEXT: jr $ra
; CHECK-NEXT: nop
start:
Expand All @@ -42,11 +42,11 @@ define internal { i32, i128, i64 } @implicit_sret_impl() unnamed_addr nounwind {
; CHECK: # %bb.0:
; CHECK-NEXT: # kill: def $at_64 killed $a0_64
; CHECK-NEXT: daddiu $1, $zero, 20
; CHECK-NEXT: sd $1, 16($4)
; CHECK-NEXT: sd $1, 24($4)
; CHECK-NEXT: daddiu $1, $zero, 0
; CHECK-NEXT: sd $zero, 8($4)
; CHECK-NEXT: sd $zero, 16($4)
; CHECK-NEXT: daddiu $1, $zero, 30
; CHECK-NEXT: sd $1, 24($4)
; CHECK-NEXT: sd $1, 32($4)
; CHECK-NEXT: addiu $1, $zero, 10
; CHECK-NEXT: sw $1, 0($4)
; CHECK-NEXT: jr $ra
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12 changes: 12 additions & 0 deletions llvm/unittests/Bitcode/DataLayoutUpgradeTest.cpp
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Expand Up @@ -75,6 +75,18 @@ TEST(DataLayoutUpgradeTest, ValidDataLayoutUpgrade) {
EXPECT_EQ(UpgradeDataLayoutString("E-m:e-i64:64-n32:64-S128", "sparcv9"),
"E-m:e-i64:64-i128:128-n32:64-S128");

// Check that MIPS64 targets add -i128:128.
EXPECT_EQ(UpgradeDataLayoutString(
"E-m:e-i8:8:32-i16:16:32-i64:64-n32:64-S128", "mips64"),
"E-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128");
EXPECT_EQ(UpgradeDataLayoutString(
"e-m:e-i8:8:32-i16:16:32-i64:64-n32:64-S128", "mips64el"),
"e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128");
//but that mips64el with o32 does not.
EXPECT_EQ(UpgradeDataLayoutString(
"e-m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32-S64", "mips64el"),
"e-m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32-S64");

// Check that SPIR && SPIRV targets add -G1 if it's not present.
EXPECT_EQ(UpgradeDataLayoutString("e-p:32:32", "spir"), "e-p:32:32-G1");
EXPECT_EQ(UpgradeDataLayoutString("e-p:32:32", "spir64"), "e-p:32:32-G1");
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