Skip to content

Commit d47bc6f

Browse files
topperctopperc
committed
[ARM] Change FastISel Address from a struct to a class. NFC
This allows us to use Register in the interface, but store an unsigned internally in a union.
1 parent 0f646fc commit d47bc6f

File tree

1 file changed

+73
-41
lines changed

1 file changed

+73
-41
lines changed

‎llvm/lib/Target/ARM/ARMFastISel.cpp

Lines changed: 73 additions & 41 deletions
Original file line numberDiff line numberDiff line change
@@ -83,23 +83,55 @@ using namespace llvm;
8383
namespace {
8484

8585
// All possible address modes, plus some.
86-
struct Address {
87-
enum {
86+
class Address {
87+
public:
88+
using BaseKind = enum {
8889
RegBase,
8990
FrameIndexBase
90-
} BaseType = RegBase;
91+
};
9192

93+
private:
94+
BaseKind Kind = RegBase;
9295
union {
9396
unsigned Reg;
9497
int FI;
9598
} Base;
9699

97100
int Offset = 0;
98101

102+
public:
99103
// Innocuous defaults for our address.
100104
Address() {
101105
Base.Reg = 0;
102106
}
107+
108+
void setKind(BaseKind K) { Kind = K; }
109+
BaseKind getKind() const { return Kind; }
110+
bool isRegBase() const { return Kind == RegBase; }
111+
bool isFIBase() const { return Kind == FrameIndexBase; }
112+
113+
void setReg(Register Reg) {
114+
assert(isRegBase() && "Invalid base register access!");
115+
Base.Reg = Reg.id();
116+
}
117+
118+
Register getReg() const {
119+
assert(isRegBase() && "Invalid base register access!");
120+
return Base.Reg;
121+
}
122+
123+
void setFI(int FI) {
124+
assert(isFIBase() && "Invalid base frame index access!");
125+
Base.FI = FI;
126+
}
127+
128+
int getFI() const {
129+
assert(isFIBase() && "Invalid base frame index access!");
130+
return Base.FI;
131+
}
132+
133+
void setOffset(int O) { Offset = O; }
134+
int getOffset() { return Offset; }
103135
};
104136

105137
class ARMFastISel final : public FastISel {
@@ -738,7 +770,7 @@ bool ARMFastISel::ARMComputeAddress(const Value *Obj, Address &Addr) {
738770
break;
739771
case Instruction::GetElementPtr: {
740772
Address SavedAddr = Addr;
741-
int TmpOffset = Addr.Offset;
773+
int TmpOffset = Addr.getOffset();
742774

743775
// Iterate through the GEP folding the constants into offsets where
744776
// we can.
@@ -774,7 +806,7 @@ bool ARMFastISel::ARMComputeAddress(const Value *Obj, Address &Addr) {
774806
}
775807

776808
// Try to grab the base operand now.
777-
Addr.Offset = TmpOffset;
809+
Addr.setOffset(TmpOffset);
778810
if (ARMComputeAddress(U->getOperand(0), Addr)) return true;
779811

780812
// We failed, restore everything and try the other options.
@@ -788,17 +820,17 @@ bool ARMFastISel::ARMComputeAddress(const Value *Obj, Address &Addr) {
788820
DenseMap<const AllocaInst*, int>::iterator SI =
789821
FuncInfo.StaticAllocaMap.find(AI);
790822
if (SI != FuncInfo.StaticAllocaMap.end()) {
791-
Addr.BaseType = Address::FrameIndexBase;
792-
Addr.Base.FI = SI->second;
823+
Addr.setKind(Address::FrameIndexBase);
824+
Addr.setFI(SI->second);
793825
return true;
794826
}
795827
break;
796828
}
797829
}
798830

799831
// Try to get this in a register if nothing else has worked.
800-
if (Addr.Base.Reg == 0) Addr.Base.Reg = getRegForValue(Obj);
801-
return Addr.Base.Reg != 0;
832+
if (!Addr.getReg()) Addr.setReg(getRegForValue(Obj));
833+
return Addr.getReg();
802834
}
803835

804836
void ARMFastISel::ARMSimplifyAddress(Address &Addr, MVT VT, bool useAM3) {
@@ -811,45 +843,45 @@ void ARMFastISel::ARMSimplifyAddress(Address &Addr, MVT VT, bool useAM3) {
811843
case MVT::i32:
812844
if (!useAM3) {
813845
// Integer loads/stores handle 12-bit offsets.
814-
needsLowering = ((Addr.Offset & 0xfff) != Addr.Offset);
846+
needsLowering = ((Addr.getOffset() & 0xfff) != Addr.getOffset());
815847
// Handle negative offsets.
816848
if (needsLowering && isThumb2)
817-
needsLowering = !(Subtarget->hasV6T2Ops() && Addr.Offset < 0 &&
818-
Addr.Offset > -256);
849+
needsLowering = !(Subtarget->hasV6T2Ops() && Addr.getOffset() < 0 &&
850+
Addr.getOffset() > -256);
819851
} else {
820852
// ARM halfword load/stores and signed byte loads use +/-imm8 offsets.
821-
needsLowering = (Addr.Offset > 255 || Addr.Offset < -255);
853+
needsLowering = (Addr.getOffset() > 255 || Addr.getOffset() < -255);
822854
}
823855
break;
824856
case MVT::f32:
825857
case MVT::f64:
826858
// Floating point operands handle 8-bit offsets.
827-
needsLowering = ((Addr.Offset & 0xff) != Addr.Offset);
859+
needsLowering = ((Addr.getOffset() & 0xff) != Addr.getOffset());
828860
break;
829861
}
830862

831863
// If this is a stack pointer and the offset needs to be simplified then
832864
// put the alloca address into a register, set the base type back to
833865
// register and continue. This should almost never happen.
834-
if (needsLowering && Addr.BaseType == Address::FrameIndexBase) {
866+
if (needsLowering && Addr.isFIBase()) {
835867
const TargetRegisterClass *RC = isThumb2 ? &ARM::tGPRRegClass
836868
: &ARM::GPRRegClass;
837869
Register ResultReg = createResultReg(RC);
838870
unsigned Opc = isThumb2 ? ARM::t2ADDri : ARM::ADDri;
839871
AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD,
840872
TII.get(Opc), ResultReg)
841-
.addFrameIndex(Addr.Base.FI)
873+
.addFrameIndex(Addr.getFI())
842874
.addImm(0));
843-
Addr.Base.Reg = ResultReg;
844-
Addr.BaseType = Address::RegBase;
875+
Addr.setKind(Address::RegBase);
876+
Addr.setReg(ResultReg);
845877
}
846878

847879
// Since the offset is too large for the load/store instruction
848880
// get the reg+offset into a register.
849881
if (needsLowering) {
850-
Addr.Base.Reg = fastEmit_ri_(MVT::i32, ISD::ADD, Addr.Base.Reg,
851-
Addr.Offset, MVT::i32);
852-
Addr.Offset = 0;
882+
Addr.setReg(fastEmit_ri_(MVT::i32, ISD::ADD, Addr.getReg(),
883+
Addr.getOffset(), MVT::i32));
884+
Addr.setOffset(0);
853885
}
854886
}
855887

@@ -860,12 +892,12 @@ void ARMFastISel::AddLoadStoreOperands(MVT VT, Address &Addr,
860892
// addrmode5 output depends on the selection dag addressing dividing the
861893
// offset by 4 that it then later multiplies. Do this here as well.
862894
if (VT.SimpleTy == MVT::f32 || VT.SimpleTy == MVT::f64)
863-
Addr.Offset /= 4;
895+
Addr.setOffset(Addr.getOffset() / 4);
864896

865897
// Frame base works a bit differently. Handle it separately.
866-
if (Addr.BaseType == Address::FrameIndexBase) {
867-
int FI = Addr.Base.FI;
868-
int Offset = Addr.Offset;
898+
if (Addr.isFIBase()) {
899+
int FI = Addr.getFI();
900+
int Offset = Addr.getOffset();
869901
MachineMemOperand *MMO = FuncInfo.MF->getMachineMemOperand(
870902
MachinePointerInfo::getFixedStack(*FuncInfo.MF, FI, Offset), Flags,
871903
MFI.getObjectSize(FI), MFI.getObjectAlign(FI));
@@ -875,25 +907,25 @@ void ARMFastISel::AddLoadStoreOperands(MVT VT, Address &Addr,
875907
// ARM halfword load/stores and signed byte loads need an additional
876908
// operand.
877909
if (useAM3) {
878-
int Imm = (Addr.Offset < 0) ? (0x100 | -Addr.Offset) : Addr.Offset;
910+
int Imm = (Addr.getOffset() < 0) ? (0x100 | -Addr.getOffset()) : Addr.getOffset();
879911
MIB.addReg(0);
880912
MIB.addImm(Imm);
881913
} else {
882-
MIB.addImm(Addr.Offset);
914+
MIB.addImm(Addr.getOffset());
883915
}
884916
MIB.addMemOperand(MMO);
885917
} else {
886918
// Now add the rest of the operands.
887-
MIB.addReg(Addr.Base.Reg);
919+
MIB.addReg(Addr.getReg());
888920

889921
// ARM halfword load/stores and signed byte loads need an additional
890922
// operand.
891923
if (useAM3) {
892-
int Imm = (Addr.Offset < 0) ? (0x100 | -Addr.Offset) : Addr.Offset;
924+
int Imm = (Addr.getOffset() < 0) ? (0x100 | -Addr.getOffset()) : Addr.getOffset();
893925
MIB.addReg(0);
894926
MIB.addImm(Imm);
895927
} else {
896-
MIB.addImm(Addr.Offset);
928+
MIB.addImm(Addr.getOffset());
897929
}
898930
}
899931
AddOptionalDefs(MIB);
@@ -912,7 +944,7 @@ bool ARMFastISel::ARMEmitLoad(MVT VT, Register &ResultReg, Address &Addr,
912944
case MVT::i1:
913945
case MVT::i8:
914946
if (isThumb2) {
915-
if (Addr.Offset < 0 && Addr.Offset > -256 && Subtarget->hasV6T2Ops())
947+
if (Addr.getOffset() < 0 && Addr.getOffset() > -256 && Subtarget->hasV6T2Ops())
916948
Opc = isZExt ? ARM::t2LDRBi8 : ARM::t2LDRSBi8;
917949
else
918950
Opc = isZExt ? ARM::t2LDRBi12 : ARM::t2LDRSBi12;
@@ -932,7 +964,7 @@ bool ARMFastISel::ARMEmitLoad(MVT VT, Register &ResultReg, Address &Addr,
932964
return false;
933965

934966
if (isThumb2) {
935-
if (Addr.Offset < 0 && Addr.Offset > -256 && Subtarget->hasV6T2Ops())
967+
if (Addr.getOffset() < 0 && Addr.getOffset() > -256 && Subtarget->hasV6T2Ops())
936968
Opc = isZExt ? ARM::t2LDRHi8 : ARM::t2LDRSHi8;
937969
else
938970
Opc = isZExt ? ARM::t2LDRHi12 : ARM::t2LDRSHi12;
@@ -948,7 +980,7 @@ bool ARMFastISel::ARMEmitLoad(MVT VT, Register &ResultReg, Address &Addr,
948980
return false;
949981

950982
if (isThumb2) {
951-
if (Addr.Offset < 0 && Addr.Offset > -256 && Subtarget->hasV6T2Ops())
983+
if (Addr.getOffset() < 0 && Addr.getOffset() > -256 && Subtarget->hasV6T2Ops())
952984
Opc = ARM::t2LDRi8;
953985
else
954986
Opc = ARM::t2LDRi12;
@@ -1061,7 +1093,7 @@ bool ARMFastISel::ARMEmitStore(MVT VT, Register SrcReg, Address &Addr,
10611093
}
10621094
case MVT::i8:
10631095
if (isThumb2) {
1064-
if (Addr.Offset < 0 && Addr.Offset > -256 && Subtarget->hasV6T2Ops())
1096+
if (Addr.getOffset() < 0 && Addr.getOffset() > -256 && Subtarget->hasV6T2Ops())
10651097
StrOpc = ARM::t2STRBi8;
10661098
else
10671099
StrOpc = ARM::t2STRBi12;
@@ -1075,7 +1107,7 @@ bool ARMFastISel::ARMEmitStore(MVT VT, Register SrcReg, Address &Addr,
10751107
return false;
10761108

10771109
if (isThumb2) {
1078-
if (Addr.Offset < 0 && Addr.Offset > -256 && Subtarget->hasV6T2Ops())
1110+
if (Addr.getOffset() < 0 && Addr.getOffset() > -256 && Subtarget->hasV6T2Ops())
10791111
StrOpc = ARM::t2STRHi8;
10801112
else
10811113
StrOpc = ARM::t2STRHi12;
@@ -1090,7 +1122,7 @@ bool ARMFastISel::ARMEmitStore(MVT VT, Register SrcReg, Address &Addr,
10901122
return false;
10911123

10921124
if (isThumb2) {
1093-
if (Addr.Offset < 0 && Addr.Offset > -256 && Subtarget->hasV6T2Ops())
1125+
if (Addr.getOffset() < 0 && Addr.getOffset() > -256 && Subtarget->hasV6T2Ops())
10941126
StrOpc = ARM::t2STRi8;
10951127
else
10961128
StrOpc = ARM::t2STRi12;
@@ -2031,9 +2063,9 @@ bool ARMFastISel::ProcessCallArgs(SmallVectorImpl<Value*> &Args,
20312063
continue;
20322064

20332065
Address Addr;
2034-
Addr.BaseType = Address::RegBase;
2035-
Addr.Base.Reg = ARM::SP;
2036-
Addr.Offset = VA.getLocMemOffset();
2066+
Addr.setKind(Address::RegBase);
2067+
Addr.setReg(ARM::SP);
2068+
Addr.setOffset(VA.getLocMemOffset());
20372069

20382070
bool EmitRet = ARMEmitStore(ArgVT, Arg, Addr); (void)EmitRet;
20392071
assert(EmitRet && "Could not emit a store for argument!");
@@ -2506,8 +2538,8 @@ bool ARMFastISel::ARMTryEmitSmallMemCpy(Address Dest, Address Src, uint64_t Len,
25062538

25072539
unsigned Size = VT.getSizeInBits()/8;
25082540
Len -= Size;
2509-
Dest.Offset += Size;
2510-
Src.Offset += Size;
2541+
Dest.setOffset(Dest.getOffset() + Size);
2542+
Src.setOffset(Src.getOffset() + Size);
25112543
}
25122544

25132545
return true;

0 commit comments

Comments
 (0)