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Thomas Johnson
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[ARC] Add additional mov immediate instruction formats with a fix for u6 decoding
Differential Revision: https://reviews.llvm.org/D107088
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5 files changed

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‎llvm/lib/Target/ARC/ARCInstrFormats.td

Lines changed: 25 additions & 27 deletions
Original file line numberDiff line numberDiff line change
@@ -261,32 +261,6 @@ class F32_SOP_RR<bits<5> major, bits<6> subop, bit F, dag outs, dag ins,
261261
let Inst{5-0} = subop;
262262
}
263263

264-
// Single Operand Immediate Instructions.
265-
// 1-register, unsigned 6-bit immediate Single Operand instruction with
266-
// condition code.
267-
// |26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|9|8|7|6|5|4|3|2|1|0|
268-
// |B[2-0] | 1| 1| subop| F|B[5-3] |U6 |1|cc |
269-
class F32_SOP_CC_RU6<bits<5> major, bits<6> subop, bit F, dag outs, dag ins,
270-
string asmstr, list<dag> pattern> :
271-
InstARC<4, outs, ins, asmstr, pattern> {
272-
273-
bits<5> cc;
274-
bits<6> U6;
275-
bits<6> B;
276-
277-
let Inst{31-27} = major;
278-
let Inst{26-24} = B{2-0};
279-
let Inst{23-22} = 0b11;
280-
let Inst{21-16} = subop;
281-
let Inst{15} = F;
282-
let Inst{14-12} = B{5-3};
283-
let Inst{11-6} = U6;
284-
let Inst{5} = 1;
285-
let Inst{4-0} = cc;
286-
287-
let DecoderMethod = "DecodeCCRU6Instruction";
288-
}
289-
290264
// Dual Operand Instructions. Inst[21-16] specifies the specific operation
291265
// for this format.
292266

@@ -353,6 +327,31 @@ class F32_DOP_RU6<bits<5> major, bits<6> subop, bit F, dag outs, dag ins,
353327
let Inst{5-0} = A;
354328
}
355329

330+
// 1-register, unsigned 6-bit, immediate Dual Operand instruction with
331+
// condition code.
332+
// |26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|9|8|7|6|5|4|3|2|1|0|
333+
// |B[2-0] | 1| 1| subop| F|B[5-3] |U6 |1|cc |
334+
class F32_DOP_CC_RU6<bits<5> major, bits<6> subop, bit F, dag outs, dag ins,
335+
string asmstr, list<dag> pattern> :
336+
InstARC<4, outs, ins, asmstr, pattern> {
337+
338+
bits<5> cc;
339+
bits<6> U6;
340+
bits<6> B;
341+
342+
let Inst{31-27} = major;
343+
let Inst{26-24} = B{2-0};
344+
let Inst{23-22} = 0b11;
345+
let Inst{21-16} = subop;
346+
let Inst{15} = F;
347+
let Inst{14-12} = B{5-3};
348+
let Inst{11-6} = U6;
349+
let Inst{5} = 1;
350+
let Inst{4-0} = cc;
351+
352+
let DecoderMethod = "DecodeCCRU6Instruction";
353+
}
354+
356355
// 2-register, unsigned 6-bit immediate Dual Operand instruction with
357356
// condition code. This instruction uses B as the first 2 operands
358357
// (i.e, add.cc B, B, u6).
@@ -364,7 +363,6 @@ class F32_DOP_CC_RRU6<bits<5> major, bits<6> subop, bit F, dag outs, dag ins,
364363
bits<5> cc;
365364
bits<6> U6;
366365
bits<6> B;
367-
bits<6> A;
368366

369367
let Inst{31-27} = major;
370368
let Inst{26-24} = B{2-0};

‎llvm/lib/Target/ARC/ARCInstrInfo.td

Lines changed: 22 additions & 16 deletions
Original file line numberDiff line numberDiff line change
@@ -337,24 +337,30 @@ def MOV_ru6 : F32_DOP_RU6<0b00100, 0b001010, 0,
337337
(outs GPR32:$B), (ins immU6:$U6),
338338
"mov\t$B, $U6", []>;
339339

340+
def MOV_f_ru6 : F32_DOP_RU6<0b00100, 0b001010, 1,
341+
(outs GPR32:$B), (ins u6:$U6),
342+
"mov.f\t$B, $U6", []> {
343+
let isAsCheapAsAMove=1;
344+
let Defs = [STATUS32];
345+
}
346+
340347
def cmov : PatFrag<(ops node:$op1, node:$op2, node:$cc),
341348
(ARCcmov $op1, $op2, $cc)>;
342-
let Uses = [STATUS32] in {
343-
def MOVcc : F32_DOP_CC_RR<0b00100, 0b001010, 0,
344-
(outs GPR32:$B),
345-
(ins GPR32:$C, GPR32:$fval, cmovpred:$cc),
346-
!strconcat("mov.", "$cc\t$B, $C"),
347-
[(set GPR32:$B, (cmov i32:$C, i32:$fval, cmovpred:$cc))]> {
348-
let Constraints = "$B = $fval";
349-
}
350-
351-
def MOVcc_ru6 : F32_SOP_CC_RU6<0b00100, 0b001010, 0,
352-
(outs GPR32:$b), (ins u6:$c, CCOp:$cc, GPR32:$b2),
353-
"mov.$cc\t$b, $c", []> {
354-
let isAsCheapAsAMove=0;
355-
let isPredicable=1;
356-
let isReMaterializable=0;
357-
let Constraints="$b2 = $b";
349+
let Uses = [STATUS32], isAsCheapAsAMove = 1, isPredicable=1,
350+
isReMaterializable = 0, Constraints = "$B = $B2" in {
351+
def MOV_cc : F32_DOP_CC_RR<0b00100, 0b001010, 0,
352+
(outs GPR32:$B), (ins GPR32:$C, GPR32:$B2, cmovpred:$cc),
353+
"mov.$cc\t$B, $C",
354+
[(set GPR32:$B, (cmov i32:$C, i32:$B2, cmovpred:$cc))]>;
355+
356+
def MOV_cc_ru6 : F32_DOP_CC_RU6<0b00100, 0b001010, 0,
357+
(outs GPR32:$B), (ins u6:$C, CCOp:$cc, GPR32:$B2),
358+
"mov.$cc\t$B, $C", []>;
359+
360+
def MOV_cc_f_ru6 : F32_DOP_CC_RU6<0b00100, 0b001010, 1,
361+
(outs GPR32:$B), (ins u6:$C, CCOp:$cc, GPR32:$B2),
362+
"mov.$cc.f\t$B, $C", []> {
363+
let Defs = [STATUS32];
358364
}
359365
}
360366

‎llvm/lib/Target/ARC/Disassembler/ARCDisassembler.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -304,7 +304,7 @@ static DecodeStatus DecodeCCRU6Instruction(MCInst &Inst, uint64_t Insn,
304304
DstB = decodeBField(Insn);
305305
DecodeGPR32RegisterClass(Inst, DstB, Address, Decoder);
306306
using Field = decltype(Insn);
307-
Field U6Field = fieldFromInstruction(Insn, 6, 11);
307+
Field U6Field = fieldFromInstruction(Insn, 6, 6);
308308
Inst.addOperand(MCOperand::createImm(U6Field));
309309
Field CCField = fieldFromInstruction(Insn, 0, 4);
310310
Inst.addOperand(MCOperand::createImm(CCField));

‎llvm/test/MC/Disassembler/ARC/alu.txt

Lines changed: 162 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -18,6 +18,60 @@
1818
# CHECK: add %r2, %r7, %r4
1919
0x00 0x27 0x02 0x01
2020

21+
# CHECK: add.eq %r0, %r0, 1
22+
0xc0 0x20 0x61 0x00
23+
24+
# CHECK: add.lt %r6, %r6, 16
25+
0xc0 0x26 0x2b 0x04
26+
27+
# CHECK: add.le %r15, %r15, 31
28+
0xc0 0x27 0xec 0x17
29+
30+
# CHECK: add.gt %r0, %r0, 1
31+
0xc0 0x20 0x69 0x00
32+
33+
# CHECK: add.ge %r6, %r6, 16
34+
0xc0 0x26 0x2a 0x04
35+
36+
# CHECK: add.p %r15, %r15, 31
37+
0xc0 0x27 0xe3 0x17
38+
39+
# CHECK: add.n %r0, %r0, 1
40+
0xc0 0x20 0x64 0x00
41+
42+
# CHECK: add.vs %r6, %r6, 16
43+
0xc0 0x26 0x27 0x04
44+
45+
# CHECK: add.pnz %r15, %r15, 31
46+
0xc0 0x27 0xef 0x17
47+
48+
# CHECK: add.eq.f %r0, %r0, 1
49+
0xc0 0x20 0x61 0x80
50+
51+
# CHECK: add.lt.f %r6, %r6, 16
52+
0xc0 0x26 0x2b 0x84
53+
54+
# CHECK: add.le.f %r15, %r15, 31
55+
0xc0 0x27 0xec 0x97
56+
57+
# CHECK: add.gt.f %r0, %r0, 1
58+
0xc0 0x20 0x69 0x80
59+
60+
# CHECK: add.ge.f %r6, %r6, 16
61+
0xc0 0x26 0x2a 0x84
62+
63+
# CHECK: add.p.f %r15, %r15, 31
64+
0xc0 0x27 0xe3 0x97
65+
66+
# CHECK: add.n.f %r0, %r0, 1
67+
0xc0 0x20 0x64 0x80
68+
69+
# CHECK: add.vs.f %r6, %r6, 16
70+
0xc0 0x26 0x27 0x84
71+
72+
# CHECK: add.pnz.f %r15, %r15, 31
73+
0xc0 0x27 0xef 0x97
74+
2175
# CHECK: and %r2, %r7, %r4
2276
0x04 0x27 0x02 0x01
2377

@@ -33,6 +87,60 @@
3387
# CHECK: and.f %r1, %r1, 255
3488
0x84 0x21 0xc3 0x8f
3589

90+
# CHECK: and.eq %r0, %r0, 0
91+
0xc4 0x20 0x21 0x00
92+
93+
# CHECK: and.lt %r6, %r6, 16
94+
0xc4 0x26 0x2b 0x04
95+
96+
# CHECK: and.le %r15, %r15, 31
97+
0xc4 0x27 0xec 0x17
98+
99+
# CHECK: and.gt %r0, %r0, 0
100+
0xc4 0x20 0x29 0x00
101+
102+
# CHECK: and.ge %r6, %r6, 16
103+
0xc4 0x26 0x2a 0x04
104+
105+
# CHECK: and.p %r15, %r15, 31
106+
0xc4 0x27 0xe3 0x17
107+
108+
# CHECK: and.n %r0, %r0, 0
109+
0xc4 0x20 0x24 0x00
110+
111+
# CHECK: and.vs %r6, %r6, 16
112+
0xc4 0x26 0x27 0x04
113+
114+
# CHECK: and.pnz %r15, %r15, 31
115+
0xc4 0x27 0xef 0x17
116+
117+
# CHECK: and.eq.f %r0, %r0, 0
118+
0xc4 0x20 0x21 0x80
119+
120+
# CHECK: and.lt.f %r6, %r6, 16
121+
0xc4 0x26 0x2b 0x84
122+
123+
# CHECK: and.le.f %r15, %r15, 31
124+
0xc4 0x27 0xec 0x97
125+
126+
# CHECK: and.gt.f %r0, %r0, 0
127+
0xc4 0x20 0x29 0x80
128+
129+
# CHECK: and.ge.f %r6, %r6, 16
130+
0xc4 0x26 0x2a 0x84
131+
132+
# CHECK: and.p.f %r15, %r15, 31
133+
0xc4 0x27 0xe3 0x97
134+
135+
# CHECK: and.n.f %r0, %r0, 0
136+
0xc4 0x20 0x24 0x80
137+
138+
# CHECK: and.vs.f %r6, %r6, 16
139+
0xc4 0x26 0x27 0x84
140+
141+
# CHECK: and.pnz.f %r15, %r15, 31
142+
0xc4 0x27 0xef 0x97
143+
36144
# CHECK: asl %r1, %r1, 2
37145
0x40 0x29 0x81 0x00
38146

@@ -105,11 +213,62 @@
105213
# CHECK: sub3.f %fp, %fp, -1
106214
0x99 0x23 0xff 0xbf
107215

108-
# CHECK: rsub.eq %r0, %r0, 30
109-
0xce 0x20 0xa1 0x07
110-
111216
# CHECK: rsub.ne %r0, %r0, 31
112217
0xce 0x20 0xe2 0x07
113218

219+
# CHECK: rsub.eq %r0, %r0, 1
220+
0xce 0x20 0x61 0x00
221+
222+
# CHECK: rsub.lt %r6, %r6, 16
223+
0xce 0x26 0x2b 0x04
224+
225+
# CHECK: rsub.le %r15, %r15, 31
226+
0xce 0x27 0xec 0x17
227+
228+
# CHECK: rsub.gt %r0, %r0, 1
229+
0xce 0x20 0x69 0x00
230+
231+
# CHECK: rsub.ge %r6, %r6, 16
232+
0xce 0x26 0x2a 0x04
233+
234+
# CHECK: rsub.p %r15, %r15, 31
235+
0xce 0x27 0xe3 0x17
236+
237+
# CHECK: rsub.n %r0, %r0, 1
238+
0xce 0x20 0x64 0x00
239+
240+
# CHECK: rsub.vs %r6, %r6, 16
241+
0xce 0x26 0x27 0x04
242+
243+
# CHECK: rsub.pnz %r15, %r15, 31
244+
0xce 0x27 0xef 0x17
245+
114246
# CHECK: rsub.ne.f %r0, %r0, 31
115247
0xce 0x20 0xe2 0x87
248+
249+
# CHECK: rsub.eq.f %r0, %r0, 1
250+
0xce 0x20 0x61 0x80
251+
252+
# CHECK: rsub.lt.f %r6, %r6, 16
253+
0xce 0x26 0x2b 0x84
254+
255+
# CHECK: rsub.le.f %r15, %r15, 31
256+
0xce 0x27 0xec 0x97
257+
258+
# CHECK: rsub.gt.f %r0, %r0, 1
259+
0xce 0x20 0x69 0x80
260+
261+
# CHECK: rsub.ge.f %r6, %r6, 16
262+
0xce 0x26 0x2a 0x84
263+
264+
# CHECK: rsub.p.f %r15, %r15, 31
265+
0xce 0x27 0xe3 0x97
266+
267+
# CHECK: rsub.n.f %r0, %r0, 1
268+
0xce 0x20 0x64 0x80
269+
270+
# CHECK: rsub.vs.f %r6, %r6, 16
271+
0xce 0x26 0x27 0x84
272+
273+
# CHECK: rsub.pnz.f %r15, %r15, 31
274+
0xce 0x27 0xef 0x97

‎llvm/test/MC/Disassembler/ARC/misc.txt

Lines changed: 63 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -22,6 +22,69 @@
2222
# CHECK: mov.ne %r0, 0
2323
0xca 0x20 0x22 0x00
2424

25+
# CHECK: mov.eq %r0, 0
26+
0xca 0x20 0x21 0x00
27+
28+
# CHECK: mov.lt %r6, 16
29+
0xca 0x26 0x2b 0x04
30+
31+
# CHECK: mov.le %r15, 31
32+
0xca 0x27 0xec 0x17
33+
34+
# CHECK: mov.gt %r0, 0
35+
0xca 0x20 0x29 0x00
36+
37+
# CHECK: mov.ge %r6, 16
38+
0xca 0x26 0x2a 0x04
39+
40+
# CHECK: mov.p %r15, 31
41+
0xca 0x27 0xe3 0x17
42+
43+
# CHECK: mov.n %r0, 0
44+
0xca 0x20 0x24 0x00
45+
46+
# CHECK: mov.vs %r6, 16
47+
0xca 0x26 0x27 0x04
48+
49+
# CHECK: mov.pnz %r15, 31
50+
0xca 0x27 0xef 0x17
51+
52+
# CHECK: mov.f %r0, 0
53+
0x4a 0x20 0x00 0x80
54+
55+
# CHECK: mov.f %r6, 16
56+
0x4a 0x26 0x00 0x84
57+
58+
# CHECK: mov.f %r15, 31
59+
0x4a 0x27 0xc0 0x97
60+
61+
# CHECK: mov.eq.f %r0, 0
62+
0xca 0x20 0x21 0x80
63+
64+
# CHECK: mov.lt.f %r6, 16
65+
0xca 0x26 0x2b 0x84
66+
67+
# CHECK: mov.le.f %r15, 31
68+
0xca 0x27 0xec 0x97
69+
70+
# CHECK: mov.gt.f %r0, 0
71+
0xca 0x20 0x29 0x80
72+
73+
# CHECK: mov.ge.f %r6, 16
74+
0xca 0x26 0x2a 0x84
75+
76+
# CHECK: mov.p.f %r15, 31
77+
0xca 0x27 0xe3 0x97
78+
79+
# CHECK: mov.n.f %r0, 0
80+
0xca 0x20 0x24 0x80
81+
82+
# CHECK: mov.vs.f %r6, 16
83+
0xca 0x26 0x27 0x84
84+
85+
# CHECK: mov.pnz.f %r15, 31
86+
0xca 0x27 0xef 0x97
87+
2588
# CHECK: st.aw %fp, [%sp,-4]
2689
0xfc 0x1c 0xc8 0xb6
2790

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