@@ -1521,13 +1521,13 @@ class VPseudoTiedBinaryMaskRoundingMode<VReg RetClass,
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let UsesVXRM = 0;
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}
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- class VPseudoBinaryCarryIn <VReg RetClass,
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- VReg Op1Class,
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- DAGOperand Op2Class,
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- LMULInfo MInfo,
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- bit CarryIn,
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- string Constraint,
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- int TargetConstraintType = 1> :
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+ class VPseudoBinaryCarry <VReg RetClass,
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+ VReg Op1Class,
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+ DAGOperand Op2Class,
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+ LMULInfo MInfo,
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+ bit CarryIn,
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+ string Constraint,
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+ int TargetConstraintType = 1> :
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Pseudo<(outs RetClass:$rd),
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!if(CarryIn,
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(ins Op1Class:$rs2, Op2Class:$rs1,
@@ -2454,10 +2454,10 @@ multiclass VPseudoBinaryV_VM<LMULInfo m, bit CarryOut = 0, bit CarryIn = 1,
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int TargetConstraintType = 1> {
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let isCommutable = Commutable in
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def "_VV" # !if(CarryIn, "M", "") # "_" # m.MX :
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- VPseudoBinaryCarryIn <!if(CarryOut, VR,
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- !if(!and(CarryIn, !not(CarryOut)),
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- GetVRegNoV0<m.vrclass>.R, m.vrclass)),
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- m.vrclass, m.vrclass, m, CarryIn, Constraint, TargetConstraintType>;
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+ VPseudoBinaryCarry <!if(CarryOut, VR,
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+ !if(!and(CarryIn, !not(CarryOut)),
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+ GetVRegNoV0<m.vrclass>.R, m.vrclass)),
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+ m.vrclass, m.vrclass, m, CarryIn, Constraint, TargetConstraintType>;
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}
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multiclass VPseudoTiedBinaryV_VM<LMULInfo m, bit Commutable = 0> {
@@ -2470,10 +2470,10 @@ multiclass VPseudoTiedBinaryV_VM<LMULInfo m, bit Commutable = 0> {
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multiclass VPseudoBinaryV_XM<LMULInfo m, bit CarryOut = 0, bit CarryIn = 1,
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string Constraint = "", int TargetConstraintType = 1> {
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def "_VX" # !if(CarryIn, "M", "") # "_" # m.MX :
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- VPseudoBinaryCarryIn <!if(CarryOut, VR,
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- !if(!and(CarryIn, !not(CarryOut)),
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- GetVRegNoV0<m.vrclass>.R, m.vrclass)),
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- m.vrclass, GPR, m, CarryIn, Constraint, TargetConstraintType>;
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+ VPseudoBinaryCarry <!if(CarryOut, VR,
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+ !if(!and(CarryIn, !not(CarryOut)),
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+ GetVRegNoV0<m.vrclass>.R, m.vrclass)),
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+ m.vrclass, GPR, m, CarryIn, Constraint, TargetConstraintType>;
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}
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multiclass VPseudoTiedBinaryV_XM<LMULInfo m> {
@@ -2498,10 +2498,10 @@ multiclass VPseudoVMRG_FM {
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multiclass VPseudoBinaryV_IM<LMULInfo m, bit CarryOut = 0, bit CarryIn = 1,
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string Constraint = "", int TargetConstraintType = 1> {
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def "_VI" # !if(CarryIn, "M", "") # "_" # m.MX :
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- VPseudoBinaryCarryIn <!if(CarryOut, VR,
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- !if(!and(CarryIn, !not(CarryOut)),
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- GetVRegNoV0<m.vrclass>.R, m.vrclass)),
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- m.vrclass, simm5, m, CarryIn, Constraint, TargetConstraintType>;
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+ VPseudoBinaryCarry <!if(CarryOut, VR,
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+ !if(!and(CarryIn, !not(CarryOut)),
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+ GetVRegNoV0<m.vrclass>.R, m.vrclass)),
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+ m.vrclass, simm5, m, CarryIn, Constraint, TargetConstraintType>;
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}
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multiclass VPseudoTiedBinaryV_IM<LMULInfo m> {
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