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[CodeGen] Using ZExt for extractelement indices.
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In #57452, we found that IRTranslator is translating `i1 true` into `i32 -1`.
This is because IRTranslator uses SExt for indices.

In this fix, we change the expected behavior of extractelement's index, moving from SExt to ZExt.
This change includes both documentation, SelectionDAG and IRTranslator.
We also included a test for AMDGPU, updated tests for AArch64, Mips, PowerPC, RISCV, VE, WebAssembly and X86

This patch fixes issue #57452.

Differential Revision: https://reviews.llvm.org/D132978
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@DataCorrupted
DataCorrupted committed Oct 15, 2022
1 parent 8e892c9 commit c2e7c9c
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Showing 35 changed files with 786 additions and 630 deletions.
5 changes: 3 additions & 2 deletions llvm/docs/LangRef.rst
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Original file line number Diff line number Diff line change
Expand Up @@ -9699,7 +9699,7 @@ Arguments:
The first operand of an '``extractelement``' instruction is a value of
:ref:`vector <t_vector>` type. The second operand is an index indicating
the position from which to extract the element. The index may be a
variable of any integer type.
variable of any integer type, and will be treated as an unsigned integer.

Semantics:
""""""""""
Expand Down Expand Up @@ -9744,7 +9744,8 @@ The first operand of an '``insertelement``' instruction is a value of
:ref:`vector <t_vector>` type. The second operand is a scalar value whose
type must equal the element type of the first operand. The third operand
is an index indicating the position at which to insert the value. The
index may be a variable of any integer type.
index may be a variable of any integer type, and will be treated as an
unsigned integer.

Semantics:
""""""""""
Expand Down
4 changes: 2 additions & 2 deletions llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -2813,7 +2813,7 @@ bool IRTranslator::translateExtractElement(const User &U,
Register Idx;
if (auto *CI = dyn_cast<ConstantInt>(U.getOperand(1))) {
if (CI->getBitWidth() != PreferredVecIdxWidth) {
APInt NewIdx = CI->getValue().sextOrTrunc(PreferredVecIdxWidth);
APInt NewIdx = CI->getValue().zextOrTrunc(PreferredVecIdxWidth);
auto *NewIdxCI = ConstantInt::get(CI->getContext(), NewIdx);
Idx = getOrCreateVReg(*NewIdxCI);
}
Expand All @@ -2822,7 +2822,7 @@ bool IRTranslator::translateExtractElement(const User &U,
Idx = getOrCreateVReg(*U.getOperand(1));
if (MRI->getType(Idx).getSizeInBits() != PreferredVecIdxWidth) {
const LLT VecIdxTy = LLT::scalar(PreferredVecIdxWidth);
Idx = MIRBuilder.buildSExtOrTrunc(VecIdxTy, Idx).getReg(0);
Idx = MIRBuilder.buildZExtOrTrunc(VecIdxTy, Idx).getReg(0);
}
MIRBuilder.buildExtractVectorElement(Res, Val, Idx);
return true;
Expand Down
4 changes: 2 additions & 2 deletions llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -3582,7 +3582,7 @@ void SelectionDAGBuilder::visitInsertElement(const User &I) {
const TargetLowering &TLI = DAG.getTargetLoweringInfo();
SDValue InVec = getValue(I.getOperand(0));
SDValue InVal = getValue(I.getOperand(1));
SDValue InIdx = DAG.getSExtOrTrunc(getValue(I.getOperand(2)), getCurSDLoc(),
SDValue InIdx = DAG.getZExtOrTrunc(getValue(I.getOperand(2)), getCurSDLoc(),
TLI.getVectorIdxTy(DAG.getDataLayout()));
setValue(&I, DAG.getNode(ISD::INSERT_VECTOR_ELT, getCurSDLoc(),
TLI.getValueType(DAG.getDataLayout(), I.getType()),
Expand All @@ -3592,7 +3592,7 @@ void SelectionDAGBuilder::visitInsertElement(const User &I) {
void SelectionDAGBuilder::visitExtractElement(const User &I) {
const TargetLowering &TLI = DAG.getTargetLoweringInfo();
SDValue InVec = getValue(I.getOperand(0));
SDValue InIdx = DAG.getSExtOrTrunc(getValue(I.getOperand(1)), getCurSDLoc(),
SDValue InIdx = DAG.getZExtOrTrunc(getValue(I.getOperand(1)), getCurSDLoc(),
TLI.getVectorIdxTy(DAG.getDataLayout()));
setValue(&I, DAG.getNode(ISD::EXTRACT_VECTOR_ELT, getCurSDLoc(),
TLI.getValueType(DAG.getDataLayout(), I.getType()),
Expand Down
23 changes: 22 additions & 1 deletion llvm/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -1549,7 +1549,7 @@ define i32 @test_extractelement(<2 x i32> %vec, i32 %idx) {
; CHECK-LABEL: name: test_extractelement
; CHECK: [[VEC:%[0-9]+]]:_(<2 x s32>) = COPY $d0
; CHECK: [[IDX:%[0-9]+]]:_(s32) = COPY $w0
; CHECK: [[IDXEXT:%[0-9]+]]:_(s64) = G_SEXT [[IDX]]
; CHECK: [[IDXEXT:%[0-9]+]]:_(s64) = G_ZEXT [[IDX]]
; CHECK: [[RES:%[0-9]+]]:_(s32) = G_EXTRACT_VECTOR_ELT [[VEC]](<2 x s32>), [[IDXEXT]](s64)
; CHECK: $w0 = COPY [[RES]](s32)
%res = extractelement <2 x i32> %vec, i32 %idx
Expand All @@ -1566,6 +1566,27 @@ define i32 @test_extractelement_const_idx(<2 x i32> %vec) {
ret i32 %res
}

define i32 @test_extractelement_const_idx_zext_i1(<2 x i32> %vec) {
; CHECK-LABEL: name: test_extractelement
; CHECK: [[VEC:%[0-9]+]]:_(<2 x s32>) = COPY $d0
; CHECK: [[IDX:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
; CHECK: [[RES:%[0-9]+]]:_(s32) = G_EXTRACT_VECTOR_ELT [[VEC]](<2 x s32>), [[IDX]](s64)
; CHECK: $w0 = COPY [[RES]](s32)
%res = extractelement <2 x i32> %vec, i1 true
ret i32 %res
}

define i32 @test_extractelement_const_idx_zext_i8(<2 x i32> %vec) {
; CHECK-LABEL: name: test_extractelement
; CHECK: [[VEC:%[0-9]+]]:_(<2 x s32>) = COPY $d0
; CHECK: [[IDX:%[0-9]+]]:_(s64) = G_CONSTANT i64 255
; CHECK: [[RES:%[0-9]+]]:_(s32) = G_EXTRACT_VECTOR_ELT [[VEC]](<2 x s32>), [[IDX]](s64)
; CHECK: $w0 = COPY [[RES]](s32)
%res = extractelement <2 x i32> %vec, i8 255
ret i32 %res
}


define i32 @test_singleelementvector(i32 %elt){
; CHECK-LABEL: name: test_singleelementvector
; CHECK: [[ELT:%[0-9]+]]:_(s32) = COPY $w0
Expand Down
6 changes: 2 additions & 4 deletions llvm/test/CodeGen/AArch64/arm64-indexed-vector-ldst.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -9143,8 +9143,7 @@ define i32 @load_single_extract_variable_index_i32(<4 x i32>* %A, i32 %idx) {
define i32 @load_single_extract_variable_index_v3i32_small_align(<3 x i32>* %A, i32 %idx) {
; CHECK-LABEL: load_single_extract_variable_index_v3i32_small_align:
; CHECK: ; %bb.0:
; CHECK-NEXT: ; kill: def $w1 killed $w1 def $x1
; CHECK-NEXT: sxtw x9, w1
; CHECK-NEXT: mov w9, w1
; CHECK-NEXT: mov w8, #2
; CHECK-NEXT: cmp x9, #2
; CHECK-NEXT: csel x8, x9, x8, lo
Expand All @@ -9158,8 +9157,7 @@ define i32 @load_single_extract_variable_index_v3i32_small_align(<3 x i32>* %A,
define i32 @load_single_extract_variable_index_v3i32_default_align(<3 x i32>* %A, i32 %idx) {
; CHECK-LABEL: load_single_extract_variable_index_v3i32_default_align:
; CHECK: ; %bb.0:
; CHECK-NEXT: ; kill: def $w1 killed $w1 def $x1
; CHECK-NEXT: sxtw x9, w1
; CHECK-NEXT: mov w9, w1
; CHECK-NEXT: mov w8, #2
; CHECK-NEXT: cmp x9, #2
; CHECK-NEXT: csel x8, x9, x8, lo
Expand Down
33 changes: 11 additions & 22 deletions llvm/test/CodeGen/AArch64/sve-extract-element.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -292,8 +292,7 @@ define double @test_lane2_2xf64(<vscale x 2 x double> %a) #0 {
define i8 @test_lanex_16xi8(<vscale x 16 x i8> %a, i32 %x) #0 {
; CHECK-LABEL: test_lanex_16xi8:
; CHECK: // %bb.0:
; CHECK-NEXT: // kill: def $w0 killed $w0 def $x0
; CHECK-NEXT: sxtw x8, w0
; CHECK-NEXT: mov w8, w0
; CHECK-NEXT: whilels p0.b, xzr, x8
; CHECK-NEXT: lastb w0, p0, z0.b
; CHECK-NEXT: ret
Expand All @@ -304,8 +303,7 @@ define i8 @test_lanex_16xi8(<vscale x 16 x i8> %a, i32 %x) #0 {
define i16 @test_lanex_8xi16(<vscale x 8 x i16> %a, i32 %x) #0 {
; CHECK-LABEL: test_lanex_8xi16:
; CHECK: // %bb.0:
; CHECK-NEXT: // kill: def $w0 killed $w0 def $x0
; CHECK-NEXT: sxtw x8, w0
; CHECK-NEXT: mov w8, w0
; CHECK-NEXT: whilels p0.h, xzr, x8
; CHECK-NEXT: lastb w0, p0, z0.h
; CHECK-NEXT: ret
Expand All @@ -316,8 +314,7 @@ define i16 @test_lanex_8xi16(<vscale x 8 x i16> %a, i32 %x) #0 {
define i32 @test_lanex_4xi32(<vscale x 4 x i32> %a, i32 %x) #0 {
; CHECK-LABEL: test_lanex_4xi32:
; CHECK: // %bb.0:
; CHECK-NEXT: // kill: def $w0 killed $w0 def $x0
; CHECK-NEXT: sxtw x8, w0
; CHECK-NEXT: mov w8, w0
; CHECK-NEXT: whilels p0.s, xzr, x8
; CHECK-NEXT: lastb w0, p0, z0.s
; CHECK-NEXT: ret
Expand All @@ -328,8 +325,7 @@ define i32 @test_lanex_4xi32(<vscale x 4 x i32> %a, i32 %x) #0 {
define i64 @test_lanex_2xi64(<vscale x 2 x i64> %a, i32 %x) #0 {
; CHECK-LABEL: test_lanex_2xi64:
; CHECK: // %bb.0:
; CHECK-NEXT: // kill: def $w0 killed $w0 def $x0
; CHECK-NEXT: sxtw x8, w0
; CHECK-NEXT: mov w8, w0
; CHECK-NEXT: whilels p0.d, xzr, x8
; CHECK-NEXT: lastb x0, p0, z0.d
; CHECK-NEXT: ret
Expand All @@ -340,8 +336,7 @@ define i64 @test_lanex_2xi64(<vscale x 2 x i64> %a, i32 %x) #0 {
define half @test_lanex_8xf16(<vscale x 8 x half> %a, i32 %x) #0 {
; CHECK-LABEL: test_lanex_8xf16:
; CHECK: // %bb.0:
; CHECK-NEXT: // kill: def $w0 killed $w0 def $x0
; CHECK-NEXT: sxtw x8, w0
; CHECK-NEXT: mov w8, w0
; CHECK-NEXT: whilels p0.h, xzr, x8
; CHECK-NEXT: lastb h0, p0, z0.h
; CHECK-NEXT: ret
Expand All @@ -352,8 +347,7 @@ define half @test_lanex_8xf16(<vscale x 8 x half> %a, i32 %x) #0 {
define half @test_lanex_4xf16(<vscale x 4 x half> %a, i32 %x) #0 {
; CHECK-LABEL: test_lanex_4xf16:
; CHECK: // %bb.0:
; CHECK-NEXT: // kill: def $w0 killed $w0 def $x0
; CHECK-NEXT: sxtw x8, w0
; CHECK-NEXT: mov w8, w0
; CHECK-NEXT: whilels p0.s, xzr, x8
; CHECK-NEXT: lastb h0, p0, z0.h
; CHECK-NEXT: ret
Expand All @@ -364,8 +358,7 @@ define half @test_lanex_4xf16(<vscale x 4 x half> %a, i32 %x) #0 {
define half @test_lanex_2xf16(<vscale x 2 x half> %a, i32 %x) #0 {
; CHECK-LABEL: test_lanex_2xf16:
; CHECK: // %bb.0:
; CHECK-NEXT: // kill: def $w0 killed $w0 def $x0
; CHECK-NEXT: sxtw x8, w0
; CHECK-NEXT: mov w8, w0
; CHECK-NEXT: whilels p0.d, xzr, x8
; CHECK-NEXT: lastb h0, p0, z0.h
; CHECK-NEXT: ret
Expand All @@ -376,8 +369,7 @@ define half @test_lanex_2xf16(<vscale x 2 x half> %a, i32 %x) #0 {
define float @test_lanex_4xf32(<vscale x 4 x float> %a, i32 %x) #0 {
; CHECK-LABEL: test_lanex_4xf32:
; CHECK: // %bb.0:
; CHECK-NEXT: // kill: def $w0 killed $w0 def $x0
; CHECK-NEXT: sxtw x8, w0
; CHECK-NEXT: mov w8, w0
; CHECK-NEXT: whilels p0.s, xzr, x8
; CHECK-NEXT: lastb s0, p0, z0.s
; CHECK-NEXT: ret
Expand All @@ -388,8 +380,7 @@ define float @test_lanex_4xf32(<vscale x 4 x float> %a, i32 %x) #0 {
define float @test_lanex_2xf32(<vscale x 2 x float> %a, i32 %x) #0 {
; CHECK-LABEL: test_lanex_2xf32:
; CHECK: // %bb.0:
; CHECK-NEXT: // kill: def $w0 killed $w0 def $x0
; CHECK-NEXT: sxtw x8, w0
; CHECK-NEXT: mov w8, w0
; CHECK-NEXT: whilels p0.d, xzr, x8
; CHECK-NEXT: lastb s0, p0, z0.s
; CHECK-NEXT: ret
Expand All @@ -400,8 +391,7 @@ define float @test_lanex_2xf32(<vscale x 2 x float> %a, i32 %x) #0 {
define double @test_lanex_2xf64(<vscale x 2 x double> %a, i32 %x) #0 {
; CHECK-LABEL: test_lanex_2xf64:
; CHECK: // %bb.0:
; CHECK-NEXT: // kill: def $w0 killed $w0 def $x0
; CHECK-NEXT: sxtw x8, w0
; CHECK-NEXT: mov w8, w0
; CHECK-NEXT: whilels p0.d, xzr, x8
; CHECK-NEXT: lastb d0, p0, z0.d
; CHECK-NEXT: ret
Expand Down Expand Up @@ -518,8 +508,7 @@ define i1 @test_last_8xi1(<vscale x 8 x i1> %a) #0 {
define i1 @test_lanex_4xi1(<vscale x 4 x i1> %a, i32 %x) #0 {
; CHECK-LABEL: test_lanex_4xi1:
; CHECK: // %bb.0:
; CHECK-NEXT: // kill: def $w0 killed $w0 def $x0
; CHECK-NEXT: sxtw x8, w0
; CHECK-NEXT: mov w8, w0
; CHECK-NEXT: mov z0.s, p0/z, #1 // =0x1
; CHECK-NEXT: whilels p0.s, xzr, x8
; CHECK-NEXT: lastb w8, p0, z0.s
Expand Down
21 changes: 7 additions & 14 deletions llvm/test/CodeGen/AArch64/sve-insert-element.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -128,8 +128,7 @@ define <vscale x 16 x i8> @test_lane1_16xi8(<vscale x 16 x i8> %a) {
define <vscale x 16 x i8> @test_lanex_16xi8(<vscale x 16 x i8> %a, i32 %x) {
; CHECK-LABEL: test_lanex_16xi8:
; CHECK: // %bb.0:
; CHECK-NEXT: // kill: def $w0 killed $w0 def $x0
; CHECK-NEXT: sxtw x8, w0
; CHECK-NEXT: mov w8, w0
; CHECK-NEXT: mov w9, #30
; CHECK-NEXT: index z2.b, #0, #1
; CHECK-NEXT: ptrue p0.b
Expand Down Expand Up @@ -389,8 +388,7 @@ define <vscale x 4 x i1> @test_predicate_insert_4xi1_immediate (<vscale x 4 x i1
define <vscale x 8 x i1> @test_predicate_insert_8xi1_immediate (<vscale x 8 x i1> %val, i32 %idx) {
; CHECK-LABEL: test_predicate_insert_8xi1_immediate:
; CHECK: // %bb.0:
; CHECK-NEXT: // kill: def $w0 killed $w0 def $x0
; CHECK-NEXT: sxtw x8, w0
; CHECK-NEXT: mov w8, w0
; CHECK-NEXT: mov w9, #1
; CHECK-NEXT: index z1.h, #0, #1
; CHECK-NEXT: ptrue p1.h
Expand Down Expand Up @@ -427,8 +425,7 @@ define <vscale x 16 x i1> @test_predicate_insert_16xi1_immediate (<vscale x 16 x
define <vscale x 2 x i1> @test_predicate_insert_2xi1(<vscale x 2 x i1> %val, i1 %elt, i32 %idx) {
; CHECK-LABEL: test_predicate_insert_2xi1:
; CHECK: // %bb.0:
; CHECK-NEXT: // kill: def $w1 killed $w1 def $x1
; CHECK-NEXT: sxtw x8, w1
; CHECK-NEXT: mov w8, w1
; CHECK-NEXT: index z1.d, #0, #1
; CHECK-NEXT: ptrue p1.d
; CHECK-NEXT: // kill: def $w0 killed $w0 def $x0
Expand All @@ -446,8 +443,7 @@ define <vscale x 2 x i1> @test_predicate_insert_2xi1(<vscale x 2 x i1> %val, i1
define <vscale x 4 x i1> @test_predicate_insert_4xi1(<vscale x 4 x i1> %val, i1 %elt, i32 %idx) {
; CHECK-LABEL: test_predicate_insert_4xi1:
; CHECK: // %bb.0:
; CHECK-NEXT: // kill: def $w1 killed $w1 def $x1
; CHECK-NEXT: sxtw x8, w1
; CHECK-NEXT: mov w8, w1
; CHECK-NEXT: index z1.s, #0, #1
; CHECK-NEXT: ptrue p1.s
; CHECK-NEXT: mov z0.s, w8
Expand All @@ -463,8 +459,7 @@ define <vscale x 4 x i1> @test_predicate_insert_4xi1(<vscale x 4 x i1> %val, i1
define <vscale x 8 x i1> @test_predicate_insert_8xi1(<vscale x 8 x i1> %val, i1 %elt, i32 %idx) {
; CHECK-LABEL: test_predicate_insert_8xi1:
; CHECK: // %bb.0:
; CHECK-NEXT: // kill: def $w1 killed $w1 def $x1
; CHECK-NEXT: sxtw x8, w1
; CHECK-NEXT: mov w8, w1
; CHECK-NEXT: index z1.h, #0, #1
; CHECK-NEXT: ptrue p1.h
; CHECK-NEXT: mov z0.h, w8
Expand All @@ -481,8 +476,7 @@ define <vscale x 8 x i1> @test_predicate_insert_8xi1(<vscale x 8 x i1> %val, i1
define <vscale x 16 x i1> @test_predicate_insert_16xi1(<vscale x 16 x i1> %val, i1 %elt, i32 %idx) {
; CHECK-LABEL: test_predicate_insert_16xi1:
; CHECK: // %bb.0:
; CHECK-NEXT: // kill: def $w1 killed $w1 def $x1
; CHECK-NEXT: sxtw x8, w1
; CHECK-NEXT: mov w8, w1
; CHECK-NEXT: index z1.b, #0, #1
; CHECK-NEXT: ptrue p1.b
; CHECK-NEXT: mov z0.b, w8
Expand All @@ -505,8 +499,7 @@ define <vscale x 32 x i1> @test_predicate_insert_32xi1(<vscale x 32 x i1> %val,
; CHECK-NEXT: addvl sp, sp, #-2
; CHECK-NEXT: .cfi_escape 0x0f, 0x0c, 0x8f, 0x00, 0x11, 0x10, 0x22, 0x11, 0x10, 0x92, 0x2e, 0x00, 0x1e, 0x22 // sp + 16 + 16 * VG
; CHECK-NEXT: mov x8, #-1
; CHECK-NEXT: // kill: def $w1 killed $w1 def $x1
; CHECK-NEXT: sxtw x9, w1
; CHECK-NEXT: mov w9, w1
; CHECK-NEXT: mov z0.b, p1/z, #1 // =0x1
; CHECK-NEXT: ptrue p1.b
; CHECK-NEXT: st1b { z0.b }, p1, [sp, #1, mul vl]
Expand Down
15 changes: 5 additions & 10 deletions llvm/test/CodeGen/AArch64/sve-split-extract-elt.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -6,8 +6,7 @@
define i32 @promote_extract_2i32_idx(<vscale x 2 x i32> %a, i32 %idx) {
; CHECK-LABEL: promote_extract_2i32_idx:
; CHECK: // %bb.0:
; CHECK-NEXT: // kill: def $w0 killed $w0 def $x0
; CHECK-NEXT: sxtw x8, w0
; CHECK-NEXT: mov w8, w0
; CHECK-NEXT: whilels p0.d, xzr, x8
; CHECK-NEXT: lastb x0, p0, z0.d
; CHECK-NEXT: // kill: def $w0 killed $w0 killed $x0
Expand All @@ -25,8 +24,7 @@ define i8 @split_extract_32i8_idx(<vscale x 32 x i8> %a, i32 %idx) {
; CHECK-NEXT: addvl sp, sp, #-2
; CHECK-NEXT: .cfi_escape 0x0f, 0x0c, 0x8f, 0x00, 0x11, 0x10, 0x22, 0x11, 0x10, 0x92, 0x2e, 0x00, 0x1e, 0x22 // sp + 16 + 16 * VG
; CHECK-NEXT: mov x8, #-1
; CHECK-NEXT: // kill: def $w0 killed $w0 def $x0
; CHECK-NEXT: sxtw x9, w0
; CHECK-NEXT: mov w9, w0
; CHECK-NEXT: ptrue p0.b
; CHECK-NEXT: st1b { z1.b }, p0, [sp, #1, mul vl]
; CHECK-NEXT: st1b { z0.b }, p0, [sp]
Expand All @@ -51,8 +49,7 @@ define i16 @split_extract_16i16_idx(<vscale x 16 x i16> %a, i32 %idx) {
; CHECK-NEXT: addvl sp, sp, #-2
; CHECK-NEXT: .cfi_escape 0x0f, 0x0c, 0x8f, 0x00, 0x11, 0x10, 0x22, 0x11, 0x10, 0x92, 0x2e, 0x00, 0x1e, 0x22 // sp + 16 + 16 * VG
; CHECK-NEXT: mov x8, #-1
; CHECK-NEXT: // kill: def $w0 killed $w0 def $x0
; CHECK-NEXT: sxtw x9, w0
; CHECK-NEXT: mov w9, w0
; CHECK-NEXT: ptrue p0.h
; CHECK-NEXT: st1h { z1.h }, p0, [sp, #1, mul vl]
; CHECK-NEXT: st1h { z0.h }, p0, [sp]
Expand All @@ -77,8 +74,7 @@ define i32 @split_extract_8i32_idx(<vscale x 8 x i32> %a, i32 %idx) {
; CHECK-NEXT: addvl sp, sp, #-2
; CHECK-NEXT: .cfi_escape 0x0f, 0x0c, 0x8f, 0x00, 0x11, 0x10, 0x22, 0x11, 0x10, 0x92, 0x2e, 0x00, 0x1e, 0x22 // sp + 16 + 16 * VG
; CHECK-NEXT: cnth x8
; CHECK-NEXT: // kill: def $w0 killed $w0 def $x0
; CHECK-NEXT: sxtw x9, w0
; CHECK-NEXT: mov w9, w0
; CHECK-NEXT: sub x8, x8, #1
; CHECK-NEXT: ptrue p0.s
; CHECK-NEXT: cmp x9, x8
Expand All @@ -103,8 +99,7 @@ define i64 @split_extract_8i64_idx(<vscale x 8 x i64> %a, i32 %idx) {
; CHECK-NEXT: addvl sp, sp, #-4
; CHECK-NEXT: .cfi_escape 0x0f, 0x0c, 0x8f, 0x00, 0x11, 0x10, 0x22, 0x11, 0x20, 0x92, 0x2e, 0x00, 0x1e, 0x22 // sp + 16 + 32 * VG
; CHECK-NEXT: cnth x8
; CHECK-NEXT: // kill: def $w0 killed $w0 def $x0
; CHECK-NEXT: sxtw x9, w0
; CHECK-NEXT: mov w9, w0
; CHECK-NEXT: sub x8, x8, #1
; CHECK-NEXT: ptrue p0.d
; CHECK-NEXT: cmp x9, x8
Expand Down
28 changes: 28 additions & 0 deletions llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-zext-vec-index.ll
View file
Original file line number Diff line number Diff line change
@@ -0,0 +1,28 @@
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
; RUN: llc -march=amdgcn -O0 -stop-after=irtranslator -global-isel -verify-machineinstrs %s -o - | FileCheck %s

define i8 @f_i1_1() {
; CHECK-LABEL: name: f_i1_1
; CHECK: bb.1 (%ir-block.0):
; CHECK-NEXT: [[DEF:%[0-9]+]]:_(<256 x s8>) = G_IMPLICIT_DEF
; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
; CHECK-NEXT: [[EVEC:%[0-9]+]]:_(s8) = G_EXTRACT_VECTOR_ELT [[DEF]](<256 x s8>), [[C]](s32)
; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[EVEC]](s8)
; CHECK-NEXT: $vgpr0 = COPY [[ANYEXT]](s32)
; CHECK-NEXT: SI_RETURN implicit $vgpr0
%E1 = extractelement <256 x i8> undef, i1 true
ret i8 %E1
}

define i8 @f_i8_255() {
; CHECK-LABEL: name: f_i8_255
; CHECK: bb.1 (%ir-block.0):
; CHECK-NEXT: [[DEF:%[0-9]+]]:_(<256 x s8>) = G_IMPLICIT_DEF
; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
; CHECK-NEXT: [[EVEC:%[0-9]+]]:_(s8) = G_EXTRACT_VECTOR_ELT [[DEF]](<256 x s8>), [[C]](s32)
; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[EVEC]](s8)
; CHECK-NEXT: $vgpr0 = COPY [[ANYEXT]](s32)
; CHECK-NEXT: SI_RETURN implicit $vgpr0
%E1 = extractelement <256 x i8> undef, i8 255
ret i8 %E1
}
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