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ChuongGoh-armChuongGoh-arm
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[AArch64][GlobalISel] Enable computeNumSignBits for G_XOR, G_AND, G_OR (#89896)
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‎llvm/lib/CodeGen/GlobalISel/GISelKnownBits.cpp‎

Lines changed: 14 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -694,6 +694,20 @@ unsigned GISelKnownBits::computeNumSignBits(Register R,
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const MachineMemOperand *MMO = *MI.memoperands_begin();
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return TyBits - MMO->getSizeInBits().getValue();
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}
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case TargetOpcode::G_AND:
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case TargetOpcode::G_OR:
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case TargetOpcode::G_XOR: {
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Register Src1 = MI.getOperand(1).getReg();
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unsigned Src1NumSignBits =
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computeNumSignBits(Src1, DemandedElts, Depth + 1);
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if (Src1NumSignBits != 1) {
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Register Src2 = MI.getOperand(2).getReg();
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unsigned Src2NumSignBits =
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computeNumSignBits(Src2, DemandedElts, Depth + 1);
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FirstAnswer = std::min(Src1NumSignBits, Src2NumSignBits);
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}
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break;
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}
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case TargetOpcode::G_TRUNC: {
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Register Src = MI.getOperand(1).getReg();
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LLT SrcTy = MRI.getType(Src);

‎llvm/unittests/CodeGen/GlobalISel/KnownBitsTest.cpp‎

Lines changed: 114 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -745,6 +745,120 @@ TEST_F(AArch64GISelMITest, TestNumSignBitsConstant) {
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EXPECT_EQ(3u, Info.computeNumSignBits(CopyRegNeg32));
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}
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TEST_F(AArch64GISelMITest, TestNumSignBitsXOR) {
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StringRef MIRString = " %c1:_(s8) = G_CONSTANT i8 1\n"
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" %cn1:_(s8) = G_CONSTANT i8 -1\n"
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" %c127:_(s8) = G_CONSTANT i8 127\n"
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" %c32:_(s8) = G_CONSTANT i8 32\n"
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" %cn32:_(s8) = G_CONSTANT i8 -32\n"
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" %xor1:_(s8) = G_XOR %c1, %cn1\n"
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" %Copy1:_(s8) = COPY %xor1\n"
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" %xor2:_(s8) = G_XOR %c1, %c32\n"
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" %Copy2:_(s8) = COPY %xor2\n"
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" %xor3:_(s8) = G_XOR %c32, %c127\n"
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" %Copy3:_(s8) = COPY %xor3\n"
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" %xor4:_(s8) = G_XOR %cn32, %c127\n"
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" %Copy4:_(s8) = COPY %xor4\n"
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" %xor5:_(s8) = G_XOR %c127, %cn32\n"
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" %Copy5:_(s8) = COPY %xor5\n";
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setUp(MIRString);
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if (!TM)
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GTEST_SKIP();
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Register Copy1 = Copies[Copies.size() - 5];
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Register Copy2 = Copies[Copies.size() - 4];
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Register Copy3 = Copies[Copies.size() - 3];
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Register Copy4 = Copies[Copies.size() - 2];
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Register Copy5 = Copies[Copies.size() - 1];
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GISelKnownBits Info(*MF);
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EXPECT_EQ(7u, Info.computeNumSignBits(Copy1));
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EXPECT_EQ(2u, Info.computeNumSignBits(Copy2));
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EXPECT_EQ(1u, Info.computeNumSignBits(Copy3));
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EXPECT_EQ(1u, Info.computeNumSignBits(Copy4));
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EXPECT_EQ(1u, Info.computeNumSignBits(Copy5));
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}
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TEST_F(AArch64GISelMITest, TestNumSignBitsOR) {
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StringRef MIRString = " %c1:_(s8) = G_CONSTANT i8 1\n"
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" %cn1:_(s8) = G_CONSTANT i8 -1\n"
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" %c127:_(s8) = G_CONSTANT i8 127\n"
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" %c32:_(s8) = G_CONSTANT i8 32\n"
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" %cn32:_(s8) = G_CONSTANT i8 -32\n"
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" %or1:_(s8) = G_OR %c1, %cn1\n"
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" %Copy1:_(s8) = COPY %or1\n"
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" %or2:_(s8) = G_OR %c1, %c32\n"
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" %Copy2:_(s8) = COPY %or2\n"
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" %or3:_(s8) = G_OR %c32, %c127\n"
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" %Copy3:_(s8) = COPY %or3\n"
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" %or4:_(s8) = G_OR %cn32, %c127\n"
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" %Copy4:_(s8) = COPY %or4\n"
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" %or5:_(s8) = G_OR %c127, %cn32\n"
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" %Copy5:_(s8) = COPY %or5\n";
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setUp(MIRString);
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if (!TM)
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GTEST_SKIP();
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Register Copy1 = Copies[Copies.size() - 5];
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Register Copy2 = Copies[Copies.size() - 4];
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Register Copy3 = Copies[Copies.size() - 3];
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Register Copy4 = Copies[Copies.size() - 2];
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Register Copy5 = Copies[Copies.size() - 1];
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GISelKnownBits Info(*MF);
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EXPECT_EQ(8u, Info.computeNumSignBits(Copy1));
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EXPECT_EQ(2u, Info.computeNumSignBits(Copy2));
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EXPECT_EQ(1u, Info.computeNumSignBits(Copy3));
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EXPECT_EQ(8u, Info.computeNumSignBits(Copy4));
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EXPECT_EQ(8u, Info.computeNumSignBits(Copy5));
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}
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TEST_F(AArch64GISelMITest, TestNumSignBitsAND) {
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StringRef MIRString = " %c1:_(s8) = G_CONSTANT i8 1\n"
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" %cn1:_(s8) = G_CONSTANT i8 -1\n"
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" %c127:_(s8) = G_CONSTANT i8 127\n"
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" %c32:_(s8) = G_CONSTANT i8 32\n"
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" %cn32:_(s8) = G_CONSTANT i8 -32\n"
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" %and1:_(s8) = G_AND %c1, %cn1\n"
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" %Copy1:_(s8) = COPY %and1\n"
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" %and2:_(s8) = G_AND %c1, %c32\n"
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" %Copy2:_(s8) = COPY %and2\n"
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" %and3:_(s8) = G_AND %c32, %c127\n"
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" %Copy3:_(s8) = COPY %and3\n"
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" %and4:_(s8) = G_AND %cn32, %c127\n"
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" %Copy4:_(s8) = COPY %and4\n"
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" %and5:_(s8) = G_AND %c127, %cn32\n"
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" %Copy5:_(s8) = COPY %and5\n";
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setUp(MIRString);
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if (!TM)
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GTEST_SKIP();
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Register Copy1 = Copies[Copies.size() - 5];
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Register Copy2 = Copies[Copies.size() - 4];
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Register Copy3 = Copies[Copies.size() - 3];
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Register Copy4 = Copies[Copies.size() - 2];
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Register Copy5 = Copies[Copies.size() - 1];
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GISelKnownBits Info(*MF);
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EXPECT_EQ(7u, Info.computeNumSignBits(Copy1));
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EXPECT_EQ(8u, Info.computeNumSignBits(Copy2));
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EXPECT_EQ(2u, Info.computeNumSignBits(Copy3));
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EXPECT_EQ(1u, Info.computeNumSignBits(Copy4));
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EXPECT_EQ(1u, Info.computeNumSignBits(Copy5));
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}
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TEST_F(AArch64GISelMITest, TestNumSignBitsSext) {
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StringRef MIRString = " %3:_(p0) = G_IMPLICIT_DEF\n"
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" %4:_(s8) = G_LOAD %3 :: (load (s8))\n"

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