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[RISCV] Add more instructions for the short forward branch optimization. (#66789)
This adds the shifts and the immediate forms of the instructions that were already supported. There are still more instructions that can be predicated, but this is the rest of what we had in our downstream.
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4 files changed

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‎llvm/lib/Target/RISCV/RISCVExpandPseudoInsts.cpp

Lines changed: 34 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -119,6 +119,23 @@ bool RISCVExpandPseudo::expandMI(MachineBasicBlock &MBB,
119119
case RISCV::PseudoCCXOR:
120120
case RISCV::PseudoCCADDW:
121121
case RISCV::PseudoCCSUBW:
122+
case RISCV::PseudoCCSLL:
123+
case RISCV::PseudoCCSRL:
124+
case RISCV::PseudoCCSRA:
125+
case RISCV::PseudoCCADDI:
126+
case RISCV::PseudoCCSLLI:
127+
case RISCV::PseudoCCSRLI:
128+
case RISCV::PseudoCCSRAI:
129+
case RISCV::PseudoCCANDI:
130+
case RISCV::PseudoCCORI:
131+
case RISCV::PseudoCCXORI:
132+
case RISCV::PseudoCCSLLW:
133+
case RISCV::PseudoCCSRLW:
134+
case RISCV::PseudoCCSRAW:
135+
case RISCV::PseudoCCADDIW:
136+
case RISCV::PseudoCCSLLIW:
137+
case RISCV::PseudoCCSRLIW:
138+
case RISCV::PseudoCCSRAIW:
122139
return expandCCOp(MBB, MBBI, NextMBBI);
123140
case RISCV::PseudoVSETVLI:
124141
case RISCV::PseudoVSETVLIX0:
@@ -188,11 +205,28 @@ bool RISCVExpandPseudo::expandCCOp(MachineBasicBlock &MBB,
188205
llvm_unreachable("Unexpected opcode!");
189206
case RISCV::PseudoCCADD: NewOpc = RISCV::ADD; break;
190207
case RISCV::PseudoCCSUB: NewOpc = RISCV::SUB; break;
208+
case RISCV::PseudoCCSLL: NewOpc = RISCV::SLL; break;
209+
case RISCV::PseudoCCSRL: NewOpc = RISCV::SRL; break;
210+
case RISCV::PseudoCCSRA: NewOpc = RISCV::SRA; break;
191211
case RISCV::PseudoCCAND: NewOpc = RISCV::AND; break;
192212
case RISCV::PseudoCCOR: NewOpc = RISCV::OR; break;
193213
case RISCV::PseudoCCXOR: NewOpc = RISCV::XOR; break;
214+
case RISCV::PseudoCCADDI: NewOpc = RISCV::ADDI; break;
215+
case RISCV::PseudoCCSLLI: NewOpc = RISCV::SLLI; break;
216+
case RISCV::PseudoCCSRLI: NewOpc = RISCV::SRLI; break;
217+
case RISCV::PseudoCCSRAI: NewOpc = RISCV::SRAI; break;
218+
case RISCV::PseudoCCANDI: NewOpc = RISCV::ANDI; break;
219+
case RISCV::PseudoCCORI: NewOpc = RISCV::ORI; break;
220+
case RISCV::PseudoCCXORI: NewOpc = RISCV::XORI; break;
194221
case RISCV::PseudoCCADDW: NewOpc = RISCV::ADDW; break;
195222
case RISCV::PseudoCCSUBW: NewOpc = RISCV::SUBW; break;
223+
case RISCV::PseudoCCSLLW: NewOpc = RISCV::SLLW; break;
224+
case RISCV::PseudoCCSRLW: NewOpc = RISCV::SRLW; break;
225+
case RISCV::PseudoCCSRAW: NewOpc = RISCV::SRAW; break;
226+
case RISCV::PseudoCCADDIW: NewOpc = RISCV::ADDIW; break;
227+
case RISCV::PseudoCCSLLIW: NewOpc = RISCV::SLLIW; break;
228+
case RISCV::PseudoCCSRLIW: NewOpc = RISCV::SRLIW; break;
229+
case RISCV::PseudoCCSRAIW: NewOpc = RISCV::SRAIW; break;
196230
}
197231
BuildMI(TrueBB, DL, TII->get(NewOpc), DestReg)
198232
.add(MI.getOperand(5))

‎llvm/lib/Target/RISCV/RISCVInstrInfo.cpp

Lines changed: 23 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1106,12 +1106,31 @@ unsigned getPredicatedOpcode(unsigned Opcode) {
11061106
switch (Opcode) {
11071107
case RISCV::ADD: return RISCV::PseudoCCADD; break;
11081108
case RISCV::SUB: return RISCV::PseudoCCSUB; break;
1109+
case RISCV::SLL: return RISCV::PseudoCCSLL; break;
1110+
case RISCV::SRL: return RISCV::PseudoCCSRL; break;
1111+
case RISCV::SRA: return RISCV::PseudoCCSRA; break;
11091112
case RISCV::AND: return RISCV::PseudoCCAND; break;
11101113
case RISCV::OR: return RISCV::PseudoCCOR; break;
11111114
case RISCV::XOR: return RISCV::PseudoCCXOR; break;
11121115

1116+
case RISCV::ADDI: return RISCV::PseudoCCADDI; break;
1117+
case RISCV::SLLI: return RISCV::PseudoCCSLLI; break;
1118+
case RISCV::SRLI: return RISCV::PseudoCCSRLI; break;
1119+
case RISCV::SRAI: return RISCV::PseudoCCSRAI; break;
1120+
case RISCV::ANDI: return RISCV::PseudoCCANDI; break;
1121+
case RISCV::ORI: return RISCV::PseudoCCORI; break;
1122+
case RISCV::XORI: return RISCV::PseudoCCXORI; break;
1123+
11131124
case RISCV::ADDW: return RISCV::PseudoCCADDW; break;
11141125
case RISCV::SUBW: return RISCV::PseudoCCSUBW; break;
1126+
case RISCV::SLLW: return RISCV::PseudoCCSLLW; break;
1127+
case RISCV::SRLW: return RISCV::PseudoCCSRLW; break;
1128+
case RISCV::SRAW: return RISCV::PseudoCCSRAW; break;
1129+
1130+
case RISCV::ADDIW: return RISCV::PseudoCCADDIW; break;
1131+
case RISCV::SLLIW: return RISCV::PseudoCCSLLIW; break;
1132+
case RISCV::SRLIW: return RISCV::PseudoCCSRLIW; break;
1133+
case RISCV::SRAIW: return RISCV::PseudoCCSRAIW; break;
11151134
}
11161135

11171136
return RISCV::INSTRUCTION_LIST_END;
@@ -1132,6 +1151,10 @@ static MachineInstr *canFoldAsPredicatedOp(Register Reg,
11321151
// Check if MI can be predicated and folded into the CCMOV.
11331152
if (getPredicatedOpcode(MI->getOpcode()) == RISCV::INSTRUCTION_LIST_END)
11341153
return nullptr;
1154+
// Don't predicate li idiom.
1155+
if (MI->getOpcode() == RISCV::ADDI && MI->getOperand(1).isReg() &&
1156+
MI->getOperand(1).getReg() == RISCV::X0)
1157+
return nullptr;
11351158
// Check if MI has any other defs or physreg uses.
11361159
for (const MachineOperand &MO : llvm::drop_begin(MI->operands())) {
11371160
// Reject frame index operands, PEI can't handle the predicated pseudos.

‎llvm/lib/Target/RISCV/RISCVInstrInfo.td

Lines changed: 87 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1438,6 +1438,21 @@ def PseudoCCSUB : Pseudo<(outs GPR:$dst),
14381438
GPR:$falsev, GPR:$rs1, GPR:$rs2), []>,
14391439
Sched<[WriteSFB, ReadSFBJmp, ReadSFBJmp,
14401440
ReadSFBALU, ReadSFBALU, ReadSFBALU]>;
1441+
def PseudoCCSLL : Pseudo<(outs GPR:$dst),
1442+
(ins GPR:$lhs, GPR:$rhs, ixlenimm:$cc,
1443+
GPR:$falsev, GPR:$rs1, GPR:$rs2), []>,
1444+
Sched<[WriteSFB, ReadSFBJmp, ReadSFBJmp, ReadSFBALU,
1445+
ReadSFBALU, ReadSFBALU]>;
1446+
def PseudoCCSRL : Pseudo<(outs GPR:$dst),
1447+
(ins GPR:$lhs, GPR:$rhs, ixlenimm:$cc,
1448+
GPR:$falsev, GPR:$rs1, GPR:$rs2), []>,
1449+
Sched<[WriteSFB, ReadSFBJmp, ReadSFBJmp, ReadSFBALU,
1450+
ReadSFBALU, ReadSFBALU]>;
1451+
def PseudoCCSRA : Pseudo<(outs GPR:$dst),
1452+
(ins GPR:$lhs, GPR:$rhs, ixlenimm:$cc,
1453+
GPR:$falsev, GPR:$rs1, GPR:$rs2), []>,
1454+
Sched<[WriteSFB, ReadSFBJmp, ReadSFBJmp, ReadSFBALU,
1455+
ReadSFBALU, ReadSFBALU]>;
14411456
def PseudoCCAND : Pseudo<(outs GPR:$dst),
14421457
(ins GPR:$lhs, GPR:$rhs, ixlenimm:$cc,
14431458
GPR:$falsev, GPR:$rs1, GPR:$rs2), []>,
@@ -1454,6 +1469,42 @@ def PseudoCCXOR : Pseudo<(outs GPR:$dst),
14541469
Sched<[WriteSFB, ReadSFBJmp, ReadSFBJmp,
14551470
ReadSFBALU, ReadSFBALU, ReadSFBALU]>;
14561471

1472+
def PseudoCCADDI : Pseudo<(outs GPR:$dst),
1473+
(ins GPR:$lhs, GPR:$rhs, ixlenimm:$cc,
1474+
GPR:$falsev, GPR:$rs1, simm12:$rs2), []>,
1475+
Sched<[WriteSFB, ReadSFBJmp, ReadSFBJmp, ReadSFBALU,
1476+
ReadSFBALU]>;
1477+
def PseudoCCSLLI : Pseudo<(outs GPR:$dst),
1478+
(ins GPR:$lhs, GPR:$rhs, ixlenimm:$cc,
1479+
GPR:$falsev, GPR:$rs1, simm12:$rs2), []>,
1480+
Sched<[WriteSFB, ReadSFBJmp, ReadSFBJmp, ReadSFBALU,
1481+
ReadSFBALU]>;
1482+
def PseudoCCSRLI : Pseudo<(outs GPR:$dst),
1483+
(ins GPR:$lhs, GPR:$rhs, ixlenimm:$cc,
1484+
GPR:$falsev, GPR:$rs1, simm12:$rs2), []>,
1485+
Sched<[WriteSFB, ReadSFBJmp, ReadSFBJmp, ReadSFBALU,
1486+
ReadSFBALU]>;
1487+
def PseudoCCSRAI : Pseudo<(outs GPR:$dst),
1488+
(ins GPR:$lhs, GPR:$rhs, ixlenimm:$cc,
1489+
GPR:$falsev, GPR:$rs1, simm12:$rs2), []>,
1490+
Sched<[WriteSFB, ReadSFBJmp, ReadSFBJmp, ReadSFBALU,
1491+
ReadSFBALU]>;
1492+
def PseudoCCANDI : Pseudo<(outs GPR:$dst),
1493+
(ins GPR:$lhs, GPR:$rhs, ixlenimm:$cc,
1494+
GPR:$falsev, GPR:$rs1, simm12:$rs2), []>,
1495+
Sched<[WriteSFB, ReadSFBJmp, ReadSFBJmp, ReadSFBALU,
1496+
ReadSFBALU]>;
1497+
def PseudoCCORI : Pseudo<(outs GPR:$dst),
1498+
(ins GPR:$lhs, GPR:$rhs, ixlenimm:$cc,
1499+
GPR:$falsev, GPR:$rs1, simm12:$rs2), []>,
1500+
Sched<[WriteSFB, ReadSFBJmp, ReadSFBJmp, ReadSFBALU,
1501+
ReadSFBALU]>;
1502+
def PseudoCCXORI : Pseudo<(outs GPR:$dst),
1503+
(ins GPR:$lhs, GPR:$rhs, ixlenimm:$cc,
1504+
GPR:$falsev, GPR:$rs1, simm12:$rs2), []>,
1505+
Sched<[WriteSFB, ReadSFBJmp, ReadSFBJmp, ReadSFBALU,
1506+
ReadSFBALU]>;
1507+
14571508
// RV64I instructions
14581509
def PseudoCCADDW : Pseudo<(outs GPR:$dst),
14591510
(ins GPR:$lhs, GPR:$rhs, ixlenimm:$cc,
@@ -1465,6 +1516,42 @@ def PseudoCCSUBW : Pseudo<(outs GPR:$dst),
14651516
GPR:$falsev, GPR:$rs1, GPR:$rs2), []>,
14661517
Sched<[WriteSFB, ReadSFBJmp, ReadSFBJmp,
14671518
ReadSFBALU, ReadSFBALU, ReadSFBALU]>;
1519+
def PseudoCCSLLW : Pseudo<(outs GPR:$dst),
1520+
(ins GPR:$lhs, GPR:$rhs, ixlenimm:$cc,
1521+
GPR:$falsev, GPR:$rs1, GPR:$rs2), []>,
1522+
Sched<[WriteSFB, ReadSFBJmp, ReadSFBJmp, ReadSFBALU,
1523+
ReadSFBALU, ReadSFBALU]>;
1524+
def PseudoCCSRLW : Pseudo<(outs GPR:$dst),
1525+
(ins GPR:$lhs, GPR:$rhs, ixlenimm:$cc,
1526+
GPR:$falsev, GPR:$rs1, GPR:$rs2), []>,
1527+
Sched<[WriteSFB, ReadSFBJmp, ReadSFBJmp, ReadSFBALU,
1528+
ReadSFBALU, ReadSFBALU]>;
1529+
def PseudoCCSRAW : Pseudo<(outs GPR:$dst),
1530+
(ins GPR:$lhs, GPR:$rhs, ixlenimm:$cc,
1531+
GPR:$falsev, GPR:$rs1, GPR:$rs2), []>,
1532+
Sched<[WriteSFB, ReadSFBJmp, ReadSFBJmp, ReadSFBALU,
1533+
ReadSFBALU, ReadSFBALU]>;
1534+
1535+
def PseudoCCADDIW : Pseudo<(outs GPR:$dst),
1536+
(ins GPR:$lhs, GPR:$rhs, ixlenimm:$cc,
1537+
GPR:$falsev, GPR:$rs1, simm12:$rs2), []>,
1538+
Sched<[WriteSFB, ReadSFBJmp, ReadSFBJmp, ReadSFBALU,
1539+
ReadSFBALU]>;
1540+
def PseudoCCSLLIW : Pseudo<(outs GPR:$dst),
1541+
(ins GPR:$lhs, GPR:$rhs, ixlenimm:$cc,
1542+
GPR:$falsev, GPR:$rs1, simm12:$rs2), []>,
1543+
Sched<[WriteSFB, ReadSFBJmp, ReadSFBJmp, ReadSFBALU,
1544+
ReadSFBALU]>;
1545+
def PseudoCCSRLIW : Pseudo<(outs GPR:$dst),
1546+
(ins GPR:$lhs, GPR:$rhs, ixlenimm:$cc,
1547+
GPR:$falsev, GPR:$rs1, simm12:$rs2), []>,
1548+
Sched<[WriteSFB, ReadSFBJmp, ReadSFBJmp, ReadSFBALU,
1549+
ReadSFBALU]>;
1550+
def PseudoCCSRAIW : Pseudo<(outs GPR:$dst),
1551+
(ins GPR:$lhs, GPR:$rhs, ixlenimm:$cc,
1552+
GPR:$falsev, GPR:$rs1, simm12:$rs2), []>,
1553+
Sched<[WriteSFB, ReadSFBJmp, ReadSFBJmp, ReadSFBALU,
1554+
ReadSFBALU]>;
14681555
}
14691556

14701557
multiclass SelectCC_GPR_rrirr<DAGOperand valty, ValueType vt> {

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