[LiveVariables] Mark use as implicit-def if def is a subregister

LiveVariables will mark instructions with their implicit subregister
uses. However, it will miss marking the subregister as an implicit-def
if its own definition is a subregister of it, i.e.
`$r3 = OP val, implicit-def $r0_r1_r2_r3, ..., implicit $r2_r3`,
which defines $sr3 on the same line it is used.

This change ensures such uses are marked as implicit-def, i.e.
`$r3 = OP val, implicit-def $r0_r1_r2_r3, ..., implicit-def $r2_r3`.

Author: jofrn

llvm/lib/CodeGen/LiveVariables.cpp

@@ -277,11 +277,22 @@ void LiveVariables::HandlePhysRegUse(Register Reg, MachineInstr &MI) {
           continue;
         if (PartDefRegs.count(SubReg))
           continue;
+
+        // Check if SubReg is defined at LastPartialDef.
+        bool IsDefinedHere = false;
+        for (int I = 0; I < LastPartialDef->getNumOperands(); ++I) {
+          const auto MO = LastPartialDef->getOperand(I);
+          if (!MO.isReg() || !MO.isDef())
+            continue;
+          if (TRI->isSubRegister(SubReg, MO.getReg())) {
+            IsDefinedHere = true;
+            break;
+          }
+        }
         // This part of Reg was defined before the last partial def. It's killed
         // here.
-        LastPartialDef->addOperand(MachineOperand::CreateReg(SubReg,
-                                                             false/*IsDef*/,
-                                                             true/*IsImp*/));
+        LastPartialDef->addOperand(
+            MachineOperand::CreateReg(SubReg, IsDefinedHere, true /*IsImp*/));
         PhysRegDef[SubReg] = LastPartialDef;
         for (MCPhysReg SS : TRI->subregs(SubReg))
           Processed.insert(SS);

llvm/test/CodeGen/AMDGPU/implicitdef-subreg.mir

@@ -0,0 +1,44 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5
+# RUN: llc -mtriple=amdgcn --run-pass=livevars -o - %s | FileCheck %s
+---
+name:            sgpr_copy
+tracksRegLiveness: true
+body:             |
+  bb.0:
+    ; CHECK-LABEL: name: sgpr_copy
+    ; CHECK: %sval:sreg_32 = S_MOV_B32 0
+    ; CHECK-NEXT: $sgpr0 = COPY %sval
+    ; CHECK-NEXT: $sgpr1 = COPY %sval
+    ; CHECK-NEXT: $sgpr2 = COPY %sval
+    ; CHECK-NEXT: $sgpr3 = COPY killed %sval, implicit-def $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr0, implicit $sgpr1, implicit $sgpr2, implicit $sgpr0_sgpr1, implicit $sgpr0_sgpr1_sgpr2, implicit-def $sgpr2_sgpr3
+    ; CHECK-NEXT: dead $sgpr30_sgpr31 = COPY killed $sgpr0_sgpr1_sgpr2_sgpr3
+    %sval:sreg_32 = S_MOV_B32 0
+
+    $sgpr0 = COPY %sval
+    $sgpr1 = COPY %sval
+    $sgpr2 = COPY %sval
+    $sgpr3 = COPY %sval
+    $sgpr30_sgpr31 = COPY $sgpr0_sgpr1_sgpr2_sgpr3
+
+...
+---
+name:            vgpr_copy
+tracksRegLiveness: true
+body:             |
+  bb.0:
+    ; CHECK-LABEL: name: vgpr_copy
+    ; CHECK: %sval:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
+    ; CHECK-NEXT: $vgpr0 = COPY %sval
+    ; CHECK-NEXT: $vgpr1 = COPY %sval
+    ; CHECK-NEXT: $vgpr2 = COPY %sval
+    ; CHECK-NEXT: $vgpr3 = COPY killed %sval, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3, implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr0_vgpr1, implicit $vgpr0_vgpr1_vgpr2, implicit-def $vgpr1_vgpr2_vgpr3
+    ; CHECK-NEXT: dead [[COPY:%[0-9]+]]:vgpr_32 = COPY killed $vgpr0_vgpr1_vgpr2_vgpr3
+    %sval:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
+
+    $vgpr0 = COPY %sval
+    $vgpr1 = COPY %sval
+    $vgpr2 = COPY %sval
+    $vgpr3 = COPY %sval
+    %0:vgpr_32 = COPY $vgpr0_vgpr1_vgpr2_vgpr3
+
+...