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[AArch64] Fix an incorrect handling of debug values in MachineSink (#68107)
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2 files changed

+137
-2
lines changed

2 files changed

+137
-2
lines changed

llvm/lib/CodeGen/MachineSink.cpp

Lines changed: 4 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -528,7 +528,10 @@ bool MachineSinking::PerformSinkAndFold(MachineInstr &MI,
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continue;
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MachineInstr *NewDbgMI = SinkDst->getMF()->CloneMachineInstr(DbgMI);
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SinkMBB.insertAfter(InsertPt, NewDbgMI);
531-
NewDbgMI->getOperand(0).setReg(DstReg);
531+
for (auto &SrcMO : DbgMI->getDebugOperandsForReg(DefReg)) {
532+
auto &DstMO = NewDbgMI->getOperand(SrcMO.getOperandNo());
533+
DstMO.setReg(DstReg);
534+
}
532535
}
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} else {
534537
// Fold instruction into the addressing mode of a memory instruction.

llvm/test/CodeGen/AArch64/sink-and-fold-dbg-value-crash.mir

Lines changed: 133 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -26,7 +26,16 @@
2626
ret void
2727
}
2828

29-
declare ptr @g(ptr)
29+
define ptr @g(ptr) {
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entry:
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br label %if.then
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if.then:
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br label %if.end
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if.end:
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br label %exit
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exit:
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ret ptr null
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}
3039

3140
declare void @llvm.dbg.value(metadata, metadata, metadata) #0
3241

@@ -170,3 +179,126 @@ body: |
170179
RET_ReallyLR
171180
172181
...
182+
---
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name: g
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alignment: 4
185+
exposesReturnsTwice: false
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legalized: false
187+
regBankSelected: false
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selected: false
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failedISel: false
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tracksRegLiveness: true
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hasWinCFI: false
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callsEHReturn: false
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callsUnwindInit: false
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hasEHCatchret: false
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hasEHScopes: false
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hasEHFunclets: false
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isOutlined: false
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debugInstrRef: false
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failsVerification: false
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tracksDebugUserValues: false
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registers:
202+
- { id: 0, class: gpr64all, preferred-register: '' }
203+
- { id: 1, class: gpr64common, preferred-register: '' }
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- { id: 2, class: gpr32, preferred-register: '' }
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- { id: 3, class: gpr32, preferred-register: '' }
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- { id: 4, class: gpr32, preferred-register: '' }
207+
- { id: 5, class: gpr64sp, preferred-register: '' }
208+
- { id: 6, class: gpr64all, preferred-register: '' }
209+
liveins:
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- { reg: '$x0', virtual-reg: '%1' }
211+
- { reg: '$w1', virtual-reg: '%2' }
212+
- { reg: '$w2', virtual-reg: '%3' }
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frameInfo:
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isFrameAddressTaken: false
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isReturnAddressTaken: false
216+
hasStackMap: false
217+
hasPatchPoint: false
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stackSize: 0
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offsetAdjustment: 0
220+
maxAlignment: 1
221+
adjustsStack: true
222+
hasCalls: true
223+
stackProtector: ''
224+
functionContext: ''
225+
maxCallFrameSize: 0
226+
cvBytesOfCalleeSavedRegisters: 0
227+
hasOpaqueSPAdjustment: false
228+
hasVAStart: false
229+
hasMustTailInVarArgFunc: false
230+
hasTailCall: false
231+
localFrameSize: 0
232+
savePoint: ''
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restorePoint: ''
234+
fixedStack: []
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stack: []
236+
entry_values: []
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callSites: []
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debugValueSubstitutions: []
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constants: []
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machineFunctionInfo: {}
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body: |
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; CHECK-LABEL: name: g
243+
; CHECK: bb.0.entry:
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; CHECK-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000)
245+
; CHECK-NEXT: liveins: $x0, $w1, $w2
246+
; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY $w2
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; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr32 = COPY $w1
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; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr64common = COPY $x0
250+
; CHECK-NEXT: DBG_VALUE_LIST !4, !DIExpression(), [[COPY]], $noreg, debug-location !10
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; CHECK-NEXT: TBZW [[COPY1]], 0, %bb.2
252+
; CHECK-NEXT: B %bb.1
253+
; CHECK-NEXT: {{ $}}
254+
; CHECK-NEXT: bb.1.if.then:
255+
; CHECK-NEXT: successors: %bb.3(0x40000000), %bb.2(0x40000000)
256+
; CHECK-NEXT: {{ $}}
257+
; CHECK-NEXT: [[COPY3:%[0-9]+]]:gpr32 = COPY [[COPY]]
258+
; CHECK-NEXT: DBG_VALUE_LIST !4, !DIExpression(), [[COPY3]], $noreg, debug-location !10
259+
; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def dead $sp, implicit $sp
260+
; CHECK-NEXT: $x0 = ADDXri [[COPY2]], 8, 0
261+
; CHECK-NEXT: DBG_VALUE_LIST !4, !DIExpression(), [[COPY3]], $x0, debug-location !10
262+
; CHECK-NEXT: BL @g, csr_aarch64_aapcs, implicit-def dead $lr, implicit $sp, implicit $x0, implicit-def $sp, implicit-def $x0
263+
; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def dead $sp, implicit $sp
264+
; CHECK-NEXT: TBNZW [[COPY3]], 0, %bb.3
265+
; CHECK-NEXT: B %bb.2
266+
; CHECK-NEXT: {{ $}}
267+
; CHECK-NEXT: bb.2.if.end:
268+
; CHECK-NEXT: successors: %bb.3(0x80000000)
269+
; CHECK-NEXT: {{ $}}
270+
; CHECK-NEXT: {{ $}}
271+
; CHECK-NEXT: bb.3.exit:
272+
; CHECK-NEXT: RET_ReallyLR
273+
bb.0.entry:
274+
successors: %bb.1(0x40000000), %bb.2(0x40000000)
275+
liveins: $x0, $w1, $w2
276+
277+
%3:gpr32 = COPY $w2
278+
%2:gpr32 = COPY $w1
279+
%1:gpr64common = COPY $x0
280+
%4:gpr32 = COPY %3
281+
%5:gpr64sp = ADDXri %1, 8, 0
282+
DBG_VALUE_LIST !4, !DIExpression(), %4:gpr32, %5:gpr64sp, debug-location !10
283+
%0:gpr64all = COPY %5
284+
TBZW %2, 0, %bb.2
285+
B %bb.1
286+
287+
bb.1.if.then:
288+
successors: %bb.3(0x40000000), %bb.2(0x40000000)
289+
290+
ADJCALLSTACKDOWN 0, 0, implicit-def dead $sp, implicit $sp
291+
$x0 = COPY %0
292+
BL @g, csr_aarch64_aapcs, implicit-def dead $lr, implicit $sp, implicit $x0, implicit-def $sp, implicit-def $x0
293+
ADJCALLSTACKUP 0, 0, implicit-def dead $sp, implicit $sp
294+
TBNZW %4, 0, %bb.3
295+
B %bb.2
296+
297+
bb.2.if.end:
298+
successors: %bb.3(0x80000000)
299+
300+
301+
bb.3.exit:
302+
RET_ReallyLR
303+
304+
...

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