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pkarvetiquic-santdas
pkarveti
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quic-santdas
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[Hexagon] Added v32i1/v64i1 to v32f32/v64f16 lowering (#159355)
This patch introduces uint_to_fp conversions from v32i1 and v64i1 predicate vectors to v32f32 and v64f16 floating-point vectors. Patch-by: Santanu Das Co-authored-by: quic-santdas <quic_santdas@quicinc.com>
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‎llvm/lib/Target/Hexagon/HexagonISelLowering.cpp‎

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@@ -3352,7 +3352,6 @@ HexagonTargetLowering::LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const {
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SDValue
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HexagonTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
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unsigned Opc = Op.getOpcode();
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// Handle INLINEASM first.
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if (Opc == ISD::INLINEASM || Opc == ISD::INLINEASM_BR)
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return LowerINLINEASM(Op, DAG);

‎llvm/lib/Target/Hexagon/HexagonISelLowering.h‎

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@@ -577,6 +577,8 @@ class HexagonTargetLowering : public TargetLowering {
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SDValue LowerHvxFpExtend(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerHvxFpToInt(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerHvxIntToFp(SDValue Op, SelectionDAG &DAG) const;
580+
SDValue LowerHvxPred32ToFp(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerHvxPred64ToFp(SDValue Op, SelectionDAG &DAG) const;
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SDValue ExpandHvxFpToInt(SDValue Op, SelectionDAG &DAG) const;
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SDValue ExpandHvxIntToFp(SDValue Op, SelectionDAG &DAG) const;
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‎llvm/lib/Target/Hexagon/HexagonISelLoweringHVX.cpp‎

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Original file line numberDiff line numberDiff line change
@@ -446,6 +446,10 @@ HexagonTargetLowering::initializeHVXLowering() {
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}
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}
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// Include cases which are not hander earlier
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setOperationAction(ISD::UINT_TO_FP, MVT::v32i1, Custom);
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setOperationAction(ISD::UINT_TO_FP, MVT::v64i1, Custom);
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setTargetDAGCombine({ISD::CONCAT_VECTORS, ISD::TRUNCATE, ISD::VSELECT});
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}
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@@ -2333,6 +2337,123 @@ HexagonTargetLowering::LowerHvxFpToInt(SDValue Op, SelectionDAG &DAG) const {
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return ExpandHvxFpToInt(Op, DAG);
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}
23352339

2340+
// For vector type v32i1 uint_to_fp to v32f32:
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// R1 = #1, R2 holds the v32i1 param
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// V1 = vsplat(R1)
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// V2 = vsplat(R2)
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// Q0 = vand(V1,R1)
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// V0.w=prefixsum(Q0)
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// V0.w=vsub(V0.w,V1.w)
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// V2.w = vlsr(V2.w,V0.w)
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// V2 = vand(V2,V1)
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// V2.sf = V2.w
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SDValue HexagonTargetLowering::LowerHvxPred32ToFp(SDValue PredOp,
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SelectionDAG &DAG) const {
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MVT ResTy = ty(PredOp);
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const SDLoc &dl(PredOp);
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SDValue Const = DAG.getTargetConstant(0x1, dl, MVT::i32);
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SDNode *RegConst = DAG.getMachineNode(Hexagon::A2_tfrsi, dl, MVT::i32, Const);
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SDNode *SplatConst = DAG.getMachineNode(Hexagon::V6_lvsplatw, dl, MVT::v32i32,
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SDValue(RegConst, 0));
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SDNode *PredTransfer =
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DAG.getMachineNode(Hexagon::V6_vandvrt, dl, MVT::v32i1,
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SDValue(SplatConst, 0), SDValue(RegConst, 0));
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SDNode *PrefixSum = DAG.getMachineNode(Hexagon::V6_vprefixqw, dl, MVT::v32i32,
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SDValue(PredTransfer, 0));
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SDNode *SplatParam = DAG.getMachineNode(
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Hexagon::V6_lvsplatw, dl, MVT::v32i32,
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DAG.getNode(ISD::BITCAST, dl, MVT::i32, PredOp.getOperand(0)));
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SDNode *Vsub =
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DAG.getMachineNode(Hexagon::V6_vsubw, dl, MVT::v32i32,
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SDValue(PrefixSum, 0), SDValue(SplatConst, 0));
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SDNode *IndexShift =
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DAG.getMachineNode(Hexagon::V6_vlsrwv, dl, MVT::v32i32,
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SDValue(SplatParam, 0), SDValue(Vsub, 0));
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SDNode *MaskOff =
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DAG.getMachineNode(Hexagon::V6_vand, dl, MVT::v32i32,
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SDValue(IndexShift, 0), SDValue(SplatConst, 0));
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SDNode *Convert = DAG.getMachineNode(Hexagon::V6_vconv_sf_w, dl, ResTy,
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SDValue(MaskOff, 0));
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return SDValue(Convert, 0);
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}
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// For vector type v64i1 uint_to_fo to v64f16:
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// i64 R32 = bitcast v64i1 R3:2 (R3:2 holds v64i1)
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// R3 = subreg_high (R32)
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// R2 = subreg_low (R32)
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// R1 = #1
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// V1 = vsplat(R1)
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// V2 = vsplat(R2)
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// V3 = vsplat(R3)
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// Q0 = vand(V1,R1)
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// V0.w=prefixsum(Q0)
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// V0.w=vsub(V0.w,V1.w)
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// V2.w = vlsr(V2.w,V0.w)
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// V3.w = vlsr(V3.w,V0.w)
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// V2 = vand(V2,V1)
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// V3 = vand(V3,V1)
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// V2.h = vpacke(V3.w,V2.w)
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// V2.hf = V2.h
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SDValue HexagonTargetLowering::LowerHvxPred64ToFp(SDValue PredOp,
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SelectionDAG &DAG) const {
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MVT ResTy = ty(PredOp);
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const SDLoc &dl(PredOp);
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SDValue Inp = DAG.getNode(ISD::BITCAST, dl, MVT::i64, PredOp.getOperand(0));
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// Get the hi and lo regs
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SDValue HiReg =
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DAG.getTargetExtractSubreg(Hexagon::isub_hi, dl, MVT::i32, Inp);
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SDValue LoReg =
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DAG.getTargetExtractSubreg(Hexagon::isub_lo, dl, MVT::i32, Inp);
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// Get constant #1 and splat into vector V1
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SDValue Const = DAG.getTargetConstant(0x1, dl, MVT::i32);
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SDNode *RegConst = DAG.getMachineNode(Hexagon::A2_tfrsi, dl, MVT::i32, Const);
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SDNode *SplatConst = DAG.getMachineNode(Hexagon::V6_lvsplatw, dl, MVT::v32i32,
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SDValue(RegConst, 0));
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// Splat the hi and lo args
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SDNode *SplatHi =
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DAG.getMachineNode(Hexagon::V6_lvsplatw, dl, MVT::v32i32,
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DAG.getNode(ISD::BITCAST, dl, MVT::i32, HiReg));
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SDNode *SplatLo =
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DAG.getMachineNode(Hexagon::V6_lvsplatw, dl, MVT::v32i32,
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DAG.getNode(ISD::BITCAST, dl, MVT::i32, LoReg));
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// vand between splatted const and const
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SDNode *PredTransfer =
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DAG.getMachineNode(Hexagon::V6_vandvrt, dl, MVT::v32i1,
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SDValue(SplatConst, 0), SDValue(RegConst, 0));
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// Get the prefixsum
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SDNode *PrefixSum = DAG.getMachineNode(Hexagon::V6_vprefixqw, dl, MVT::v32i32,
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SDValue(PredTransfer, 0));
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// Get the vsub
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SDNode *Vsub =
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DAG.getMachineNode(Hexagon::V6_vsubw, dl, MVT::v32i32,
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SDValue(PrefixSum, 0), SDValue(SplatConst, 0));
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// Get vlsr for hi and lo
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SDNode *IndexShift_hi =
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DAG.getMachineNode(Hexagon::V6_vlsrwv, dl, MVT::v32i32,
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SDValue(SplatHi, 0), SDValue(Vsub, 0));
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SDNode *IndexShift_lo =
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DAG.getMachineNode(Hexagon::V6_vlsrwv, dl, MVT::v32i32,
2440+
SDValue(SplatLo, 0), SDValue(Vsub, 0));
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// Get vand of hi and lo
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SDNode *MaskOff_hi =
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DAG.getMachineNode(Hexagon::V6_vand, dl, MVT::v32i32,
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SDValue(IndexShift_hi, 0), SDValue(SplatConst, 0));
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SDNode *MaskOff_lo =
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DAG.getMachineNode(Hexagon::V6_vand, dl, MVT::v32i32,
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SDValue(IndexShift_lo, 0), SDValue(SplatConst, 0));
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// Pack them
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SDNode *Pack =
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DAG.getMachineNode(Hexagon::V6_vpackeh, dl, MVT::v64i16,
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SDValue(MaskOff_hi, 0), SDValue(MaskOff_lo, 0));
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SDNode *Convert =
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DAG.getMachineNode(Hexagon::V6_vconv_hf_h, dl, ResTy, SDValue(Pack, 0));
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return SDValue(Convert, 0);
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}
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SDValue
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HexagonTargetLowering::LowerHvxIntToFp(SDValue Op, SelectionDAG &DAG) const {
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// Catch invalid conversion ops (just in case).
@@ -2343,6 +2464,13 @@ HexagonTargetLowering::LowerHvxIntToFp(SDValue Op, SelectionDAG &DAG) const {
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MVT IntTy = ty(Op.getOperand(0)).getVectorElementType();
23442465
MVT FpTy = ResTy.getVectorElementType();
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2467+
if (Op.getOpcode() == ISD::UINT_TO_FP) {
2468+
if (ResTy == MVT::v32f32 && ty(Op.getOperand(0)) == MVT::v32i1)
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return LowerHvxPred32ToFp(Op, DAG);
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if (ResTy == MVT::v64f16 && ty(Op.getOperand(0)) == MVT::v64i1)
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return LowerHvxPred64ToFp(Op, DAG);
2472+
}
2473+
23462474
if (Subtarget.useHVXIEEEFPOps()) {
23472475
// There are only conversions to f16.
23482476
if (FpTy == MVT::f16) {

‎llvm/test/CodeGen/Hexagon/isel-uinttofp-v32i1tov32f32.ll‎

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@@ -0,0 +1,25 @@
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; Tests lowering of v32i1 to v32f32
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; RUN: llc -march=hexagon -mattr=+hvxv79,+hvx-length128b,+hvx-ieee-fp \
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; RUN: -stop-after=hexagon-isel %s -o - | FileCheck %s
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; CHECK: [[R0:%[0-9]+]]:hvxvr = V6_lvsplatw killed %{{[0-9]+}}
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; CHECK-NEXT: [[R1:%[0-9]+]]:intregs = A2_tfrsi 1
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; CHECK-NEXT: [[R2:%[0-9]+]]:hvxvr = V6_lvsplatw [[R1]]
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; CHECK-NEXT: [[R3:%[0-9]+]]:hvxqr = V6_vandvrt [[R2]], [[R1]]
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; CHECK-NEXT: [[R4:%[0-9]+]]:hvxvr = V6_vprefixqw killed [[R3]]
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; CHECK-NEXT: [[R5:%[0-9]+]]:hvxvr = V6_vsubw killed [[R4]], [[R2]]
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; CHECK-NEXT: [[R6:%[0-9]+]]:hvxvr = V6_vlsrwv killed [[R0]], killed [[R5]]
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; CHECK-NEXT: [[R7:%[0-9]+]]:hvxvr = V6_vand killed [[R6]], [[R2]]
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; CHECK-NEXT: [[R8:%[0-9]+]]:hvxvr = V6_vconv_sf_w killed [[R7]]
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; CHECK-NEXT: hvxvr = V6_vadd_sf_sf [[R8]], [[R8]]
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define <32 x float> @uitofp_i1(<32 x i16> %in0, <32 x i16> %in1) #0
18+
{
19+
%q1 = icmp eq <32 x i16> %in0, %in1
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%fp0 = uitofp <32 x i1> %q1 to <32 x float>
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%out = fadd <32 x float> %fp0, %fp0
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ret <32 x float> %out
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}
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attributes #0 = { nounwind readnone "target-cpu"="hexagonv79" "target-features"="+hvxv79,+hvx-length128b" }

‎llvm/test/CodeGen/Hexagon/isel-uinttofp-v64i1tov64f16.ll‎

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@@ -0,0 +1,27 @@
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; Tests the conversion pattern for v64i1 to v64f16
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; r0, r3 and r9 registers are i32 types converted from
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; v32i1 via a bitcasting sequence.
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; RUN: llc -march=hexagon -mattr=+hvxv79,+hvx-length128b \
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; RUN: %s -verify-machineinstrs -o - | FileCheck %s
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; CHECK: [[V3:v[0-9]+]] = vsplat([[R0:r[0-9]+]])
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; CHECK: [[Q0:q[0-9]+]] = vand([[V3]],[[R0]])
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; CHECK: [[V4:v[0-9]+]].w = prefixsum([[Q0]])
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; CHECK: [[V5:v[0-9]+]].w = vsub([[V4]].w,[[V3]].w)
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; CHECK: [[V1:v[0-9]+]] = vsplat(r
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; CHECK: [[V2:v[0-9]+]] = vsplat(r
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; CHECK: [[V6:v[0-9]+]].w = vlsr([[V1]].w,[[V5]].w)
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; CHECK: [[V7:v[0-9]+]].w = vlsr([[V2]].w,[[V5]].w)
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; CHECK: [[V8:v[0-9]+]] = vand([[V6]],[[V3]])
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; CHECK: [[V9:v[0-9]+]] = vand([[V7]],[[V3]])
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; CHECK: [[V10:v[0-9]+]].h = vpacke([[V9]].w,[[V8]].w)
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; CHECK: .hf = [[V10]].h
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define <64 x half> @uitofp_i1(<64 x i16> %in0, <64 x i16> %in1)
22+
{
23+
%in = icmp eq <64 x i16> %in0, %in1
24+
%fp0 = uitofp <64 x i1> %in to <64 x half>
25+
%out = fadd <64 x half> %fp0, %fp0
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ret <64 x half> %out
27+
}

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