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[FMV][AArch64] Unify aes with pmull and sve2-aes with sve2-pmull128. (#111673)
According to the Arm Architecture Reference Manual for A-profile architecture you can't have one feature without having the other: ID_AA64ZFR0_EL1.AES, bits [7:4] > FEAT_SVE_AES implements the functionality identified by the value 0b0001. > FEAT_SVE_PMULL128 implements the functionality identified by the value 0b0010. > The permitted values are 0b0000 and 0b0010. (The following was removed from the latest release of the specification, but it appears to be a mistake that was not intended to relax the architecture constraints. The discrepancy has been reported) ID_AA64ISAR0_EL1.AES, bits [7:4] > FEAT_AES implements the functionality identified by the value 0b0001. > FEAT_PMULL implements the functionality identified by the value 0b0010. > From Armv8, the permitted values are 0b0000 and 0b0010. Approved in ACLE as ARM-software/acle#352
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12 files changed

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‎clang/test/CodeGen/aarch64-cpu-supports.c

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -50,7 +50,7 @@ int main(void) {
5050
if (__builtin_cpu_supports("sb"))
5151
return 1;
5252

53-
if (__builtin_cpu_supports("sve2-pmull128+memtag"))
53+
if (__builtin_cpu_supports("sve2-aes+memtag"))
5454
return 2;
5555

5656
if (__builtin_cpu_supports("sme2+ls64+wfxt"))

‎clang/test/CodeGen/aarch64-fmv-dependencies.c

Lines changed: 5 additions & 11 deletions
Original file line numberDiff line numberDiff line change
@@ -3,7 +3,7 @@
33

44
// RUN: %clang --target=aarch64-linux-gnu --rtlib=compiler-rt -emit-llvm -S -o - %s | FileCheck %s
55

6-
// CHECK: define dso_local i32 @fmv._Maes() #[[ATTR0:[0-9]+]] {
6+
// CHECK: define dso_local i32 @fmv._Maes() #[[aes:[0-9]+]] {
77
__attribute__((target_version("aes"))) int fmv(void) { return 0; }
88

99
// CHECK: define dso_local i32 @fmv._Mbf16() #[[bf16_ebf16:[0-9]+]] {
@@ -81,9 +81,6 @@ __attribute__((target_version("memtag3"))) int fmv(void) { return 0; }
8181
// CHECK: define dso_local i32 @fmv._Mmops() #[[mops:[0-9]+]] {
8282
__attribute__((target_version("mops"))) int fmv(void) { return 0; }
8383

84-
// CHECK: define dso_local i32 @fmv._Mpmull() #[[pmull:[0-9]+]] {
85-
__attribute__((target_version("pmull"))) int fmv(void) { return 0; }
86-
8784
// CHECK: define dso_local i32 @fmv._Mpredres() #[[predres:[0-9]+]] {
8885
__attribute__((target_version("predres"))) int fmv(void) { return 0; }
8986

@@ -150,15 +147,12 @@ __attribute__((target_version("sve-i8mm"))) int fmv(void) { return 0; }
150147
// CHECK: define dso_local i32 @fmv._Msve2() #[[sve2:[0-9]+]] {
151148
__attribute__((target_version("sve2"))) int fmv(void) { return 0; }
152149

153-
// CHECK: define dso_local i32 @fmv._Msve2-aes() #[[sve2_aes_sve2_pmull128:[0-9]+]] {
150+
// CHECK: define dso_local i32 @fmv._Msve2-aes() #[[sve2_aes:[0-9]+]] {
154151
__attribute__((target_version("sve2-aes"))) int fmv(void) { return 0; }
155152

156153
// CHECK: define dso_local i32 @fmv._Msve2-bitperm() #[[sve2_bitperm:[0-9]+]] {
157154
__attribute__((target_version("sve2-bitperm"))) int fmv(void) { return 0; }
158155

159-
// CHECK: define dso_local i32 @fmv._Msve2-pmull128() #[[sve2_aes_sve2_pmull128:[0-9]+]] {
160-
__attribute__((target_version("sve2-pmull128"))) int fmv(void) { return 0; }
161-
162156
// CHECK: define dso_local i32 @fmv._Msve2-sha3() #[[sve2_sha3:[0-9]+]] {
163157
__attribute__((target_version("sve2-sha3"))) int fmv(void) { return 0; }
164158

@@ -177,10 +171,11 @@ int caller() {
177171
return fmv();
178172
}
179173

180-
// CHECK: attributes #[[ATTR0]] = { {{.*}} "target-features"="+fp-armv8,+neon,+outline-atomics,+v8a"
174+
// CHECK: attributes #[[aes]] = { {{.*}} "target-features"="+aes,+fp-armv8,+neon,+outline-atomics,+v8a"
181175
// CHECK: attributes #[[bf16_ebf16]] = { {{.*}} "target-features"="+bf16,+fp-armv8,+neon,+outline-atomics,+v8a"
182176
// CHECK: attributes #[[bti]] = { {{.*}} "target-features"="+bti,+fp-armv8,+neon,+outline-atomics,+v8a"
183177
// CHECK: attributes #[[crc]] = { {{.*}} "target-features"="+crc,+fp-armv8,+neon,+outline-atomics,+v8a"
178+
// CHECK: attributes #[[ATTR0]] = { {{.*}} "target-features"="+fp-armv8,+neon,+outline-atomics,+v8a"
184179
// CHECK: attributes #[[dit]] = { {{.*}} "target-features"="+dit,+fp-armv8,+neon,+outline-atomics,+v8a"
185180
// CHECK: attributes #[[dotprod]] = { {{.*}} "target-features"="+dotprod,+fp-armv8,+neon,+outline-atomics,+v8a"
186181
// CHECK: attributes #[[dpb]] = { {{.*}} "target-features"="+ccpp,+fp-armv8,+neon,+outline-atomics,+v8a"
@@ -199,7 +194,6 @@ int caller() {
199194
// CHECK: attributes #[[lse]] = { {{.*}} "target-features"="+fp-armv8,+lse,+neon,+outline-atomics,+v8a"
200195
// CHECK: attributes #[[memtag]] = { {{.*}} "target-features"="+fp-armv8,+mte,+neon,+outline-atomics,+v8a"
201196
// CHECK: attributes #[[mops]] = { {{.*}} "target-features"="+fp-armv8,+mops,+neon,+outline-atomics,+v8a"
202-
// CHECK: attributes #[[pmull]] = { {{.*}} "target-features"="+aes,+fp-armv8,+neon,+outline-atomics,+v8a"
203197
// CHECK: attributes #[[predres]] = { {{.*}} "target-features"="+fp-armv8,+neon,+outline-atomics,+predres,+v8a"
204198
// CHECK: attributes #[[rcpc]] = { {{.*}} "target-features"="+fp-armv8,+neon,+outline-atomics,+rcpc,+v8a"
205199
// CHECK: attributes #[[rcpc3]] = { {{.*}} "target-features"="+fp-armv8,+neon,+outline-atomics,+rcpc,+rcpc3,+v8a"
@@ -218,7 +212,7 @@ int caller() {
218212
// CHECK: attributes #[[sve_bf16_ebf16]] = { {{.*}} "target-features"="+bf16,+fp-armv8,+fullfp16,+neon,+outline-atomics,+sve,+v8a"
219213
// CHECK: attributes #[[sve_i8mm]] = { {{.*}} "target-features"="+fp-armv8,+fullfp16,+i8mm,+neon,+outline-atomics,+sve,+v8a"
220214
// CHECK: attributes #[[sve2]] = { {{.*}} "target-features"="+fp-armv8,+fullfp16,+neon,+outline-atomics,+sve,+sve2,+v8a"
221-
// CHECK: attributes #[[sve2_aes_sve2_pmull128]] = { {{.*}} "target-features"="+fp-armv8,+fullfp16,+neon,+outline-atomics,+sve,+sve2,+sve2-aes,+v8a"
215+
// CHECK: attributes #[[sve2_aes]] = { {{.*}} "target-features"="+aes,+fp-armv8,+fullfp16,+neon,+outline-atomics,+sve,+sve2,+sve2-aes,+v8a"
222216
// CHECK: attributes #[[sve2_bitperm]] = { {{.*}} "target-features"="+fp-armv8,+fullfp16,+neon,+outline-atomics,+sve,+sve2,+sve2-bitperm,+v8a"
223217
// CHECK: attributes #[[sve2_sha3]] = { {{.*}} "target-features"="+fp-armv8,+fullfp16,+neon,+outline-atomics,+sve,+sve2,+sve2-sha3,+v8a"
224218
// CHECK: attributes #[[sve2_sm4]] = { {{.*}} "target-features"="+fp-armv8,+fullfp16,+neon,+outline-atomics,+sve,+sve2,+sve2-sm4,+v8a"

‎clang/test/CodeGen/attr-target-clones-aarch64.c

Lines changed: 8 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -64,8 +64,8 @@ inline int __attribute__((target_clones("fp16", "sve2-bitperm+fcma", "default"))
6464
// CHECK-NEXT: resolver_entry:
6565
// CHECK-NEXT: call void @__init_cpu_features_resolver()
6666
// CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8
67-
// CHECK-NEXT: [[TMP1:%.*]] = and i64 [[TMP0]], 16512
68-
// CHECK-NEXT: [[TMP2:%.*]] = icmp eq i64 [[TMP1]], 16512
67+
// CHECK-NEXT: [[TMP1:%.*]] = and i64 [[TMP0]], 32896
68+
// CHECK-NEXT: [[TMP2:%.*]] = icmp eq i64 [[TMP1]], 32896
6969
// CHECK-NEXT: [[TMP3:%.*]] = and i1 true, [[TMP2]]
7070
// CHECK-NEXT: br i1 [[TMP3]], label [[RESOLVER_RETURN:%.*]], label [[RESOLVER_ELSE:%.*]]
7171
// CHECK: resolver_return:
@@ -360,8 +360,8 @@ inline int __attribute__((target_clones("fp16", "sve2-bitperm+fcma", "default"))
360360
// CHECK-NEXT: resolver_entry:
361361
// CHECK-NEXT: call void @__init_cpu_features_resolver()
362362
// CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8
363-
// CHECK-NEXT: [[TMP1:%.*]] = and i64 [[TMP0]], 18014535948435456
364-
// CHECK-NEXT: [[TMP2:%.*]] = icmp eq i64 [[TMP1]], 18014535948435456
363+
// CHECK-NEXT: [[TMP1:%.*]] = and i64 [[TMP0]], 18014673387388928
364+
// CHECK-NEXT: [[TMP2:%.*]] = icmp eq i64 [[TMP1]], 18014673387388928
365365
// CHECK-NEXT: [[TMP3:%.*]] = and i1 true, [[TMP2]]
366366
// CHECK-NEXT: br i1 [[TMP3]], label [[RESOLVER_RETURN:%.*]], label [[RESOLVER_ELSE:%.*]]
367367
// CHECK: resolver_return:
@@ -521,8 +521,8 @@ inline int __attribute__((target_clones("fp16", "sve2-bitperm+fcma", "default"))
521521
// CHECK-MTE-BTI-NEXT: resolver_entry:
522522
// CHECK-MTE-BTI-NEXT: call void @__init_cpu_features_resolver()
523523
// CHECK-MTE-BTI-NEXT: [[TMP0:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8
524-
// CHECK-MTE-BTI-NEXT: [[TMP1:%.*]] = and i64 [[TMP0]], 16512
525-
// CHECK-MTE-BTI-NEXT: [[TMP2:%.*]] = icmp eq i64 [[TMP1]], 16512
524+
// CHECK-MTE-BTI-NEXT: [[TMP1:%.*]] = and i64 [[TMP0]], 32896
525+
// CHECK-MTE-BTI-NEXT: [[TMP2:%.*]] = icmp eq i64 [[TMP1]], 32896
526526
// CHECK-MTE-BTI-NEXT: [[TMP3:%.*]] = and i1 true, [[TMP2]]
527527
// CHECK-MTE-BTI-NEXT: br i1 [[TMP3]], label [[RESOLVER_RETURN:%.*]], label [[RESOLVER_ELSE:%.*]]
528528
// CHECK-MTE-BTI: resolver_return:
@@ -817,8 +817,8 @@ inline int __attribute__((target_clones("fp16", "sve2-bitperm+fcma", "default"))
817817
// CHECK-MTE-BTI-NEXT: resolver_entry:
818818
// CHECK-MTE-BTI-NEXT: call void @__init_cpu_features_resolver()
819819
// CHECK-MTE-BTI-NEXT: [[TMP0:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8
820-
// CHECK-MTE-BTI-NEXT: [[TMP1:%.*]] = and i64 [[TMP0]], 18014535948435456
821-
// CHECK-MTE-BTI-NEXT: [[TMP2:%.*]] = icmp eq i64 [[TMP1]], 18014535948435456
820+
// CHECK-MTE-BTI-NEXT: [[TMP1:%.*]] = and i64 [[TMP0]], 18014673387388928
821+
// CHECK-MTE-BTI-NEXT: [[TMP2:%.*]] = icmp eq i64 [[TMP1]], 18014673387388928
822822
// CHECK-MTE-BTI-NEXT: [[TMP3:%.*]] = and i1 true, [[TMP2]]
823823
// CHECK-MTE-BTI-NEXT: br i1 [[TMP3]], label [[RESOLVER_RETURN:%.*]], label [[RESOLVER_ELSE:%.*]]
824824
// CHECK-MTE-BTI: resolver_return:

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