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RolandF77RolandF77
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[PowerPC] Intrinsics and tests for dmr insert/extract (#135653)
Add some intrinsics and LIT tests for PPC dmr insert/extract instructions.
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‎llvm/include/llvm/IR/IntrinsicsPowerPC.td

Lines changed: 16 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1677,6 +1677,22 @@ let TargetPrefix = "ppc" in {
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DefaultAttrsIntrinsic<[llvm_v1024i1_ty], [llvm_v1024i1_ty,
16781678
llvm_v1024i1_ty], [IntrNoMem]>;
16791679

1680+
def int_ppc_mma_dmxxextfdmr512 :
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DefaultAttrsIntrinsic<[llvm_v256i1_ty, llvm_v256i1_ty], [llvm_v1024i1_ty,
1682+
llvm_i32_ty], [IntrNoMem]>;
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def int_ppc_mma_dmxxinstdmr512 :
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DefaultAttrsIntrinsic<[llvm_v1024i1_ty], [llvm_v1024i1_ty, llvm_v256i1_ty,
1686+
llvm_v256i1_ty, llvm_i32_ty], [IntrNoMem]>;
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1688+
def int_ppc_mma_dmxxextfdmr256 :
1689+
DefaultAttrsIntrinsic<[llvm_v256i1_ty], [llvm_v1024i1_ty, llvm_i32_ty],
1690+
[IntrNoMem]>;
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1692+
def int_ppc_mma_dmxxinstdmr256 :
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DefaultAttrsIntrinsic<[llvm_v1024i1_ty], [llvm_v1024i1_ty, llvm_v256i1_ty,
1694+
llvm_i32_ty], [IntrNoMem]>;
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16801696
// MMA Reduced-Precision: Outer Product Intrinsic Definitions.
16811697
defm int_ppc_mma_xvi4ger8 :
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PowerPC_MMA_ACC_PP_Intrinsic<[llvm_v16i8_ty, llvm_v16i8_ty]>;

‎llvm/lib/Target/PowerPC/MCTargetDesc/PPCMCTargetDesc.h

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -294,6 +294,10 @@ static inline bool isVFRegister(unsigned Reg) {
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static inline bool isVRRegister(unsigned Reg) {
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return Reg >= PPC::V0 && Reg <= PPC::V31;
296296
}
297+
298+
static inline bool isDMRROWpRegister(unsigned Reg) {
299+
return Reg >= PPC::DMRROWp0 && Reg <= PPC::DMRROWp31;
300+
}
297301
} // namespace PPC
298302
} // namespace llvm
299303

‎llvm/lib/Target/PowerPC/PPCISelLowering.cpp

Lines changed: 110 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -11146,6 +11146,116 @@ SDValue PPCTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op,
1114611146
return DAG.getMergeValues(RetOps, dl);
1114711147
}
1114811148

11149+
case Intrinsic::ppc_mma_dmxxextfdmr512: {
11150+
assert(Subtarget.isISAFuture() && "dmxxextfdmr512 requires ISA Future");
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auto *Idx = dyn_cast<ConstantSDNode>(Op.getOperand(2));
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assert(Idx && (Idx->getSExtValue() == 0 || Idx->getSExtValue() == 1) &&
11153+
"Specify P of 0 or 1 for lower or upper 512 bytes");
11154+
unsigned HiLo = Idx->getSExtValue();
11155+
unsigned Opcode;
11156+
unsigned Subx;
11157+
if (HiLo == 0) {
11158+
Opcode = PPC::DMXXEXTFDMR512;
11159+
Subx = PPC::sub_wacc_lo;
11160+
} else {
11161+
Opcode = PPC::DMXXEXTFDMR512_HI;
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Subx = PPC::sub_wacc_hi;
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}
11164+
SDValue Subreg(
11165+
DAG.getMachineNode(TargetOpcode::EXTRACT_SUBREG, dl, MVT::v512i1,
11166+
Op.getOperand(1),
11167+
DAG.getTargetConstant(Subx, dl, MVT::i32)),
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0);
11169+
EVT ReturnTypes[] = {MVT::v256i1, MVT::v256i1};
11170+
return SDValue(DAG.getMachineNode(Opcode, dl, ReturnTypes, Subreg), 0);
11171+
}
11172+
11173+
case Intrinsic::ppc_mma_dmxxextfdmr256: {
11174+
assert(Subtarget.isISAFuture() && "dmxxextfdmr256 requires ISA Future");
11175+
auto *Idx = dyn_cast<ConstantSDNode>(Op.getOperand(2));
11176+
assert(Idx && (Idx->getSExtValue() >= 0 || Idx->getSExtValue() <= 3) &&
11177+
"Specify a dmr row pair 0-3");
11178+
unsigned IdxVal = Idx->getSExtValue();
11179+
unsigned Subx;
11180+
switch (IdxVal) {
11181+
case 0:
11182+
Subx = PPC::sub_dmrrowp0;
11183+
break;
11184+
case 1:
11185+
Subx = PPC::sub_dmrrowp1;
11186+
break;
11187+
case 2:
11188+
Subx = PPC::sub_wacc_hi_then_sub_dmrrowp0;
11189+
break;
11190+
case 3:
11191+
Subx = PPC::sub_wacc_hi_then_sub_dmrrowp1;
11192+
break;
11193+
}
11194+
SDValue Subreg(
11195+
DAG.getMachineNode(TargetOpcode::EXTRACT_SUBREG, dl, MVT::v256i1,
11196+
Op.getOperand(1),
11197+
DAG.getTargetConstant(Subx, dl, MVT::i32)),
11198+
0);
11199+
SDValue P = DAG.getTargetConstant(IdxVal, dl, MVT::i32);
11200+
return SDValue(
11201+
DAG.getMachineNode(PPC::DMXXEXTFDMR256, dl, MVT::v256i1, {Subreg, P}),
11202+
0);
11203+
}
11204+
11205+
case Intrinsic::ppc_mma_dmxxinstdmr512: {
11206+
assert(Subtarget.isISAFuture() && "dmxxinstdmr512 requires ISA Future");
11207+
auto *Idx = dyn_cast<ConstantSDNode>(Op.getOperand(4));
11208+
assert(Idx && (Idx->getSExtValue() == 0 || Idx->getSExtValue() == 1) &&
11209+
"Specify P of 0 or 1 for lower or upper 512 bytes");
11210+
unsigned HiLo = Idx->getSExtValue();
11211+
unsigned Opcode;
11212+
unsigned Subx;
11213+
if (HiLo == 0) {
11214+
Opcode = PPC::DMXXINSTDMR512;
11215+
Subx = PPC::sub_wacc_lo;
11216+
} else {
11217+
Opcode = PPC::DMXXINSTDMR512_HI;
11218+
Subx = PPC::sub_wacc_hi;
11219+
}
11220+
SDValue Ops[] = {Op.getOperand(2), Op.getOperand(3)};
11221+
SDValue Wacc = SDValue(DAG.getMachineNode(Opcode, dl, MVT::v512i1, Ops), 0);
11222+
SDValue SubReg = DAG.getTargetConstant(Subx, dl, MVT::i32);
11223+
return SDValue(DAG.getMachineNode(PPC::INSERT_SUBREG, dl, MVT::v1024i1,
11224+
Op.getOperand(1), Wacc, SubReg),
11225+
0);
11226+
}
11227+
11228+
case Intrinsic::ppc_mma_dmxxinstdmr256: {
11229+
assert(Subtarget.isISAFuture() && "dmxxinstdmr256 requires ISA Future");
11230+
auto *Idx = dyn_cast<ConstantSDNode>(Op.getOperand(3));
11231+
assert(Idx && (Idx->getSExtValue() >= 0 || Idx->getSExtValue() <= 3) &&
11232+
"Specify a dmr row pair 0-3");
11233+
unsigned IdxVal = Idx->getSExtValue();
11234+
unsigned Subx;
11235+
switch (IdxVal) {
11236+
case 0:
11237+
Subx = PPC::sub_dmrrowp0;
11238+
break;
11239+
case 1:
11240+
Subx = PPC::sub_dmrrowp1;
11241+
break;
11242+
case 2:
11243+
Subx = PPC::sub_wacc_hi_then_sub_dmrrowp0;
11244+
break;
11245+
case 3:
11246+
Subx = PPC::sub_wacc_hi_then_sub_dmrrowp1;
11247+
break;
11248+
}
11249+
SDValue SubReg = DAG.getTargetConstant(Subx, dl, MVT::i32);
11250+
SDValue P = DAG.getTargetConstant(IdxVal, dl, MVT::i32);
11251+
SDValue Ops[] = {Op.getOperand(2), P};
11252+
SDValue DMRRowp = SDValue(
11253+
DAG.getMachineNode(PPC::DMXXINSTDMR256, dl, MVT::v256i1, Ops), 0);
11254+
return SDValue(DAG.getMachineNode(PPC::INSERT_SUBREG, dl, MVT::v1024i1,
11255+
Op.getOperand(1), DMRRowp, SubReg),
11256+
0);
11257+
}
11258+
1114911259
case Intrinsic::ppc_mma_xxmfacc:
1115011260
case Intrinsic::ppc_mma_xxmtacc: {
1115111261
// Allow pre-isa-future subtargets to lower as normal.

‎llvm/lib/Target/PowerPC/PPCMCInstLower.cpp

Lines changed: 6 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -196,6 +196,12 @@ bool llvm::LowerPPCMachineOperandToMCOperand(const MachineOperand &MO,
196196
assert(MO.getReg() > PPC::NoRegister &&
197197
MO.getReg() < PPC::NUM_TARGET_REGS &&
198198
"Invalid register for this target!");
199+
// ISA instructions refer to the containing dmr reg.
200+
if (PPC::isDMRROWpRegister(MO.getReg())) {
201+
OutMO =
202+
MCOperand::createReg(PPC::DMR0 + (MO.getReg() - PPC::DMRROWp0) / 4);
203+
return true;
204+
}
199205
// Ignore all implicit register operands.
200206
if (MO.isImplicit())
201207
return false;

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