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[AMDGPU][MC] Allow 128-bit rsrc register in MIMG instructions
The r128 field in MIMG instructions indicates that the resource register is 128-bit. However, the assembler will reject instructions with 128-bit resource register even when r128 is present. This patch fixes this problem.
1 parent 6dbe82f commit a5767b1

16 files changed

+336
-293
lines changed

‎llvm/lib/Target/AMDGPU/MIMGInstructions.td

Lines changed: 27 additions & 23 deletions
Original file line numberDiff line numberDiff line change
@@ -871,11 +871,11 @@ multiclass MIMG_Store <mimgopc op, string asm, bit has_d16, bit mip = 0> {
871871
}
872872

873873
class MIMG_Atomic_gfx6789_base <bits<8> op, string asm, RegisterClass data_rc,
874-
RegisterClass addr_rc, string dns="">
874+
RegisterClass addr_rc, string dns="", bits<1> hasR128=false>
875875
: MIMG_gfx6789 <op, (outs data_rc:$vdst), dns> {
876876
let Constraints = "$vdst = $vdata";
877877

878-
let InOperandList = (ins data_rc:$vdata, addr_rc:$vaddr, SReg_256_XNULL:$srsrc,
878+
let InOperandList = (ins data_rc:$vdata, addr_rc:$vaddr, !if(hasR128, SReg_128_XNULL, SReg_256_XNULL):$srsrc,
879879
DMask:$dmask, UNorm:$unorm, CPol:$cpol,
880880
R128A16:$r128, TFE:$tfe, LWE:$lwe, DA:$da);
881881
let AsmString = asm#" $vdst, $vaddr, $srsrc$dmask$unorm$cpol$r128$tfe$lwe$da";
@@ -893,18 +893,20 @@ class MIMG_Atomic_gfx90a_base <bits<8> op, string asm, RegisterClass data_rc,
893893
let AsmString = asm#" $vdst, $vaddr, $srsrc$dmask$unorm$cpol$r128$lwe$da";
894894
}
895895

896-
class MIMG_Atomic_si<mimgopc op, string asm, RegisterClass data_rc,
897-
RegisterClass addr_rc, bit enableDasm = 0>
898-
: MIMG_Atomic_gfx6789_base<op.SI, asm, data_rc, addr_rc,
899-
!if(enableDasm, "GFX6GFX7", "")> {
900-
let AssemblerPredicate = isGFX6GFX7;
896+
multiclass MIMG_Atomic_si<mimgopc op, string asm, RegisterClass data_rc, RegisterClass addr_rc, bit enableDasm = 0> {
897+
let AssemblerPredicate = isGFX6GFX7 in {
898+
def _r1_si : MIMG_Atomic_gfx6789_base<op.SI, asm, data_rc, addr_rc, !if(enableDasm, "GFX6GFX7", "")>;
899+
def _r2_si : MIMG_Atomic_gfx6789_base<op.SI, asm, data_rc, addr_rc, "", /*hasR128*/ true>;
900+
}
901901
}
902902

903-
class MIMG_Atomic_vi<mimgopc op, string asm, RegisterClass data_rc,
904-
RegisterClass addr_rc, bit enableDasm = 0>
905-
: MIMG_Atomic_gfx6789_base<op.VI, asm, data_rc, addr_rc, !if(enableDasm, "GFX8", "")> {
906-
let AssemblerPredicate = isGFX8GFX9NotGFX90A;
907-
let MIMGEncoding = MIMGEncGfx8;
903+
multiclass MIMG_Atomic_vi<mimgopc op, string asm, RegisterClass data_rc, RegisterClass addr_rc, bit enableDasm = 0> {
904+
let AssemblerPredicate = isGFX8GFX9NotGFX90A, MIMGEncoding = MIMGEncGfx8 in {
905+
def _r1_vi : MIMG_Atomic_gfx6789_base<op.VI, asm, data_rc, addr_rc, !if(enableDasm, "GFX8", "")>;
906+
}
907+
let AssemblerPredicate = isGFX8Only, MIMGEncoding = MIMGEncGfx8 in {
908+
def _r2_vi : MIMG_Atomic_gfx6789_base<op.VI, asm, data_rc, addr_rc, "", /*hasR128*/ true>;
909+
}
908910
}
909911

910912
class MIMG_Atomic_gfx90a<mimgopc op, string asm, RegisterClass data_rc,
@@ -995,10 +997,10 @@ multiclass MIMG_Atomic_Addr_Helper_m <mimgopc op, string asm,
995997
let VAddrDwords = 1 in {
996998
let ssamp = 0 in {
997999
if op.HAS_SI then {
998-
def _V1_si : MIMG_Atomic_si <op, asm, data_rc, VGPR_32, enableDasm>;
1000+
defm _V1 : MIMG_Atomic_si <op, asm, data_rc, VGPR_32, enableDasm>;
9991001
}
10001002
if op.HAS_VI then {
1001-
def _V1_vi : MIMG_Atomic_vi <op, asm, data_rc, VGPR_32, enableDasm>;
1003+
defm _V1 : MIMG_Atomic_vi <op, asm, data_rc, VGPR_32, enableDasm>;
10021004
let hasPostISelHook = 1 in
10031005
def _V1_gfx90a : MIMG_Atomic_gfx90a <op, asm, data_rc, VGPR_32, enableDasm>;
10041006
}
@@ -1016,10 +1018,10 @@ multiclass MIMG_Atomic_Addr_Helper_m <mimgopc op, string asm,
10161018
let VAddrDwords = 2 in {
10171019
let ssamp = 0 in {
10181020
if op.HAS_SI then {
1019-
def _V2_si : MIMG_Atomic_si <op, asm, data_rc, VReg_64, 0>;
1021+
defm _V2 : MIMG_Atomic_si <op, asm, data_rc, VReg_64, 0>;
10201022
}
10211023
if op.HAS_VI then {
1022-
def _V2_vi : MIMG_Atomic_vi <op, asm, data_rc, VReg_64, 0>;
1024+
defm _V2 : MIMG_Atomic_vi <op, asm, data_rc, VReg_64, 0>;
10231025
def _V2_gfx90a : MIMG_Atomic_gfx90a <op, asm, data_rc, VReg_64, 0>;
10241026
}
10251027
if op.HAS_GFX10M then {
@@ -1038,10 +1040,10 @@ multiclass MIMG_Atomic_Addr_Helper_m <mimgopc op, string asm,
10381040
let VAddrDwords = 3 in {
10391041
let ssamp = 0 in {
10401042
if op.HAS_SI then {
1041-
def _V3_si : MIMG_Atomic_si <op, asm, data_rc, VReg_96, 0>;
1043+
defm _V3 : MIMG_Atomic_si <op, asm, data_rc, VReg_96, 0>;
10421044
}
10431045
if op.HAS_VI then {
1044-
def _V3_vi : MIMG_Atomic_vi <op, asm, data_rc, VReg_96, 0>;
1046+
defm _V3 : MIMG_Atomic_vi <op, asm, data_rc, VReg_96, 0>;
10451047
def _V3_gfx90a : MIMG_Atomic_gfx90a <op, asm, data_rc, VReg_96, 0>;
10461048
}
10471049
if op.HAS_GFX10M then {
@@ -1060,10 +1062,10 @@ multiclass MIMG_Atomic_Addr_Helper_m <mimgopc op, string asm,
10601062
let VAddrDwords = 4 in {
10611063
let ssamp = 0 in {
10621064
if op.HAS_SI then {
1063-
def _V4_si : MIMG_Atomic_si <op, asm, data_rc, VReg_128, 0>;
1065+
defm _V4 : MIMG_Atomic_si <op, asm, data_rc, VReg_128, 0>;
10641066
}
10651067
if op.HAS_VI then {
1066-
def _V4_vi : MIMG_Atomic_vi <op, asm, data_rc, VReg_128, 0>;
1068+
defm _V4 : MIMG_Atomic_vi <op, asm, data_rc, VReg_128, 0>;
10671069
def _V4_gfx90a : MIMG_Atomic_gfx90a <op, asm, data_rc, VReg_128, 0>;
10681070
}
10691071
if op.HAS_GFX10M then {
@@ -1126,9 +1128,9 @@ multiclass MIMG_Atomic_Renamed <mimgopc op, string asm, string renamed,
11261128
: MIMG_Atomic <op, asm, isCmpSwap, isFP, renamed>;
11271129

11281130
class MIMG_Sampler_Helper <mimgopc op, string asm, RegisterClass dst_rc,
1129-
RegisterClass src_rc, string dns="">
1131+
RegisterClass src_rc, string dns="", bits<1> hasR128=false>
11301132
: MIMG_gfx6789 <op.VI, (outs dst_rc:$vdata), dns> {
1131-
let InOperandList = !con((ins src_rc:$vaddr, SReg_256_XNULL:$srsrc, SReg_128_XNULL:$ssamp,
1133+
let InOperandList = !con((ins src_rc:$vaddr, !if(hasR128, SReg_128_XNULL, SReg_256_XNULL):$srsrc, SReg_128_XNULL:$ssamp,
11321134
DMask:$dmask, UNorm:$unorm, CPol:$cpol,
11331135
R128A16:$r128, TFE:$tfe, LWE:$lwe, DA:$da),
11341136
!if(BaseOpcode.HasD16, (ins D16:$d16), (ins)));
@@ -1349,9 +1351,11 @@ multiclass MIMG_Sampler_Src_Helper <mimgopc op, string asm,
13491351
foreach addr = MIMG_Sampler_AddrSizes<sample, isG16>.MachineInstrs in {
13501352
let VAddrDwords = addr.NumWords in {
13511353
if op.HAS_GFX10M then {
1352-
def _V # addr.NumWords
1354+
def _V # addr.NumWords # _r1
13531355
: MIMG_Sampler_Helper <op, asm, dst_rc, addr.RegClass,
13541356
!if(!and(enableDisasm, addr.Disassemble), "GFX8", "")>;
1357+
def _V # addr.NumWords # _r2
1358+
: MIMG_Sampler_Helper <op, asm, dst_rc, addr.RegClass, "", /*hasR128*/ true>;
13551359
if !not(ExtendedImageInst) then
13561360
def _V # addr.NumWords # _gfx90a
13571361
: MIMG_Sampler_gfx90a <op, asm, dst_rc, addr.RegClass,

‎llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.atomic.dim.mir

Lines changed: 8 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -21,7 +21,7 @@ body: |
2121
; GFX6-NEXT: [[COPY:%[0-9]+]]:sgpr_256 = COPY $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7
2222
; GFX6-NEXT: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
2323
; GFX6-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
24-
; GFX6-NEXT: [[IMAGE_ATOMIC_CMPSWAP_V2_V1_si:%[0-9]+]]:vreg_64 = IMAGE_ATOMIC_CMPSWAP_V2_V1_si [[COPY1]], [[COPY2]], [[COPY]], 3, 1, 1, 0, 0, 0, 0, implicit $exec :: (volatile dereferenceable load store (s32), addrspace 8)
24+
; GFX6-NEXT: [[IMAGE_ATOMIC_CMPSWAP_V2_V1_si:%[0-9]+]]:vreg_64 = IMAGE_ATOMIC_CMPSWAP_V2_V1_r1_si [[COPY1]], [[COPY2]], [[COPY]], 3, 1, 1, 0, 0, 0, 0, implicit $exec :: (volatile dereferenceable load store (s32), addrspace 8)
2525
; GFX6-NEXT: [[COPY3:%[0-9]+]]:vgpr_32 = COPY killed [[IMAGE_ATOMIC_CMPSWAP_V2_V1_si]].sub0
2626
; GFX6-NEXT: $vgpr0 = COPY [[COPY3]]
2727
; GFX6-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0
@@ -31,7 +31,7 @@ body: |
3131
; GFX8-NEXT: [[COPY:%[0-9]+]]:sgpr_256 = COPY $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7
3232
; GFX8-NEXT: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
3333
; GFX8-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
34-
; GFX8-NEXT: [[IMAGE_ATOMIC_CMPSWAP_V2_V1_vi:%[0-9]+]]:vreg_64 = IMAGE_ATOMIC_CMPSWAP_V2_V1_vi [[COPY1]], [[COPY2]], [[COPY]], 3, 1, 1, 0, 0, 0, 0, implicit $exec :: (volatile dereferenceable load store (s32), addrspace 8)
34+
; GFX8-NEXT: [[IMAGE_ATOMIC_CMPSWAP_V2_V1_vi:%[0-9]+]]:vreg_64 = IMAGE_ATOMIC_CMPSWAP_V2_V1_r1_vi [[COPY1]], [[COPY2]], [[COPY]], 3, 1, 1, 0, 0, 0, 0, implicit $exec :: (volatile dereferenceable load store (s32), addrspace 8)
3535
; GFX8-NEXT: [[COPY3:%[0-9]+]]:vgpr_32 = COPY killed [[IMAGE_ATOMIC_CMPSWAP_V2_V1_vi]].sub0
3636
; GFX8-NEXT: $vgpr0 = COPY [[COPY3]]
3737
; GFX8-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0
@@ -89,15 +89,15 @@ body: |
8989
; GFX6-NEXT: [[COPY:%[0-9]+]]:sgpr_256 = COPY $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7
9090
; GFX6-NEXT: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
9191
; GFX6-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
92-
; GFX6-NEXT: [[IMAGE_ATOMIC_CMPSWAP_V2_V1_si:%[0-9]+]]:vreg_64 = IMAGE_ATOMIC_CMPSWAP_V2_V1_si [[COPY1]], [[COPY2]], [[COPY]], 3, 1, 1, 0, 0, 0, 0, implicit $exec :: (volatile dereferenceable load store (s32), addrspace 8)
92+
; GFX6-NEXT: [[IMAGE_ATOMIC_CMPSWAP_V2_V1_si:%[0-9]+]]:vreg_64 = IMAGE_ATOMIC_CMPSWAP_V2_V1_r1_si [[COPY1]], [[COPY2]], [[COPY]], 3, 1, 1, 0, 0, 0, 0, implicit $exec :: (volatile dereferenceable load store (s32), addrspace 8)
9393
; GFX6-NEXT: S_ENDPGM 0
9494
; GFX8-LABEL: name: atomic_cmpswap_i32_1d_no_return
9595
; GFX8: liveins: $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7, $vgpr0_vgpr1, $vgpr2
9696
; GFX8-NEXT: {{ $}}
9797
; GFX8-NEXT: [[COPY:%[0-9]+]]:sgpr_256 = COPY $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7
9898
; GFX8-NEXT: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
9999
; GFX8-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
100-
; GFX8-NEXT: [[IMAGE_ATOMIC_CMPSWAP_V1_V1_vi:%[0-9]+]]:vreg_64 = IMAGE_ATOMIC_CMPSWAP_V2_V1_vi [[COPY1]], [[COPY2]], [[COPY]], 3, 1, 1, 0, 0, 0, 0, implicit $exec :: (volatile dereferenceable load store (s32), addrspace 8)
100+
; GFX8-NEXT: [[IMAGE_ATOMIC_CMPSWAP_V1_V1_vi:%[0-9]+]]:vreg_64 = IMAGE_ATOMIC_CMPSWAP_V2_V1_r1_vi [[COPY1]], [[COPY2]], [[COPY]], 3, 1, 1, 0, 0, 0, 0, implicit $exec :: (volatile dereferenceable load store (s32), addrspace 8)
101101
; GFX8-NEXT: S_ENDPGM 0
102102
; GFX10-LABEL: name: atomic_cmpswap_i32_1d_no_return
103103
; GFX10: liveins: $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7, $vgpr0_vgpr1, $vgpr2
@@ -146,7 +146,7 @@ body: |
146146
; GFX6-NEXT: [[COPY:%[0-9]+]]:sgpr_256 = COPY $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7
147147
; GFX6-NEXT: [[COPY1:%[0-9]+]]:vreg_128 = COPY $vgpr0_vgpr1_vgpr2_vgpr3
148148
; GFX6-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr4
149-
; GFX6-NEXT: [[IMAGE_ATOMIC_CMPSWAP_V4_V1_si:%[0-9]+]]:vreg_128 = IMAGE_ATOMIC_CMPSWAP_V4_V1_si [[COPY1]], [[COPY2]], [[COPY]], 15, 1, 1, 0, 0, 0, 0, implicit $exec :: (volatile dereferenceable load store (s64), addrspace 8)
149+
; GFX6-NEXT: [[IMAGE_ATOMIC_CMPSWAP_V4_V1_si:%[0-9]+]]:vreg_128 = IMAGE_ATOMIC_CMPSWAP_V4_V1_r1_si [[COPY1]], [[COPY2]], [[COPY]], 15, 1, 1, 0, 0, 0, 0, implicit $exec :: (volatile dereferenceable load store (s64), addrspace 8)
150150
; GFX6-NEXT: [[COPY3:%[0-9]+]]:vreg_64 = COPY killed [[IMAGE_ATOMIC_CMPSWAP_V4_V1_si]].sub0_sub1
151151
; GFX6-NEXT: $vgpr0_vgpr1 = COPY [[COPY3]]
152152
; GFX6-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0_vgpr1
@@ -156,7 +156,7 @@ body: |
156156
; GFX8-NEXT: [[COPY:%[0-9]+]]:sgpr_256 = COPY $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7
157157
; GFX8-NEXT: [[COPY1:%[0-9]+]]:vreg_128 = COPY $vgpr0_vgpr1_vgpr2_vgpr3
158158
; GFX8-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr4
159-
; GFX8-NEXT: [[IMAGE_ATOMIC_CMPSWAP_V4_V1_vi:%[0-9]+]]:vreg_128 = IMAGE_ATOMIC_CMPSWAP_V4_V1_vi [[COPY1]], [[COPY2]], [[COPY]], 15, 1, 1, 0, 0, 0, 0, implicit $exec :: (volatile dereferenceable load store (s64), addrspace 8)
159+
; GFX8-NEXT: [[IMAGE_ATOMIC_CMPSWAP_V4_V1_vi:%[0-9]+]]:vreg_128 = IMAGE_ATOMIC_CMPSWAP_V4_V1_r1_vi [[COPY1]], [[COPY2]], [[COPY]], 15, 1, 1, 0, 0, 0, 0, implicit $exec :: (volatile dereferenceable load store (s64), addrspace 8)
160160
; GFX8-NEXT: [[COPY3:%[0-9]+]]:vreg_64 = COPY killed [[IMAGE_ATOMIC_CMPSWAP_V4_V1_vi]].sub0_sub1
161161
; GFX8-NEXT: $vgpr0_vgpr1 = COPY [[COPY3]]
162162
; GFX8-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0_vgpr1
@@ -214,15 +214,15 @@ body: |
214214
; GFX6-NEXT: [[COPY:%[0-9]+]]:sgpr_256 = COPY $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7
215215
; GFX6-NEXT: [[COPY1:%[0-9]+]]:vreg_128 = COPY $vgpr0_vgpr1_vgpr2_vgpr3
216216
; GFX6-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr4
217-
; GFX6-NEXT: [[IMAGE_ATOMIC_CMPSWAP_V4_V1_si:%[0-9]+]]:vreg_128 = IMAGE_ATOMIC_CMPSWAP_V4_V1_si [[COPY1]], [[COPY2]], [[COPY]], 15, 1, 1, 0, 0, 0, 0, implicit $exec :: (volatile dereferenceable load store (s64), addrspace 8)
217+
; GFX6-NEXT: [[IMAGE_ATOMIC_CMPSWAP_V4_V1_si:%[0-9]+]]:vreg_128 = IMAGE_ATOMIC_CMPSWAP_V4_V1_r1_si [[COPY1]], [[COPY2]], [[COPY]], 15, 1, 1, 0, 0, 0, 0, implicit $exec :: (volatile dereferenceable load store (s64), addrspace 8)
218218
; GFX6-NEXT: S_ENDPGM 0
219219
; GFX8-LABEL: name: atomic_cmpswap_i64_1d_no_return
220220
; GFX8: liveins: $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7, $vgpr0_vgpr1_vgpr2_vgpr3, $vgpr4
221221
; GFX8-NEXT: {{ $}}
222222
; GFX8-NEXT: [[COPY:%[0-9]+]]:sgpr_256 = COPY $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7
223223
; GFX8-NEXT: [[COPY1:%[0-9]+]]:vreg_128 = COPY $vgpr0_vgpr1_vgpr2_vgpr3
224224
; GFX8-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr4
225-
; GFX8-NEXT: [[IMAGE_ATOMIC_CMPSWAP_V4_V1_vi:%[0-9]+]]:vreg_128 = IMAGE_ATOMIC_CMPSWAP_V4_V1_vi [[COPY1]], [[COPY2]], [[COPY]], 15, 1, 1, 0, 0, 0, 0, implicit $exec :: (volatile dereferenceable load store (s64), addrspace 8)
225+
; GFX8-NEXT: [[IMAGE_ATOMIC_CMPSWAP_V4_V1_vi:%[0-9]+]]:vreg_128 = IMAGE_ATOMIC_CMPSWAP_V4_V1_r1_vi [[COPY1]], [[COPY2]], [[COPY]], 15, 1, 1, 0, 0, 0, 0, implicit $exec :: (volatile dereferenceable load store (s64), addrspace 8)
226226
; GFX8-NEXT: S_ENDPGM 0
227227
; GFX10-LABEL: name: atomic_cmpswap_i64_1d_no_return
228228
; GFX10: liveins: $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7, $vgpr0_vgpr1_vgpr2_vgpr3, $vgpr4

‎llvm/test/CodeGen/AMDGPU/alloc-aligned-tuples-gfx908.mir

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -92,7 +92,7 @@ body: |
9292
%1:vgpr_32 = COPY $vgpr2
9393
%3:sgpr_256 = IMPLICIT_DEF
9494
%2:vreg_256 = COPY %3:sgpr_256
95-
%4:vreg_128 = IMAGE_SAMPLE_C_CL_O_V4_V8 %2, %3:sgpr_256, undef %5:sgpr_128, 0, 0, 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load (s32), addrspace 4)
95+
%4:vreg_128 = IMAGE_SAMPLE_C_CL_O_V4_V8_r1 %2, %3:sgpr_256, undef %5:sgpr_128, 0, 0, 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load (s32), addrspace 4)
9696
GLOBAL_STORE_DWORDX4 %0, %2.sub0_sub1_sub2_sub3, 0, 0, implicit $exec
9797
GLOBAL_STORE_DWORD %0, %1, 0, 0, implicit $exec
9898
...

‎llvm/test/CodeGen/AMDGPU/alloc-aligned-tuples-gfx90a.mir

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -94,7 +94,7 @@ body: |
9494
%1:vgpr_32 = COPY $vgpr2
9595
%3:sgpr_256 = IMPLICIT_DEF
9696
%2:vreg_256_align2 = COPY %3:sgpr_256
97-
%4:vreg_128_align2 = IMAGE_SAMPLE_C_CL_O_V4_V8 %2, %3:sgpr_256, undef %5:sgpr_128, 0, 0, 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load (s32), addrspace 4)
97+
%4:vreg_128_align2 = IMAGE_SAMPLE_C_CL_O_V4_V8_r1 %2, %3:sgpr_256, undef %5:sgpr_128, 0, 0, 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load (s32), addrspace 4)
9898
GLOBAL_STORE_DWORDX4 %0, %2.sub0_sub1_sub2_sub3, 0, 0, implicit $exec
9999
GLOBAL_STORE_DWORD %0, %1, 0, 0, implicit $exec
100100
...

‎llvm/test/CodeGen/AMDGPU/coalescer-subranges-another-prune-error.mir

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -257,7 +257,7 @@ body: |
257257
%109.sub5:sgpr_256 = COPY %108
258258
%109.sub6:sgpr_256 = COPY %108
259259
%109.sub7:sgpr_256 = COPY killed %108
260-
%110:vgpr_32 = IMAGE_SAMPLE_V1_V2 killed %107, killed %109, undef %111:sgpr_128, 8, 0, 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load (s128) from constant-pool, addrspace 4)
260+
%110:vgpr_32 = IMAGE_SAMPLE_V1_V2_r1 killed %107, killed %109, undef %111:sgpr_128, 8, 0, 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load (s128) from constant-pool, addrspace 4)
261261
%112:vgpr_32 = nofpexcept V_MUL_F32_e32 0, killed %110, implicit $mode, implicit $exec
262262
%113:vgpr_32 = nofpexcept V_MUL_F32_e32 0, killed %112, implicit $mode, implicit $exec
263263
%114:vgpr_32 = nofpexcept V_MAD_F32_e64 0, killed %113, 0, 0, 0, 0, 0, 0, implicit $mode, implicit $exec

‎llvm/test/CodeGen/AMDGPU/coalescer-subreg-join.mir

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -1,7 +1,7 @@
11
# RUN: llc -mtriple=amdgcn -run-pass register-coalescer -o - %s | FileCheck %s
22
# Check that %11 and %20 have been coalesced.
3-
# CHECK: IMAGE_SAMPLE_C_D_O_V1_V11 %[[REG:[0-9]+]]
4-
# CHECK: IMAGE_SAMPLE_C_D_O_V1_V11 %[[REG]]
3+
# CHECK: IMAGE_SAMPLE_C_D_O_V1_V11_r1 %[[REG:[0-9]+]]
4+
# CHECK: IMAGE_SAMPLE_C_D_O_V1_V11_r1 %[[REG]]
55

66
---
77
name: main
@@ -61,7 +61,7 @@ body: |
6161
%11.sub6 = COPY %1
6262
%11.sub7 = COPY %1
6363
%11.sub8 = COPY %1
64-
dead %18 = IMAGE_SAMPLE_C_D_O_V1_V11 %11, %3, %4, 1, 0, 0, 0, 0, 0, -1, 0, implicit $exec :: (load (s32))
64+
dead %18 = IMAGE_SAMPLE_C_D_O_V1_V11_r1 %11, %3, %4, 1, 0, 0, 0, 0, 0, -1, 0, implicit $exec :: (load (s32))
6565
%20.sub1 = COPY %2
6666
%20.sub2 = COPY %2
6767
%20.sub3 = COPY %2
@@ -70,6 +70,6 @@ body: |
7070
%20.sub6 = COPY %2
7171
%20.sub7 = COPY %2
7272
%20.sub8 = COPY %2
73-
dead %27 = IMAGE_SAMPLE_C_D_O_V1_V11 %20, %5, %6, 1, 0, 0, 0, 0, 0, -1, 0, implicit $exec :: (load (s32))
73+
dead %27 = IMAGE_SAMPLE_C_D_O_V1_V11_r1 %20, %5, %6, 1, 0, 0, 0, 0, 0, -1, 0, implicit $exec :: (load (s32))
7474
7575
...

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