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7 files changed

+34
-37
lines changed

7 files changed

+34
-37
lines changed

‎clang/test/CodeGenHLSL/builtins/tan.hlsl‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -56,4 +56,4 @@ float3 test_tan_float3 ( float3 p0 ) {
5656
// CHECK: call <4 x float> @llvm.tan.v4f32
5757
float4 test_tan_float4 ( float4 p0 ) {
5858
return tan ( p0 );
59-
}
59+
}

‎llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp‎

Lines changed: 2 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -4485,9 +4485,8 @@ void SelectionDAGLegalize::ConvertNodeToLibcall(SDNode *Node) {
44854485
break;
44864486
case ISD::FTAN:
44874487
case ISD::STRICT_FTAN:
4488-
ExpandFPLibCall(Node, RTLIB::TAN_F32, RTLIB::TAN_F64,
4489-
RTLIB::TAN_F80, RTLIB::TAN_F128,
4490-
RTLIB::TAN_PPCF128, Results);
4488+
ExpandFPLibCall(Node, RTLIB::TAN_F32, RTLIB::TAN_F64, RTLIB::TAN_F80,
4489+
RTLIB::TAN_F128, RTLIB::TAN_PPCF128, Results);
44914490
break;
44924491
case ISD::FSINCOS:
44934492
// Expand into sincos libcall.

‎llvm/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp‎

Lines changed: 13 additions & 13 deletions
Original file line numberDiff line numberDiff line change
@@ -777,12 +777,9 @@ SDValue DAGTypeLegalizer::SoftenFloatRes_FSUB(SDNode *N) {
777777
}
778778

779779
SDValue DAGTypeLegalizer::SoftenFloatRes_FTAN(SDNode *N) {
780-
return SoftenFloatRes_Unary(N, GetFPLibCall(N->getValueType(0),
781-
RTLIB::TAN_F32,
782-
RTLIB::TAN_F64,
783-
RTLIB::TAN_F80,
784-
RTLIB::TAN_F128,
785-
RTLIB::TAN_PPCF128));
780+
return SoftenFloatRes_Unary(
781+
N, GetFPLibCall(N->getValueType(0), RTLIB::TAN_F32, RTLIB::TAN_F64,
782+
RTLIB::TAN_F80, RTLIB::TAN_F128, RTLIB::TAN_PPCF128));
786783
}
787784

788785
SDValue DAGTypeLegalizer::SoftenFloatRes_FTRUNC(SDNode *N) {
@@ -1411,7 +1408,9 @@ void DAGTypeLegalizer::ExpandFloatResult(SDNode *N, unsigned ResNo) {
14111408
case ISD::STRICT_FSUB:
14121409
case ISD::FSUB: ExpandFloatRes_FSUB(N, Lo, Hi); break;
14131410
case ISD::STRICT_FTAN:
1414-
case ISD::FTAN: ExpandFloatRes_FTAN(N, Lo, Hi); break;
1411+
case ISD::FTAN:
1412+
ExpandFloatRes_FTAN(N, Lo, Hi);
1413+
break;
14151414
case ISD::STRICT_FTRUNC:
14161415
case ISD::FTRUNC: ExpandFloatRes_FTRUNC(N, Lo, Hi); break;
14171416
case ISD::LOAD: ExpandFloatRes_LOAD(N, Lo, Hi); break;
@@ -1781,12 +1780,13 @@ void DAGTypeLegalizer::ExpandFloatRes_FSUB(SDNode *N, SDValue &Lo,
17811780
RTLIB::SUB_PPCF128), Lo, Hi);
17821781
}
17831782

1784-
void DAGTypeLegalizer::ExpandFloatRes_FTAN(SDNode *N,
1785-
SDValue &Lo, SDValue &Hi) {
1786-
ExpandFloatRes_Unary(N, GetFPLibCall(N->getValueType(0),
1787-
RTLIB::TAN_F32, RTLIB::TAN_F64,
1788-
RTLIB::TAN_F80, RTLIB::TAN_F128,
1789-
RTLIB::TAN_PPCF128), Lo, Hi);
1783+
void DAGTypeLegalizer::ExpandFloatRes_FTAN(SDNode *N, SDValue &Lo,
1784+
SDValue &Hi) {
1785+
ExpandFloatRes_Unary(N,
1786+
GetFPLibCall(N->getValueType(0), RTLIB::TAN_F32,
1787+
RTLIB::TAN_F64, RTLIB::TAN_F80,
1788+
RTLIB::TAN_F128, RTLIB::TAN_PPCF128),
1789+
Lo, Hi);
17901790
}
17911791

17921792
void DAGTypeLegalizer::ExpandFloatRes_FTRUNC(SDNode *N,

‎llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -649,7 +649,7 @@ class LLVM_LIBRARY_VISIBILITY DAGTypeLegalizer {
649649
void ExpandFloatRes_FSIN (SDNode *N, SDValue &Lo, SDValue &Hi);
650650
void ExpandFloatRes_FSQRT (SDNode *N, SDValue &Lo, SDValue &Hi);
651651
void ExpandFloatRes_FSUB (SDNode *N, SDValue &Lo, SDValue &Hi);
652-
void ExpandFloatRes_FTAN (SDNode *N, SDValue &Lo, SDValue &Hi);
652+
void ExpandFloatRes_FTAN(SDNode *N, SDValue &Lo, SDValue &Hi);
653653
void ExpandFloatRes_FTRUNC (SDNode *N, SDValue &Lo, SDValue &Hi);
654654
void ExpandFloatRes_LOAD (SDNode *N, SDValue &Lo, SDValue &Hi);
655655
void ExpandFloatRes_XINT_TO_FP(SDNode *N, SDValue &Lo, SDValue &Hi);

‎llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp‎

Lines changed: 3 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -6707,7 +6707,9 @@ void SelectionDAGBuilder::visitIntrinsicCall(const CallInst &I,
67076707
case Intrinsic::fabs: Opcode = ISD::FABS; break;
67086708
case Intrinsic::sin: Opcode = ISD::FSIN; break;
67096709
case Intrinsic::cos: Opcode = ISD::FCOS; break;
6710-
case Intrinsic::tan: Opcode = ISD::FTAN; break;
6710+
case Intrinsic::tan:
6711+
Opcode = ISD::FTAN;
6712+
break;
67116713
case Intrinsic::exp10: Opcode = ISD::FEXP10; break;
67126714
case Intrinsic::floor: Opcode = ISD::FFLOOR; break;
67136715
case Intrinsic::ceil: Opcode = ISD::FCEIL; break;

‎llvm/lib/CodeGen/TargetLoweringBase.cpp‎

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -988,7 +988,8 @@ void TargetLoweringBase::initActions() {
988988
setOperationAction({ISD::FCBRT, ISD::FLOG, ISD::FLOG2, ISD::FLOG10, ISD::FEXP,
989989
ISD::FEXP2, ISD::FEXP10, ISD::FFLOOR, ISD::FNEARBYINT,
990990
ISD::FCEIL, ISD::FRINT, ISD::FTRUNC, ISD::LROUND,
991-
ISD::LLROUND, ISD::LRINT, ISD::LLRINT, ISD::FROUNDEVEN, ISD::FTAN},
991+
ISD::LLROUND, ISD::LRINT, ISD::LLRINT, ISD::FROUNDEVEN,
992+
ISD::FTAN},
992993
{MVT::f32, MVT::f64, MVT::f128}, Expand);
993994

994995
// Default ISD::TRAP to expand (which turns it into abort).

‎llvm/lib/Target/X86/X86ISelLowering.cpp‎

Lines changed: 12 additions & 17 deletions
Original file line numberDiff line numberDiff line change
@@ -655,7 +655,7 @@ X86TargetLowering::X86TargetLowering(const X86TargetMachine &TM,
655655
setOperationAction(ISD::FSIN , VT, Expand);
656656
setOperationAction(ISD::FCOS , VT, Expand);
657657
setOperationAction(ISD::FSINCOS, VT, Expand);
658-
setOperationAction(ISD::FTAN , VT, Expand);
658+
setOperationAction(ISD::FTAN, VT, Expand);
659659
}
660660

661661
// Half type will be promoted by default.
@@ -731,7 +731,7 @@ X86TargetLowering::X86TargetLowering(const X86TargetMachine &TM,
731731
setOperationAction(ISD::FSIN , MVT::f32, Expand);
732732
setOperationAction(ISD::FCOS , MVT::f32, Expand);
733733
setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
734-
setOperationAction(ISD::FTAN , MVT::f32, Expand);
734+
setOperationAction(ISD::FTAN, MVT::f32, Expand);
735735

736736
if (UseX87) {
737737
// Always expand sin/cos functions even though x87 has an instruction.
@@ -754,7 +754,7 @@ X86TargetLowering::X86TargetLowering(const X86TargetMachine &TM,
754754
setOperationAction(ISD::FSIN , VT, Expand);
755755
setOperationAction(ISD::FCOS , VT, Expand);
756756
setOperationAction(ISD::FSINCOS, VT, Expand);
757-
setOperationAction(ISD::FTAN , VT, Expand);
757+
setOperationAction(ISD::FTAN, VT, Expand);
758758
}
759759
}
760760

@@ -824,7 +824,7 @@ X86TargetLowering::X86TargetLowering(const X86TargetMachine &TM,
824824
setOperationAction(ISD::FSIN , MVT::f80, Expand);
825825
setOperationAction(ISD::FCOS , MVT::f80, Expand);
826826
setOperationAction(ISD::FSINCOS, MVT::f80, Expand);
827-
setOperationAction(ISD::FTAN , MVT::f80, Expand);
827+
setOperationAction(ISD::FTAN, MVT::f80, Expand);
828828

829829
setOperationAction(ISD::FFLOOR, MVT::f80, Expand);
830830
setOperationAction(ISD::FCEIL, MVT::f80, Expand);
@@ -882,8 +882,8 @@ X86TargetLowering::X86TargetLowering(const X86TargetMachine &TM,
882882
setOperationAction(ISD::FCOS, MVT::f128, LibCall);
883883
setOperationAction(ISD::STRICT_FCOS, MVT::f128, LibCall);
884884
setOperationAction(ISD::FSINCOS, MVT::f128, LibCall);
885-
setOperationAction(ISD::FTAN, MVT::f128, LibCall);
886-
setOperationAction(ISD::STRICT_FTAN, MVT::f128, LibCall);
885+
setOperationAction(ISD::FTAN, MVT::f128, LibCall);
886+
setOperationAction(ISD::STRICT_FTAN, MVT::f128, LibCall);
887887
// No STRICT_FSINCOS
888888
setOperationAction(ISD::FSQRT, MVT::f128, LibCall);
889889
setOperationAction(ISD::STRICT_FSQRT, MVT::f128, LibCall);
@@ -938,7 +938,7 @@ X86TargetLowering::X86TargetLowering(const X86TargetMachine &TM,
938938
setOperationAction(ISD::FSIN, VT, Expand);
939939
setOperationAction(ISD::FSINCOS, VT, Expand);
940940
setOperationAction(ISD::FCOS, VT, Expand);
941-
setOperationAction(ISD::FTAN, VT, Expand);
941+
setOperationAction(ISD::FTAN, VT, Expand);
942942
setOperationAction(ISD::FREM, VT, Expand);
943943
setOperationAction(ISD::FCOPYSIGN, VT, Expand);
944944
setOperationAction(ISD::FPOW, VT, Expand);
@@ -2475,16 +2475,11 @@ X86TargetLowering::X86TargetLowering(const X86TargetMachine &TM,
24752475
if (Subtarget.is32Bit() &&
24762476
(Subtarget.isTargetWindowsMSVC() || Subtarget.isTargetWindowsItanium()))
24772477
for (ISD::NodeType Op :
2478-
{ISD::FCEIL, ISD::STRICT_FCEIL,
2479-
ISD::FCOS, ISD::STRICT_FCOS,
2480-
ISD::FEXP, ISD::STRICT_FEXP,
2481-
ISD::FFLOOR, ISD::STRICT_FFLOOR,
2482-
ISD::FREM, ISD::STRICT_FREM,
2483-
ISD::FLOG, ISD::STRICT_FLOG,
2484-
ISD::FLOG10, ISD::STRICT_FLOG10,
2485-
ISD::FPOW, ISD::STRICT_FPOW,
2486-
ISD::FSIN, ISD::STRICT_FSIN,
2487-
ISD::FTAN, ISD::STRICT_FTAN})
2478+
{ISD::FCEIL, ISD::STRICT_FCEIL, ISD::FCOS, ISD::STRICT_FCOS,
2479+
ISD::FEXP, ISD::STRICT_FEXP, ISD::FFLOOR, ISD::STRICT_FFLOOR,
2480+
ISD::FREM, ISD::STRICT_FREM, ISD::FLOG, ISD::STRICT_FLOG,
2481+
ISD::FLOG10, ISD::STRICT_FLOG10, ISD::FPOW, ISD::STRICT_FPOW,
2482+
ISD::FSIN, ISD::STRICT_FSIN, ISD::FTAN, ISD::STRICT_FTAN})
24882483
if (isOperationExpand(Op, MVT::f32))
24892484
setOperationAction(Op, MVT::f32, Promote);
24902485

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