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[SelectionDAG] Introducing a new ISD::POISON SDNode to represent the poison value in the IR. (#125883)
A new ISD::POISON SDNode is introduced to represent the `poison value` in the IR, replacing the previous use of ISD::UNDEF.
1 parent 82103df commit 8fddef8

15 files changed

+73
-38
lines changed

‎llvm/include/llvm/CodeGen/ISDOpcodes.h

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -217,6 +217,9 @@ enum NodeType {
217217
/// UNDEF - An undefined node.
218218
UNDEF,
219219

220+
/// POISON - A poison node.
221+
POISON,
222+
220223
/// FREEZE - FREEZE(VAL) returns an arbitrary value if VAL is UNDEF (or
221224
/// is evaluated to UNDEF), or returns VAL otherwise. Note that each
222225
/// read of UNDEF can yield different value, but FREEZE(UNDEF) cannot.

‎llvm/include/llvm/CodeGen/SelectionDAG.h

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1130,6 +1130,9 @@ class SelectionDAG {
11301130
return getNode(ISD::UNDEF, SDLoc(), VT);
11311131
}
11321132

1133+
/// Return a POISON node. POISON does not have a useful SDLoc.
1134+
SDValue getPOISON(EVT VT) { return getNode(ISD::POISON, SDLoc(), VT); }
1135+
11331136
/// Return a node that represents the runtime scaling 'MulImm * RuntimeVL'.
11341137
SDValue getVScale(const SDLoc &DL, EVT VT, APInt MulImm,
11351138
bool ConstantFold = true);

‎llvm/include/llvm/CodeGen/SelectionDAGNodes.h

Lines changed: 4 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -692,8 +692,10 @@ END_TWO_BYTE_PACK()
692692
/// \<target\>ISD namespace).
693693
bool isTargetOpcode() const { return NodeType >= ISD::BUILTIN_OP_END; }
694694

695-
/// Return true if the type of the node type undefined.
696-
bool isUndef() const { return NodeType == ISD::UNDEF; }
695+
/// Returns true if the node type is UNDEF or POISON.
696+
bool isUndef() const {
697+
return NodeType == ISD::UNDEF || NodeType == ISD::POISON;
698+
}
697699

698700
/// Test if this node is a memory intrinsic (with valid pointer information).
699701
bool isMemIntrinsic() const { return SDNodeBits.IsMemIntrinsic; }

‎llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -16287,7 +16287,8 @@ SDValue DAGCombiner::visitFREEZE(SDNode *N) {
1628716287
// Finally, recreate the node, it's operands were updated to use
1628816288
// frozen operands, so we just need to use it's "original" operands.
1628916289
SmallVector<SDValue> Ops(N0->ops());
16290-
// Special-handle ISD::UNDEF, each single one of them can be it's own thing.
16290+
// TODO: ISD::UNDEF and ISD::POISON should get separate handling, but best
16291+
// leave for a future patch.
1629116292
for (SDValue &Op : Ops) {
1629216293
if (Op.isUndef())
1629316294
Op = DAG.getFreeze(Op);

‎llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp

Lines changed: 14 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -986,6 +986,19 @@ void SelectionDAGLegalize::LegalizeOp(SDNode *Node) {
986986
TargetLowering::LegalizeAction Action = TargetLowering::Legal;
987987
bool SimpleFinishLegalizing = true;
988988
switch (Node->getOpcode()) {
989+
// TODO: Currently, POISON is being lowered to UNDEF here. However, there is
990+
// an open concern that this transformation may not be ideal, as targets
991+
// should ideally handle POISON directly. Changing this behavior would require
992+
// adding support for POISON in TableGen, which is a large change.
993+
// Additionally, many existing test cases rely on the current behavior (e.g.,
994+
// llvm/test/CodeGen/PowerPC/vec_shuffle.ll). A broader discussion and
995+
// incremental changes might be needed to properly
996+
// support POISON without breaking existing targets and tests.
997+
case ISD::POISON: {
998+
SDValue UndefNode = DAG.getUNDEF(Node->getValueType(0));
999+
ReplaceNode(Node, UndefNode.getNode());
1000+
break;
1001+
}
9891002
case ISD::INTRINSIC_W_CHAIN:
9901003
case ISD::INTRINSIC_WO_CHAIN:
9911004
case ISD::INTRINSIC_VOID:
@@ -3169,6 +3182,7 @@ bool SelectionDAGLegalize::ExpandNode(SDNode *Node) {
31693182
for (unsigned i = 0; i < Node->getNumValues(); i++)
31703183
Results.push_back(Node->getOperand(i));
31713184
break;
3185+
case ISD::POISON:
31723186
case ISD::UNDEF: {
31733187
EVT VT = Node->getValueType(0);
31743188
if (VT.isInteger())

‎llvm/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -2845,6 +2845,7 @@ void DAGTypeLegalizer::PromoteFloatResult(SDNode *N, unsigned ResNo) {
28452845

28462846
case ISD::SINT_TO_FP:
28472847
case ISD::UINT_TO_FP: R = PromoteFloatRes_XINT_TO_FP(N); break;
2848+
case ISD::POISON:
28482849
case ISD::UNDEF: R = PromoteFloatRes_UNDEF(N); break;
28492850
case ISD::ATOMIC_SWAP: R = BitcastToInt_ATOMIC_SWAP(N); break;
28502851
case ISD::VECREDUCE_FADD:

‎llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -118,6 +118,7 @@ void DAGTypeLegalizer::PromoteIntegerResult(SDNode *N, unsigned ResNo) {
118118
case ISD::VP_SRL: Res = PromoteIntRes_SRL(N); break;
119119
case ISD::VP_TRUNCATE:
120120
case ISD::TRUNCATE: Res = PromoteIntRes_TRUNCATE(N); break;
121+
case ISD::POISON:
121122
case ISD::UNDEF: Res = PromoteIntRes_UNDEF(N); break;
122123
case ISD::VAARG: Res = PromoteIntRes_VAARG(N); break;
123124
case ISD::VSCALE: Res = PromoteIntRes_VSCALE(N); break;
@@ -2932,6 +2933,7 @@ void DAGTypeLegalizer::ExpandIntegerResult(SDNode *N, unsigned ResNo) {
29322933
case ISD::MERGE_VALUES: SplitRes_MERGE_VALUES(N, ResNo, Lo, Hi); break;
29332934
case ISD::SELECT: SplitRes_Select(N, Lo, Hi); break;
29342935
case ISD::SELECT_CC: SplitRes_SELECT_CC(N, Lo, Hi); break;
2936+
case ISD::POISON:
29352937
case ISD::UNDEF: SplitRes_UNDEF(N, Lo, Hi); break;
29362938
case ISD::FREEZE: SplitRes_FREEZE(N, Lo, Hi); break;
29372939
case ISD::SETCC: ExpandIntRes_SETCC(N, Lo, Hi); break;

‎llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -71,6 +71,7 @@ void DAGTypeLegalizer::ScalarizeVectorResult(SDNode *N, unsigned ResNo) {
7171
case ISD::SELECT: R = ScalarizeVecRes_SELECT(N); break;
7272
case ISD::SELECT_CC: R = ScalarizeVecRes_SELECT_CC(N); break;
7373
case ISD::SETCC: R = ScalarizeVecRes_SETCC(N); break;
74+
case ISD::POISON:
7475
case ISD::UNDEF: R = ScalarizeVecRes_UNDEF(N); break;
7576
case ISD::VECTOR_SHUFFLE: R = ScalarizeVecRes_VECTOR_SHUFFLE(N); break;
7677
case ISD::IS_FPCLASS: R = ScalarizeVecRes_IS_FPCLASS(N); break;
@@ -1137,6 +1138,7 @@ void DAGTypeLegalizer::SplitVectorResult(SDNode *N, unsigned ResNo) {
11371138
case ISD::VP_MERGE:
11381139
case ISD::VP_SELECT: SplitRes_Select(N, Lo, Hi); break;
11391140
case ISD::SELECT_CC: SplitRes_SELECT_CC(N, Lo, Hi); break;
1141+
case ISD::POISON:
11401142
case ISD::UNDEF: SplitRes_UNDEF(N, Lo, Hi); break;
11411143
case ISD::BITCAST: SplitVecRes_BITCAST(N, Lo, Hi); break;
11421144
case ISD::BUILD_VECTOR: SplitVecRes_BUILD_VECTOR(N, Lo, Hi); break;
@@ -4592,6 +4594,7 @@ void DAGTypeLegalizer::WidenVectorResult(SDNode *N, unsigned ResNo) {
45924594
case ISD::SELECT_CC: Res = WidenVecRes_SELECT_CC(N); break;
45934595
case ISD::VP_SETCC:
45944596
case ISD::SETCC: Res = WidenVecRes_SETCC(N); break;
4597+
case ISD::POISON:
45954598
case ISD::UNDEF: Res = WidenVecRes_UNDEF(N); break;
45964599
case ISD::VECTOR_SHUFFLE:
45974600
Res = WidenVecRes_VECTOR_SHUFFLE(cast<ShuffleVectorSDNode>(N));

‎llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -5387,6 +5387,9 @@ bool SelectionDAG::isGuaranteedNotToBeUndefOrPoison(SDValue Op,
53875387
case ISD::CopyFromReg:
53885388
return true;
53895389

5390+
case ISD::POISON:
5391+
return false;
5392+
53905393
case ISD::UNDEF:
53915394
return PoisonOnly;
53925395

‎llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1817,7 +1817,7 @@ SDValue SelectionDAGBuilder::getValueImpl(const Value *V) {
18171817
return DAG.getConstantFP(*CFP, getCurSDLoc(), VT);
18181818

18191819
if (isa<UndefValue>(C) && !V->getType()->isAggregateType())
1820-
return DAG.getUNDEF(VT);
1820+
return isa<PoisonValue>(C) ? DAG.getPOISON(VT) : DAG.getUNDEF(VT);
18211821

18221822
if (const ConstantExpr *CE = dyn_cast<ConstantExpr>(C)) {
18231823
visit(CE->getOpcode(), *CE);

‎llvm/lib/CodeGen/SelectionDAG/SelectionDAGDumper.cpp

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -189,6 +189,7 @@ std::string SDNode::getOperationName(const SelectionDAG *G) const {
189189
case ISD::CopyToReg: return "CopyToReg";
190190
case ISD::CopyFromReg: return "CopyFromReg";
191191
case ISD::UNDEF: return "undef";
192+
case ISD::POISON: return "poison";
192193
case ISD::VSCALE: return "vscale";
193194
case ISD::MERGE_VALUES: return "merge_values";
194195
case ISD::INLINEASM: return "inlineasm";

‎llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -3276,6 +3276,7 @@ void SelectionDAGISel::SelectCodeCommon(SDNode *NodeToMatch,
32763276
case ISD::WRITE_REGISTER:
32773277
Select_WRITE_REGISTER(NodeToMatch);
32783278
return;
3279+
case ISD::POISON:
32793280
case ISD::UNDEF:
32803281
Select_UNDEF(NodeToMatch);
32813282
return;

‎llvm/test/CodeGen/AArch64/vector-insert-dag-combines.ll

Lines changed: 19 additions & 19 deletions
Original file line numberDiff line numberDiff line change
@@ -12,15 +12,15 @@ target triple = "aarch64-unknown-linux-gnu"
1212
; CHECK: t0: ch,glue = EntryToken
1313
; CHECK: t2: v8i8,ch = CopyFromReg t0, Register:v8i8 %0
1414
; CHECK: t4: v4i8 = extract_subvector t2, Constant:i64<0>
15-
; CHECK: t6: v16i8 = insert_subvector undef:v16i8, t4, Constant:i64<0>
15+
; CHECK: t6: v16i8 = insert_subvector poison:v16i8, t4, Constant:i64<0>
1616
; CHECK: t8: ch,glue = CopyToReg t0, Register:v16i8 $q0, t6
1717
; CHECK: t9: ch = AArch64ISD::RET_GLUE t8, Register:v16i8 $q0, t8:1
1818

1919
; CHECK: Optimized lowered selection DAG: %bb.0 'insert_small_fixed_into_big_fixed:'
2020
; CHECK: SelectionDAG has 9 nodes:
2121
; CHECK: t0: ch,glue = EntryToken
2222
; CHECK: t2: v8i8,ch = CopyFromReg t0, Register:v8i8 %0
23-
; CHECK: t10: v16i8 = insert_subvector undef:v16i8, t2, Constant:i64<0>
23+
; CHECK: t10: v16i8 = insert_subvector poison:v16i8, t2, Constant:i64<0>
2424
; CHECK: t8: ch,glue = CopyToReg t0, Register:v16i8 $q0, t10
2525
; CHECK: t9: ch = AArch64ISD::RET_GLUE t8, Register:v16i8 $q0, t8:1
2626

@@ -35,15 +35,15 @@ define <16 x i8> @insert_small_fixed_into_big_fixed(<8 x i8> %a) #0 {
3535
; CHECK: t0: ch,glue = EntryToken
3636
; CHECK: t2: v8i8,ch = CopyFromReg t0, Register:v8i8 %0
3737
; CHECK: t4: v4i8 = extract_subvector t2, Constant:i64<0>
38-
; CHECK: t6: nxv16i8 = insert_subvector undef:nxv16i8, t4, Constant:i64<0>
38+
; CHECK: t6: nxv16i8 = insert_subvector poison:nxv16i8, t4, Constant:i64<0>
3939
; CHECK: t8: ch,glue = CopyToReg t0, Register:nxv16i8 $z0, t6
4040
; CHECK: t9: ch = AArch64ISD::RET_GLUE t8, Register:nxv16i8 $z0, t8:1
4141

4242
; CHECK: Optimized lowered selection DAG: %bb.0 'insert_small_fixed_into_big_scalable:'
4343
; CHECK: SelectionDAG has 9 nodes:
4444
; CHECK: t0: ch,glue = EntryToken
4545
; CHECK: t2: v8i8,ch = CopyFromReg t0, Register:v8i8 %0
46-
; CHECK: t10: nxv16i8 = insert_subvector undef:nxv16i8, t2, Constant:i64<0>
46+
; CHECK: t10: nxv16i8 = insert_subvector poison:nxv16i8, t2, Constant:i64<0>
4747
; CHECK: t8: ch,glue = CopyToReg t0, Register:nxv16i8 $z0, t10
4848
; CHECK: t9: ch = AArch64ISD::RET_GLUE t8, Register:nxv16i8 $z0, t8:1
4949

@@ -59,7 +59,7 @@ define <vscale x 16 x i8> @insert_small_fixed_into_big_scalable(<8 x i8> %a) #0
5959
; CHECK: t2: nxv8i16,ch = CopyFromReg t0, Register:nxv8i16 %0
6060
; CHECK: t3: nxv8i8 = truncate t2
6161
; CHECK: t5: v4i8 = extract_subvector t3, Constant:i64<0>
62-
; CHECK: t7: v16i8 = insert_subvector undef:v16i8, t5, Constant:i64<0>
62+
; CHECK: t7: v16i8 = insert_subvector poison:v16i8, t5, Constant:i64<0>
6363
; CHECK: t9: ch,glue = CopyToReg t0, Register:v16i8 $q0, t7
6464
; CHECK: t10: ch = AArch64ISD::RET_GLUE t9, Register:v16i8 $q0, t9:1
6565

@@ -69,7 +69,7 @@ define <vscale x 16 x i8> @insert_small_fixed_into_big_scalable(<8 x i8> %a) #0
6969
; CHECK: t2: nxv8i16,ch = CopyFromReg t0, Register:nxv8i16 %0
7070
; CHECK: t3: nxv8i8 = truncate t2
7171
; CHECK: t5: v4i8 = extract_subvector t3, Constant:i64<0>
72-
; CHECK: t7: v16i8 = insert_subvector undef:v16i8, t5, Constant:i64<0>
72+
; CHECK: t7: v16i8 = insert_subvector poison:v16i8, t5, Constant:i64<0>
7373
; CHECK: t9: ch,glue = CopyToReg t0, Register:v16i8 $q0, t7
7474
; CHECK: t10: ch = AArch64ISD::RET_GLUE t9, Register:v16i8 $q0, t9:1
7575

@@ -86,7 +86,7 @@ define <16 x i8> @insert_small_scalable_into_big_fixed(<vscale x 8 x i8> %a) #0
8686
; CHECK: t2: nxv8i16,ch = CopyFromReg t0, Register:nxv8i16 %0
8787
; CHECK: t3: nxv8i8 = truncate t2
8888
; CHECK: t5: v4i8 = extract_subvector t3, Constant:i64<0>
89-
; CHECK: t7: nxv16i8 = insert_subvector undef:nxv16i8, t5, Constant:i64<0>
89+
; CHECK: t7: nxv16i8 = insert_subvector poison:nxv16i8, t5, Constant:i64<0>
9090
; CHECK: t9: ch,glue = CopyToReg t0, Register:nxv16i8 $z0, t7
9191
; CHECK: t10: ch = AArch64ISD::RET_GLUE t9, Register:nxv16i8 $z0, t9:1
9292

@@ -95,7 +95,7 @@ define <16 x i8> @insert_small_scalable_into_big_fixed(<vscale x 8 x i8> %a) #0
9595
; CHECK: t0: ch,glue = EntryToken
9696
; CHECK: t2: nxv8i16,ch = CopyFromReg t0, Register:nxv8i16 %0
9797
; CHECK: t3: nxv8i8 = truncate t2
98-
; CHECK: t11: nxv16i8 = insert_subvector undef:nxv16i8, t3, Constant:i64<0>
98+
; CHECK: t11: nxv16i8 = insert_subvector poison:nxv16i8, t3, Constant:i64<0>
9999
; CHECK: t9: ch,glue = CopyToReg t0, Register:nxv16i8 $z0, t11
100100
; CHECK: t10: ch = AArch64ISD::RET_GLUE t9, Register:nxv16i8 $z0, t9:1
101101

@@ -111,7 +111,7 @@ define <vscale x 16 x i8> @insert_small_scalable_into_big_scalable_1(<vscale x 8
111111
; CHECK: t2: nxv8i16,ch = CopyFromReg t0, Register:nxv8i16 %0
112112
; CHECK: t3: nxv8i8 = truncate t2
113113
; CHECK: t5: nxv4i8 = extract_subvector t3, Constant:i64<0>
114-
; CHECK: t7: nxv16i8 = insert_subvector undef:nxv16i8, t5, Constant:i64<0>
114+
; CHECK: t7: nxv16i8 = insert_subvector poison:nxv16i8, t5, Constant:i64<0>
115115
; CHECK: t9: ch,glue = CopyToReg t0, Register:nxv16i8 $z0, t7
116116
; CHECK: t10: ch = AArch64ISD::RET_GLUE t9, Register:nxv16i8 $z0, t9:1
117117

@@ -120,7 +120,7 @@ define <vscale x 16 x i8> @insert_small_scalable_into_big_scalable_1(<vscale x 8
120120
; CHECK: t0: ch,glue = EntryToken
121121
; CHECK: t2: nxv8i16,ch = CopyFromReg t0, Register:nxv8i16 %0
122122
; CHECK: t3: nxv8i8 = truncate t2
123-
; CHECK: t11: nxv16i8 = insert_subvector undef:nxv16i8, t3, Constant:i64<0>
123+
; CHECK: t11: nxv16i8 = insert_subvector poison:nxv16i8, t3, Constant:i64<0>
124124
; CHECK: t9: ch,glue = CopyToReg t0, Register:nxv16i8 $z0, t11
125125
; CHECK: t10: ch = AArch64ISD::RET_GLUE t9, Register:nxv16i8 $z0, t9:1
126126

@@ -135,7 +135,7 @@ define <vscale x 16 x i8> @insert_small_scalable_into_big_scalable_2(<vscale x 8
135135
; CHECK: t0: ch,glue = EntryToken
136136
; CHECK: t2: v16i8,ch = CopyFromReg t0, Register:v16i8 %0
137137
; CHECK: t4: v4i8 = extract_subvector t2, Constant:i64<0>
138-
; CHECK: t6: v8i8 = insert_subvector undef:v8i8, t4, Constant:i64<0>
138+
; CHECK: t6: v8i8 = insert_subvector poison:v8i8, t4, Constant:i64<0>
139139
; CHECK: t8: ch,glue = CopyToReg t0, Register:v8i8 $d0, t6
140140
; CHECK: t9: ch = AArch64ISD::RET_GLUE t8, Register:v8i8 $d0, t8:1
141141

@@ -158,7 +158,7 @@ define <8 x i8> @extract_small_fixed_from_big_fixed(<16 x i8> %a) #0 {
158158
; CHECK: t0: ch,glue = EntryToken
159159
; CHECK: t2: v16i8,ch = CopyFromReg t0, Register:v16i8 %0
160160
; CHECK: t4: v4i8 = extract_subvector t2, Constant:i64<0>
161-
; CHECK: t6: nxv8i8 = insert_subvector undef:nxv8i8, t4, Constant:i64<0>
161+
; CHECK: t6: nxv8i8 = insert_subvector poison:nxv8i8, t4, Constant:i64<0>
162162
; CHECK: t7: nxv8i16 = any_extend t6
163163
; CHECK: t9: ch,glue = CopyToReg t0, Register:nxv8i16 $z0, t7
164164
; CHECK: t10: ch = AArch64ISD::RET_GLUE t9, Register:nxv8i16 $z0, t9:1
@@ -168,7 +168,7 @@ define <8 x i8> @extract_small_fixed_from_big_fixed(<16 x i8> %a) #0 {
168168
; CHECK: t0: ch,glue = EntryToken
169169
; CHECK: t2: v16i8,ch = CopyFromReg t0, Register:v16i8 %0
170170
; CHECK: t4: v4i8 = extract_subvector t2, Constant:i64<0>
171-
; CHECK: t6: nxv8i8 = insert_subvector undef:nxv8i8, t4, Constant:i64<0>
171+
; CHECK: t6: nxv8i8 = insert_subvector poison:nxv8i8, t4, Constant:i64<0>
172172
; CHECK: t7: nxv8i16 = any_extend t6
173173
; CHECK: t9: ch,glue = CopyToReg t0, Register:nxv8i16 $z0, t7
174174
; CHECK: t10: ch = AArch64ISD::RET_GLUE t9, Register:nxv8i16 $z0, t9:1
@@ -185,7 +185,7 @@ define <vscale x 8 x i8> @extract_small_scalable_from_big_fixed(<16 x i8> %a) #0
185185
; CHECK: t0: ch,glue = EntryToken
186186
; CHECK: t2: nxv16i8,ch = CopyFromReg t0, Register:nxv16i8 %0
187187
; CHECK: t4: v4i8 = extract_subvector t2, Constant:i64<0>
188-
; CHECK: t6: v8i8 = insert_subvector undef:v8i8, t4, Constant:i64<0>
188+
; CHECK: t6: v8i8 = insert_subvector poison:v8i8, t4, Constant:i64<0>
189189
; CHECK: t8: ch,glue = CopyToReg t0, Register:v8i8 $d0, t6
190190
; CHECK: t9: ch = AArch64ISD::RET_GLUE t8, Register:v8i8 $d0, t8:1
191191

@@ -208,7 +208,7 @@ define <8 x i8> @extract_small_fixed_from_big_scalable(<vscale x 16 x i8> %a) #0
208208
; CHECK: t0: ch,glue = EntryToken
209209
; CHECK: t2: nxv16i8,ch = CopyFromReg t0, Register:nxv16i8 %0
210210
; CHECK: t4: v4i8 = extract_subvector t2, Constant:i64<0>
211-
; CHECK: t6: nxv8i8 = insert_subvector undef:nxv8i8, t4, Constant:i64<0>
211+
; CHECK: t6: nxv8i8 = insert_subvector poison:nxv8i8, t4, Constant:i64<0>
212212
; CHECK: t7: nxv8i16 = any_extend t6
213213
; CHECK: t9: ch,glue = CopyToReg t0, Register:nxv8i16 $z0, t7
214214
; CHECK: t10: ch = AArch64ISD::RET_GLUE t9, Register:nxv8i16 $z0, t9:1
@@ -233,7 +233,7 @@ define <vscale x 8 x i8> @extract_small_scalable_from_big_scalable_1(<vscale x 1
233233
; CHECK: t0: ch,glue = EntryToken
234234
; CHECK: t2: nxv16i8,ch = CopyFromReg t0, Register:nxv16i8 %0
235235
; CHECK: t4: nxv4i8 = extract_subvector t2, Constant:i64<0>
236-
; CHECK: t6: nxv8i8 = insert_subvector undef:nxv8i8, t4, Constant:i64<0>
236+
; CHECK: t6: nxv8i8 = insert_subvector poison:nxv8i8, t4, Constant:i64<0>
237237
; CHECK: t7: nxv8i16 = any_extend t6
238238
; CHECK: t9: ch,glue = CopyToReg t0, Register:nxv8i16 $z0, t7
239239
; CHECK: t10: ch = AArch64ISD::RET_GLUE t9, Register:nxv8i16 $z0, t9:1
@@ -258,7 +258,7 @@ define <vscale x 8 x i8> @extract_small_scalable_from_big_scalable_2(<vscale x 1
258258
; CHECK: t0: ch,glue = EntryToken
259259
; CHECK: t2: nxv16i8,ch = CopyFromReg t0, Register:nxv16i8 %0
260260
; CHECK: t4: v4i8 = extract_subvector t2, Constant:i64<0>
261-
; CHECK: t6: v16i8 = insert_subvector undef:v16i8, t4, Constant:i64<0>
261+
; CHECK: t6: v16i8 = insert_subvector poison:v16i8, t4, Constant:i64<0>
262262
; CHECK: t8: ch,glue = CopyToReg t0, Register:v16i8 $q0, t6
263263
; CHECK: t9: ch = AArch64ISD::RET_GLUE t8, Register:v16i8 $q0, t8:1
264264

@@ -285,15 +285,15 @@ define <16 x i8> @extract_fixed_from_scalable(<vscale x 16 x i8> %a) #0 {
285285
; CHECK: t0: ch,glue = EntryToken
286286
; CHECK: t2: v16i8,ch = CopyFromReg t0, Register:v16i8 %0
287287
; CHECK: t4: v4i8 = extract_subvector t2, Constant:i64<0>
288-
; CHECK: t6: nxv16i8 = insert_subvector undef:nxv16i8, t4, Constant:i64<0>
288+
; CHECK: t6: nxv16i8 = insert_subvector poison:nxv16i8, t4, Constant:i64<0>
289289
; CHECK: t8: ch,glue = CopyToReg t0, Register:nxv16i8 $z0, t6
290290
; CHECK: t9: ch = AArch64ISD::RET_GLUE t8, Register:nxv16i8 $z0, t8:1
291291

292292
; CHECK: Optimized lowered selection DAG: %bb.0 'insert_fixed_into_scalable:'
293293
; CHECK: SelectionDAG has 9 nodes:
294294
; CHECK: t0: ch,glue = EntryToken
295295
; CHECK: t2: v16i8,ch = CopyFromReg t0, Register:v16i8 %0
296-
; CHECK: t10: nxv16i8 = insert_subvector undef:nxv16i8, t2, Constant:i64<0>
296+
; CHECK: t10: nxv16i8 = insert_subvector poison:nxv16i8, t2, Constant:i64<0>
297297
; CHECK: t8: ch,glue = CopyToReg t0, Register:nxv16i8 $z0, t10
298298
; CHECK: t9: ch = AArch64ISD::RET_GLUE t8, Register:nxv16i8 $z0, t8:1
299299

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