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[AMDGPU] Replace gfx940 and gfx941 with gfx942 in llvm (#126763)
gfx940 and gfx941 are no longer supported. This is one of a series of PRs to remove them from the code base. This PR removes all non-documentation occurrences of gfx940/gfx941 from the llvm directory, and the remaining occurrences in clang. Documentation changes will follow. For SWDEV-512631
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‎clang/test/Misc/target-invalid-cpu-note/amdgcn.c

Lines changed: 0 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -45,8 +45,6 @@
4545
// CHECK-SAME: {{^}}, gfx909
4646
// CHECK-SAME: {{^}}, gfx90a
4747
// CHECK-SAME: {{^}}, gfx90c
48-
// CHECK-SAME: {{^}}, gfx940
49-
// CHECK-SAME: {{^}}, gfx941
5048
// CHECK-SAME: {{^}}, gfx942
5149
// CHECK-SAME: {{^}}, gfx950
5250
// CHECK-SAME: {{^}}, gfx1010

‎llvm/docs/AMDGPUUsage.rst

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -2232,7 +2232,7 @@ The AMDGPU backend uses the following ELF header:
22322232
``EF_AMDGPU_MACH_AMDGCN_GFX1035`` 0x03d ``gfx1035``
22332233
``EF_AMDGPU_MACH_AMDGCN_GFX1034`` 0x03e ``gfx1034``
22342234
``EF_AMDGPU_MACH_AMDGCN_GFX90A`` 0x03f ``gfx90a``
2235-
``EF_AMDGPU_MACH_AMDGCN_GFX940`` 0x040 ``gfx940``
2235+
*reserved* 0x040 Reserved.
22362236
``EF_AMDGPU_MACH_AMDGCN_GFX1100`` 0x041 ``gfx1100``
22372237
``EF_AMDGPU_MACH_AMDGCN_GFX1013`` 0x042 ``gfx1013``
22382238
``EF_AMDGPU_MACH_AMDGCN_GFX1150`` 0x043 ``gfx1150``
@@ -2243,7 +2243,7 @@ The AMDGPU backend uses the following ELF header:
22432243
``EF_AMDGPU_MACH_AMDGCN_GFX1200`` 0x048 ``gfx1200``
22442244
*reserved* 0x049 Reserved.
22452245
``EF_AMDGPU_MACH_AMDGCN_GFX1151`` 0x04a ``gfx1151``
2246-
``EF_AMDGPU_MACH_AMDGCN_GFX941`` 0x04b ``gfx941``
2246+
*reserved* 0x04b Reserved.
22472247
``EF_AMDGPU_MACH_AMDGCN_GFX942`` 0x04c ``gfx942``
22482248
*reserved* 0x04d Reserved.
22492249
``EF_AMDGPU_MACH_AMDGCN_GFX1201`` 0x04e ``gfx1201``

‎llvm/include/llvm/BinaryFormat/ELF.h

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -814,7 +814,7 @@ enum : unsigned {
814814
EF_AMDGPU_MACH_AMDGCN_GFX1035 = 0x03d,
815815
EF_AMDGPU_MACH_AMDGCN_GFX1034 = 0x03e,
816816
EF_AMDGPU_MACH_AMDGCN_GFX90A = 0x03f,
817-
EF_AMDGPU_MACH_AMDGCN_GFX940 = 0x040,
817+
EF_AMDGPU_MACH_AMDGCN_RESERVED_0X40 = 0x040,
818818
EF_AMDGPU_MACH_AMDGCN_GFX1100 = 0x041,
819819
EF_AMDGPU_MACH_AMDGCN_GFX1013 = 0x042,
820820
EF_AMDGPU_MACH_AMDGCN_GFX1150 = 0x043,
@@ -825,7 +825,7 @@ enum : unsigned {
825825
EF_AMDGPU_MACH_AMDGCN_GFX1200 = 0x048,
826826
EF_AMDGPU_MACH_AMDGCN_RESERVED_0X49 = 0x049,
827827
EF_AMDGPU_MACH_AMDGCN_GFX1151 = 0x04a,
828-
EF_AMDGPU_MACH_AMDGCN_GFX941 = 0x04b,
828+
EF_AMDGPU_MACH_AMDGCN_RESERVED_0X4B = 0x04b,
829829
EF_AMDGPU_MACH_AMDGCN_GFX942 = 0x04c,
830830
EF_AMDGPU_MACH_AMDGCN_RESERVED_0X4D = 0x04d,
831831
EF_AMDGPU_MACH_AMDGCN_GFX1201 = 0x04e,

‎llvm/include/llvm/IR/IntrinsicsAMDGPU.td

Lines changed: 28 additions & 28 deletions
Large diffs are not rendered by default.

‎llvm/include/llvm/TargetParser/TargetParser.h

Lines changed: 0 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -83,8 +83,6 @@ enum GPUKind : uint32_t {
8383
GK_GFX909 = 65,
8484
GK_GFX90A = 66,
8585
GK_GFX90C = 67,
86-
GK_GFX940 = 68,
87-
GK_GFX941 = 69,
8886
GK_GFX942 = 70,
8987
GK_GFX950 = 71,
9088

‎llvm/lib/Object/ELFObjectFile.cpp

Lines changed: 0 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -545,10 +545,6 @@ StringRef ELFObjectFileBase::getAMDGPUCPUName() const {
545545
return "gfx90a";
546546
case ELF::EF_AMDGPU_MACH_AMDGCN_GFX90C:
547547
return "gfx90c";
548-
case ELF::EF_AMDGPU_MACH_AMDGCN_GFX940:
549-
return "gfx940";
550-
case ELF::EF_AMDGPU_MACH_AMDGCN_GFX941:
551-
return "gfx941";
552548
case ELF::EF_AMDGPU_MACH_AMDGCN_GFX942:
553549
return "gfx942";
554550
case ELF::EF_AMDGPU_MACH_AMDGCN_GFX950:

‎llvm/lib/ObjectYAML/ELFYAML.cpp

Lines changed: 0 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -609,8 +609,6 @@ void ScalarBitSetTraits<ELFYAML::ELF_EF>::bitset(IO &IO,
609609
BCaseMask(EF_AMDGPU_MACH_AMDGCN_GFX909, EF_AMDGPU_MACH);
610610
BCaseMask(EF_AMDGPU_MACH_AMDGCN_GFX90A, EF_AMDGPU_MACH);
611611
BCaseMask(EF_AMDGPU_MACH_AMDGCN_GFX90C, EF_AMDGPU_MACH);
612-
BCaseMask(EF_AMDGPU_MACH_AMDGCN_GFX940, EF_AMDGPU_MACH);
613-
BCaseMask(EF_AMDGPU_MACH_AMDGCN_GFX941, EF_AMDGPU_MACH);
614612
BCaseMask(EF_AMDGPU_MACH_AMDGCN_GFX942, EF_AMDGPU_MACH);
615613
BCaseMask(EF_AMDGPU_MACH_AMDGCN_GFX950, EF_AMDGPU_MACH);
616614
BCaseMask(EF_AMDGPU_MACH_AMDGCN_GFX1010, EF_AMDGPU_MACH);

‎llvm/lib/Target/AMDGPU/AMDGPU.td

Lines changed: 0 additions & 22 deletions
Original file line numberDiff line numberDiff line change
@@ -1619,28 +1619,6 @@ def FeatureISAVersion9_5_Common : FeatureSet<
16191619
FeatureAtomicBufferPkAddBF16Inst
16201620
])>;
16211621

1622-
def FeatureISAVersion9_4_0 : FeatureSet<
1623-
!listconcat(FeatureISAVersion9_4_Common.Features,
1624-
[
1625-
FeatureAddressableLocalMemorySize65536,
1626-
FeatureForceStoreSC0SC1,
1627-
FeatureFP8Insts,
1628-
FeatureFP8ConversionInsts,
1629-
FeatureCvtFP8VOP1Bug,
1630-
FeatureXF32Insts
1631-
])>;
1632-
1633-
def FeatureISAVersion9_4_1 : FeatureSet<
1634-
!listconcat(FeatureISAVersion9_4_Common.Features,
1635-
[
1636-
FeatureAddressableLocalMemorySize65536,
1637-
FeatureForceStoreSC0SC1,
1638-
FeatureFP8Insts,
1639-
FeatureFP8ConversionInsts,
1640-
FeatureCvtFP8VOP1Bug,
1641-
FeatureXF32Insts
1642-
])>;
1643-
16441622
def FeatureISAVersion9_4_2 : FeatureSet<
16451623
!listconcat(FeatureISAVersion9_4_Common.Features,
16461624
[

‎llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -4295,7 +4295,7 @@ AMDGPUInstructionSelector::selectVOP3PModsImpl(
42954295
// TODO: Handle G_FSUB 0 as fneg
42964296

42974297
// TODO: Match op_sel through g_build_vector_trunc and g_shuffle_vector.
4298-
(void)IsDOT; // DOTs do not use OPSEL on gfx940+, check ST.hasDOTOpSelHazard()
4298+
(void)IsDOT; // DOTs do not use OPSEL on gfx942+, check ST.hasDOTOpSelHazard()
42994299

43004300
// Packed instructions do not have abs modifiers.
43014301
Mods |= SISrcMods::OP_SEL_1;

‎llvm/lib/Target/AMDGPU/DSInstructions.td

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1773,7 +1773,7 @@ def DS_READ_B128_vi : DS_Real_vi<0xff, DS_READ_B128>;
17731773
def DS_ADD_F64_vi : DS_Real_vi<0x5c, DS_ADD_F64>;
17741774
def DS_ADD_RTN_F64_vi : DS_Real_vi<0x7c, DS_ADD_RTN_F64>;
17751775

1776-
// GFX940+.
1776+
// GFX942+.
17771777
def DS_PK_ADD_F16_vi : DS_Real_vi<0x17, DS_PK_ADD_F16>;
17781778
def DS_PK_ADD_RTN_F16_vi : DS_Real_vi<0xb7, DS_PK_ADD_RTN_F16>;
17791779
def DS_PK_ADD_BF16_vi : DS_Real_vi<0x18, DS_PK_ADD_BF16>;

‎llvm/lib/Target/AMDGPU/FLATInstructions.td

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -814,7 +814,7 @@ defm FLAT_ATOMIC_FMAX : FLAT_Atomic_Pseudo <"flat_atomic_fmax",
814814

815815
} // End SubtargetPredicate = isGFX7GFX10GFX11
816816

817-
// GFX940-, GFX11-only flat instructions.
817+
// GFX942-, GFX11-only flat instructions.
818818
let SubtargetPredicate = HasFlatAtomicFaddF32Inst in {
819819
defm FLAT_ATOMIC_ADD_F32 : FLAT_Atomic_Pseudo<"flat_atomic_add_f32", VGPR_32, f32>;
820820
} // End SubtargetPredicate = HasFlatAtomicFaddF32Inst
@@ -2076,7 +2076,7 @@ defm SCRATCH_STORE_DWORDX3 : FLAT_Real_AllAddr_SVE_vi <0x1e>;
20762076
defm SCRATCH_STORE_DWORDX4 : FLAT_Real_AllAddr_SVE_vi <0x1f>;
20772077

20782078
let SubtargetPredicate = isGFX8GFX9NotGFX940 in {
2079-
// These instructions are encoded differently on gfx90* and gfx940.
2079+
// These instructions are encoded differently on gfx90* and gfx94*.
20802080
defm GLOBAL_ATOMIC_ADD_F32 : FLAT_Global_Real_Atomics_vi <0x04d, 0>;
20812081
defm GLOBAL_ATOMIC_PK_ADD_F16 : FLAT_Global_Real_Atomics_vi <0x04e, 0>;
20822082
}

‎llvm/lib/Target/AMDGPU/GCNHazardRecognizer.cpp

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -2292,7 +2292,7 @@ GFX940_SMFMA_N_PassWritesVGPROverlappedSrcABWaitStates(int NumPasses) {
22922292

22932293
static int GFX940_XDL_N_PassWritesVGPROverlappedSrcABWaitStates(int NumPasses,
22942294
bool IsGFX950) {
2295-
// xdl def cycles | gfx940 | gfx950
2295+
// xdl def cycles | gfx942 | gfx950
22962296
// 2 pass | 5 5
22972297
// 4 pass | 7 8
22982298
// 8 pass | 11 12
@@ -2600,7 +2600,7 @@ static int GFX940_SMFMA_N_PassWriteVgprVALUWawWaitStates(int NumPasses) {
26002600

26012601
static int GFX940_XDL_N_PassWriteVgprVALUWawWaitStates(int NumPasses,
26022602
bool IsGFX950) {
2603-
// xdl def cycles | gfx940 | gfx950
2603+
// xdl def cycles | gfx942 | gfx950
26042604
// 2 pass | 5 5
26052605
// 4 pass | 7 8
26062606
// 8 pass | 11 12
@@ -2610,7 +2610,7 @@ static int GFX940_XDL_N_PassWriteVgprVALUWawWaitStates(int NumPasses,
26102610

26112611
static int GFX940_XDL_N_PassWriteVgprVALUMemExpReadWaitStates(int NumPasses,
26122612
bool IsGFX950) {
2613-
// xdl def cycles | gfx940 | gfx950
2613+
// xdl def cycles | gfx942 | gfx950
26142614
// 2 pass | 5 5
26152615
// 4 pass | 7 8
26162616
// 8 pass | 11 12

‎llvm/lib/Target/AMDGPU/GCNProcessors.td

Lines changed: 3 additions & 11 deletions
Original file line numberDiff line numberDiff line change
@@ -192,15 +192,7 @@ def : ProcessorModel<"gfx90c", SIQuarterSpeedModel,
192192
FeatureISAVersion9_0_C.Features
193193
>;
194194

195-
def : ProcessorModel<"gfx940", SIDPGFX940FullSpeedModel,
196-
FeatureISAVersion9_4_0.Features
197-
>;
198-
199-
def : ProcessorModel<"gfx941", SIDPGFX940FullSpeedModel,
200-
FeatureISAVersion9_4_1.Features
201-
>;
202-
203-
def : ProcessorModel<"gfx942", SIDPGFX940FullSpeedModel,
195+
def : ProcessorModel<"gfx942", SIDPGFX942FullSpeedModel,
204196
FeatureISAVersion9_4_2.Features
205197
>;
206198

@@ -213,8 +205,8 @@ def : ProcessorModel<"gfx9-generic", SIQuarterSpeedModel,
213205
FeatureISAVersion9_Generic.Features
214206
>;
215207

216-
// [gfx940, gfx941, gfx942]
217-
def : ProcessorModel<"gfx9-4-generic", SIDPGFX940FullSpeedModel,
208+
// [gfx942]
209+
def : ProcessorModel<"gfx9-4-generic", SIDPGFX942FullSpeedModel,
218210
FeatureISAVersion9_4_Generic.Features
219211
>;
220212

‎llvm/lib/Target/AMDGPU/GCNSubtarget.h

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1297,11 +1297,11 @@ class GCNSubtarget final : public AMDGPUGenSubtargetInfo,
12971297

12981298
bool hasPackedTID() const { return HasPackedTID; }
12991299

1300-
// GFX940 is a derivation to GFX90A. hasGFX940Insts() being true implies that
1300+
// GFX94* is a derivation to GFX90A. hasGFX940Insts() being true implies that
13011301
// hasGFX90AInsts is also true.
13021302
bool hasGFX940Insts() const { return GFX940Insts; }
13031303

1304-
// GFX950 is a derivation to GFX940. hasGFX950Insts() implies that
1304+
// GFX950 is a derivation to GFX94*. hasGFX950Insts() implies that
13051305
// hasGFX940Insts and hasGFX90AInsts are also true.
13061306
bool hasGFX950Insts() const { return GFX950Insts; }
13071307

‎llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUTargetStreamer.cpp

Lines changed: 0 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -93,8 +93,6 @@ StringRef AMDGPUTargetStreamer::getArchNameFromElfMach(unsigned ElfMach) {
9393
case ELF::EF_AMDGPU_MACH_AMDGCN_GFX909: AK = GK_GFX909; break;
9494
case ELF::EF_AMDGPU_MACH_AMDGCN_GFX90A: AK = GK_GFX90A; break;
9595
case ELF::EF_AMDGPU_MACH_AMDGCN_GFX90C: AK = GK_GFX90C; break;
96-
case ELF::EF_AMDGPU_MACH_AMDGCN_GFX940: AK = GK_GFX940; break;
97-
case ELF::EF_AMDGPU_MACH_AMDGCN_GFX941: AK = GK_GFX941; break;
9896
case ELF::EF_AMDGPU_MACH_AMDGCN_GFX942: AK = GK_GFX942; break;
9997
case ELF::EF_AMDGPU_MACH_AMDGCN_GFX950: AK = GK_GFX950; break;
10098
case ELF::EF_AMDGPU_MACH_AMDGCN_GFX1010: AK = GK_GFX1010; break;
@@ -180,8 +178,6 @@ unsigned AMDGPUTargetStreamer::getElfMach(StringRef GPU) {
180178
case GK_GFX909: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX909;
181179
case GK_GFX90A: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX90A;
182180
case GK_GFX90C: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX90C;
183-
case GK_GFX940: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX940;
184-
case GK_GFX941: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX941;
185181
case GK_GFX942: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX942;
186182
case GK_GFX950: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX950;
187183
case GK_GFX1010: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX1010;

‎llvm/lib/Target/AMDGPU/SIDefines.h

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -542,7 +542,7 @@ enum Id { // HwRegCode, (6) [5:0]
542542
ID_EXCP_FLAG_USER = 18,
543543
ID_TRAP_CTRL = 19,
544544

545-
// GFX940 specific registers
545+
// GFX94* specific registers
546546
ID_XCC_ID = 20,
547547
ID_SQ_PERF_SNAPSHOT_DATA = 21,
548548
ID_SQ_PERF_SNAPSHOT_DATA1 = 22,

‎llvm/lib/Target/AMDGPU/SIISelLowering.cpp

Lines changed: 10 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -16823,39 +16823,39 @@ SITargetLowering::shouldExpandAtomicRMWInIR(AtomicRMWInst *RMW) const {
1682316823
// safe. The message phrasing also should be better.
1682416824
if (globalMemoryFPAtomicIsLegal(*Subtarget, RMW, HasSystemScope)) {
1682516825
if (AS == AMDGPUAS::FLAT_ADDRESS) {
16826-
// gfx940, gfx12
16826+
// gfx942, gfx12
1682716827
if (Subtarget->hasAtomicFlatPkAdd16Insts() && isV2F16OrV2BF16(Ty))
1682816828
return ReportUnsafeHWInst(AtomicExpansionKind::None);
1682916829
} else if (AMDGPU::isExtendedGlobalAddrSpace(AS)) {
16830-
// gfx90a, gfx940, gfx12
16830+
// gfx90a, gfx942, gfx12
1683116831
if (Subtarget->hasAtomicBufferGlobalPkAddF16Insts() && isV2F16(Ty))
1683216832
return ReportUnsafeHWInst(AtomicExpansionKind::None);
1683316833

16834-
// gfx940, gfx12
16834+
// gfx942, gfx12
1683516835
if (Subtarget->hasAtomicGlobalPkAddBF16Inst() && isV2BF16(Ty))
1683616836
return ReportUnsafeHWInst(AtomicExpansionKind::None);
1683716837
} else if (AS == AMDGPUAS::BUFFER_FAT_POINTER) {
16838-
// gfx90a, gfx940, gfx12
16838+
// gfx90a, gfx942, gfx12
1683916839
if (Subtarget->hasAtomicBufferGlobalPkAddF16Insts() && isV2F16(Ty))
1684016840
return ReportUnsafeHWInst(AtomicExpansionKind::None);
1684116841

16842-
// While gfx90a/gfx940 supports v2bf16 for global/flat, it does not for
16842+
// While gfx90a/gfx942 supports v2bf16 for global/flat, it does not for
1684316843
// buffer. gfx12 does have the buffer version.
1684416844
if (Subtarget->hasAtomicBufferPkAddBF16Inst() && isV2BF16(Ty))
1684516845
return ReportUnsafeHWInst(AtomicExpansionKind::None);
1684616846
}
1684716847

16848-
// global and flat atomic fadd f64: gfx90a, gfx940.
16848+
// global and flat atomic fadd f64: gfx90a, gfx942.
1684916849
if (Subtarget->hasFlatBufferGlobalAtomicFaddF64Inst() && Ty->isDoubleTy())
1685016850
return ReportUnsafeHWInst(AtomicExpansionKind::None);
1685116851

1685216852
if (AS != AMDGPUAS::FLAT_ADDRESS) {
1685316853
if (Ty->isFloatTy()) {
16854-
// global/buffer atomic fadd f32 no-rtn: gfx908, gfx90a, gfx940,
16854+
// global/buffer atomic fadd f32 no-rtn: gfx908, gfx90a, gfx942,
1685516855
// gfx11+.
1685616856
if (RMW->use_empty() && Subtarget->hasAtomicFaddNoRtnInsts())
1685716857
return ReportUnsafeHWInst(AtomicExpansionKind::None);
16858-
// global/buffer atomic fadd f32 rtn: gfx90a, gfx940, gfx11+.
16858+
// global/buffer atomic fadd f32 rtn: gfx90a, gfx942, gfx11+.
1685916859
if (!RMW->use_empty() && Subtarget->hasAtomicFaddRtnInsts())
1686016860
return ReportUnsafeHWInst(AtomicExpansionKind::None);
1686116861
} else {
@@ -16867,7 +16867,7 @@ SITargetLowering::shouldExpandAtomicRMWInIR(AtomicRMWInst *RMW) const {
1686716867
}
1686816868
}
1686916869

16870-
// flat atomic fadd f32: gfx940, gfx11+.
16870+
// flat atomic fadd f32: gfx942, gfx11+.
1687116871
if (AS == AMDGPUAS::FLAT_ADDRESS && Ty->isFloatTy()) {
1687216872
if (Subtarget->hasFlatAtomicFaddF32Inst())
1687316873
return ReportUnsafeHWInst(AtomicExpansionKind::None);
@@ -16906,7 +16906,7 @@ SITargetLowering::shouldExpandAtomicRMWInIR(AtomicRMWInst *RMW) const {
1690616906
// float, double restored in gfx10.
1690716907
// double removed again in gfx11, so only f32 for gfx11/gfx12.
1690816908
//
16909-
// For gfx9, gfx90a and gfx940 support f64 for global (same as fadd), but
16909+
// For gfx9, gfx90a and gfx942 support f64 for global (same as fadd), but
1691016910
// no f32.
1691116911
if (AS == AMDGPUAS::FLAT_ADDRESS) {
1691216912
if (Subtarget->hasAtomicFMinFMaxF32FlatInsts() && Ty->isFloatTy())

‎llvm/lib/Target/AMDGPU/SIMemoryLegalizer.cpp

Lines changed: 0 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -492,7 +492,6 @@ class SIGfx940CacheControl : public SIGfx90ACacheControl {
492492
}
493493

494494
public:
495-
496495
SIGfx940CacheControl(const GCNSubtarget &ST) : SIGfx90ACacheControl(ST) {};
497496

498497
bool enableLoadCacheBypass(const MachineBasicBlock::iterator &MI,

‎llvm/lib/Target/AMDGPU/SISchedule.td

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -94,7 +94,7 @@ class SISchedMachineModel : SchedMachineModel {
9494
def SIFullSpeedModel : SISchedMachineModel;
9595
def SIQuarterSpeedModel : SISchedMachineModel;
9696
def SIDPFullSpeedModel : SISchedMachineModel;
97-
def SIDPGFX940FullSpeedModel : SISchedMachineModel;
97+
def SIDPGFX942FullSpeedModel : SISchedMachineModel;
9898
def SIDPGFX950FullSpeedModel : SISchedMachineModel;
9999
def GFX10SpeedModel : SISchedMachineModel;
100100
def GFX11SpeedModel : SISchedMachineModel;
@@ -276,7 +276,7 @@ def : InstRW<[Write8PassDGEMM, MIMFMARead], (instregex "^V_MFMA_.64_16X16X")>;
276276

277277
} // End SchedModel = SIDPFullSpeedModel
278278

279-
let SchedModel = SIDPGFX940FullSpeedModel in {
279+
let SchedModel = SIDPGFX942FullSpeedModel in {
280280

281281
defm : SICommonWriteRes;
282282

@@ -308,7 +308,7 @@ def : InstRW<[Write8PassDGEMM, MIMFMARead], (instregex "^V_MFMA_.64_16X16X")>;
308308
def : InstRW<[Write4PassMAI, MIMFMARead], (instregex "^V_SMFMAC_.32_16X16X")>;
309309
def : InstRW<[Write8PassMAI, MIMFMARead], (instregex "^V_SMFMAC_.32_32X32X")>;
310310

311-
} // End SchedModel = SIDPGFX940FullSpeedModel
311+
} // End SchedModel = SIDPGFX942FullSpeedModel
312312

313313

314314
let SchedModel = SIDPGFX950FullSpeedModel in {

‎llvm/lib/Target/AMDGPU/Utils/AMDGPUAsmUtils.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -216,7 +216,7 @@ static constexpr CustomOperand Operands[] = {
216216
{{"HW_REG_SCRATCH_BASE_HI"}, ID_FLAT_SCR_HI, isGFX12Plus},
217217
{{"HW_REG_SHADER_CYCLES_LO"}, ID_SHADER_CYCLES, isGFX12Plus},
218218

219-
// GFX940 specific registers
219+
// GFX942 specific registers
220220
{{"HW_REG_XCC_ID"}, ID_XCC_ID, isGFX940},
221221
{{"HW_REG_SQ_PERF_SNAPSHOT_DATA"}, ID_SQ_PERF_SNAPSHOT_DATA, isGFX940},
222222
{{"HW_REG_SQ_PERF_SNAPSHOT_DATA1"}, ID_SQ_PERF_SNAPSHOT_DATA1, isGFX940},

‎llvm/lib/TargetParser/TargetParser.cpp

Lines changed: 0 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -104,8 +104,6 @@ constexpr GPUInfo AMDGCNGPUs[] = {
104104
{{"gfx909"}, {"gfx909"}, GK_GFX909, FEATURE_FAST_FMA_F32|FEATURE_FAST_DENORMAL_F32|FEATURE_XNACK},
105105
{{"gfx90a"}, {"gfx90a"}, GK_GFX90A, FEATURE_FAST_FMA_F32|FEATURE_FAST_DENORMAL_F32|FEATURE_XNACK|FEATURE_SRAMECC},
106106
{{"gfx90c"}, {"gfx90c"}, GK_GFX90C, FEATURE_FAST_FMA_F32|FEATURE_FAST_DENORMAL_F32|FEATURE_XNACK},
107-
{{"gfx940"}, {"gfx940"}, GK_GFX940, FEATURE_FAST_FMA_F32|FEATURE_FAST_DENORMAL_F32|FEATURE_XNACK|FEATURE_SRAMECC},
108-
{{"gfx941"}, {"gfx941"}, GK_GFX941, FEATURE_FAST_FMA_F32|FEATURE_FAST_DENORMAL_F32|FEATURE_XNACK|FEATURE_SRAMECC},
109107
{{"gfx942"}, {"gfx942"}, GK_GFX942, FEATURE_FAST_FMA_F32|FEATURE_FAST_DENORMAL_F32|FEATURE_XNACK|FEATURE_SRAMECC},
110108
{{"gfx950"}, {"gfx950"}, GK_GFX950, FEATURE_FAST_FMA_F32|FEATURE_FAST_DENORMAL_F32|FEATURE_XNACK|FEATURE_SRAMECC},
111109
{{"gfx1010"}, {"gfx1010"}, GK_GFX1010, FEATURE_FAST_FMA_F32|FEATURE_FAST_DENORMAL_F32|FEATURE_WAVE32|FEATURE_XNACK|FEATURE_WGP},
@@ -260,8 +258,6 @@ AMDGPU::IsaVersion AMDGPU::getIsaVersion(StringRef GPU) {
260258
case GK_GFX909: return {9, 0, 9};
261259
case GK_GFX90A: return {9, 0, 10};
262260
case GK_GFX90C: return {9, 0, 12};
263-
case GK_GFX940: return {9, 4, 0};
264-
case GK_GFX941: return {9, 4, 1};
265261
case GK_GFX942: return {9, 4, 2};
266262
case GK_GFX950: return {9, 5, 0};
267263
case GK_GFX1010: return {10, 1, 0};
@@ -506,8 +502,6 @@ void AMDGPU::fillAMDGPUFeatureMap(StringRef GPU, const Triple &T,
506502
Features["gfx950-insts"] = true;
507503
[[fallthrough]];
508504
case GK_GFX942:
509-
case GK_GFX941:
510-
case GK_GFX940:
511505
Features["fp8-insts"] = true;
512506
Features["fp8-conversion-insts"] = true;
513507
if (Kind != GK_GFX950)

‎llvm/test/CodeGen/AMDGPU/preload-implicit-kernargs-debug-info.ll

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,4 +1,4 @@
1-
; RUN: opt -mtriple=amdgcn-amd-amdhsa -mcpu=gfx940 -passes='amdgpu-attributor,function(amdgpu-lower-kernel-arguments)' -amdgpu-kernarg-preload-count=16 -S < %s 2>&1 \
1+
; RUN: opt -mtriple=amdgcn-amd-amdhsa -mcpu=gfx942 -passes='amdgpu-attributor,function(amdgpu-lower-kernel-arguments)' -amdgpu-kernarg-preload-count=16 -S < %s 2>&1 \
22
; RUN: | FileCheck --match-full-lines --implicit-check-not='declare' %s
33

44
; Confirms we do not leave behind a declaration which references the same

‎llvm/tools/llvm-readobj/ELFDumper.cpp

Lines changed: 0 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1624,8 +1624,6 @@ const EnumEntry<unsigned> ElfHeaderMipsFlags[] = {
16241624
ENUM_ENT(EF_AMDGPU_MACH_AMDGCN_GFX909, "gfx909"), \
16251625
ENUM_ENT(EF_AMDGPU_MACH_AMDGCN_GFX90A, "gfx90a"), \
16261626
ENUM_ENT(EF_AMDGPU_MACH_AMDGCN_GFX90C, "gfx90c"), \
1627-
ENUM_ENT(EF_AMDGPU_MACH_AMDGCN_GFX940, "gfx940"), \
1628-
ENUM_ENT(EF_AMDGPU_MACH_AMDGCN_GFX941, "gfx941"), \
16291627
ENUM_ENT(EF_AMDGPU_MACH_AMDGCN_GFX942, "gfx942"), \
16301628
ENUM_ENT(EF_AMDGPU_MACH_AMDGCN_GFX950, "gfx950"), \
16311629
ENUM_ENT(EF_AMDGPU_MACH_AMDGCN_GFX1010, "gfx1010"), \

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