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AMDGPU: Replace some float undef test uses with poison
1 parent 1eb5588 commit 80e70c7

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63 files changed

+179
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lines changed

‎llvm/test/CodeGen/AMDGPU/GlobalISel/i1-copy.ll

+2-2
Original file line numberDiff line numberDiff line change
@@ -22,7 +22,7 @@ main_body:
2222
%vcc = icmp eq i32 %val, 2
2323
%a = select i1 %vcc, float %a0, float %a1
2424
%b = select i1 %vcc, float %b0, float %b1
25-
call void @llvm.amdgcn.exp.f32(i32 0, i32 15, float %a, float %b, float undef, float undef, i1 true, i1 true)
25+
call void @llvm.amdgcn.exp.f32(i32 0, i32 15, float %a, float %b, float poison, float poison, i1 true, i1 true)
2626
ret void
2727
}
2828

@@ -52,7 +52,7 @@ main_body:
5252
%uniform_i1 = icmp eq i32 %val, 2
5353
%a = select i1 %uniform_i1, float %a0, float %a1
5454
%b = select i1 %uniform_i1, float %b0, float %b1
55-
call void @llvm.amdgcn.exp.f32(i32 0, i32 15, float %a, float %b, float undef, float undef, i1 true, i1 true)
55+
call void @llvm.amdgcn.exp.f32(i32 0, i32 15, float %a, float %b, float poison, float poison, i1 true, i1 true)
5656
ret void
5757
}
5858

‎llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-amdgpu_vs.ll

+3-3
Original file line numberDiff line numberDiff line change
@@ -10,7 +10,7 @@ define amdgpu_vs void @test_f32_inreg(float inreg %arg0) {
1010
; CHECK-NEXT: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
1111
; CHECK-NEXT: G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.exp), 32, 15, [[COPY]](s32), [[DEF]](s32), [[DEF]](s32), [[DEF]](s32), 0, 0
1212
; CHECK-NEXT: S_ENDPGM 0
13-
call void @llvm.amdgcn.exp.f32(i32 32, i32 15, float %arg0, float undef, float undef, float undef, i1 false, i1 false) #0
13+
call void @llvm.amdgcn.exp.f32(i32 32, i32 15, float %arg0, float poison, float poison, float poison, i1 false, i1 false) #0
1414
ret void
1515
}
1616

@@ -23,7 +23,7 @@ define amdgpu_vs void @test_f32(float %arg0) {
2323
; CHECK-NEXT: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
2424
; CHECK-NEXT: G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.exp), 32, 15, [[COPY]](s32), [[DEF]](s32), [[DEF]](s32), [[DEF]](s32), 0, 0
2525
; CHECK-NEXT: S_ENDPGM 0
26-
call void @llvm.amdgcn.exp.f32(i32 32, i32 15, float %arg0, float undef, float undef, float undef, i1 false, i1 false) #0
26+
call void @llvm.amdgcn.exp.f32(i32 32, i32 15, float %arg0, float poison, float poison, float poison, i1 false, i1 false) #0
2727
ret void
2828
}
2929

@@ -55,7 +55,7 @@ define amdgpu_vs void @test_sgpr_alignment0(float inreg %arg0, ptr addrspace(4)
5555
; CHECK-NEXT: G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.exp), 32, 15, [[COPY]](s32), [[DEF]](s32), [[DEF]](s32), [[DEF]](s32), 0, 0
5656
; CHECK-NEXT: S_ENDPGM 0
5757
%tmp0 = load volatile i32, ptr addrspace(4) %arg1
58-
call void @llvm.amdgcn.exp.f32(i32 32, i32 15, float %arg0, float undef, float undef, float undef, i1 false, i1 false) #0
58+
call void @llvm.amdgcn.exp.f32(i32 32, i32 15, float %arg0, float poison, float poison, float poison, i1 false, i1 false) #0
5959
ret void
6060
}
6161

‎llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.div.scale.ll

+3-3
Original file line numberDiff line numberDiff line change
@@ -1543,7 +1543,7 @@ define amdgpu_kernel void @test_div_scale_f32_val_undef_val(ptr addrspace(1) %ou
15431543
; GFX11-NEXT: v_div_scale_f32 v0, null, s0, s0, 0x41000000
15441544
; GFX11-NEXT: global_store_b32 v1, v0, s[0:1]
15451545
; GFX11-NEXT: s_endpgm
1546-
%result = call { float, i1 } @llvm.amdgcn.div.scale.f32(float 8.0, float undef, i1 false)
1546+
%result = call { float, i1 } @llvm.amdgcn.div.scale.f32(float 8.0, float poison, i1 false)
15471547
%result0 = extractvalue { float, i1 } %result, 0
15481548
store float %result0, ptr addrspace(1) %out, align 4
15491549
ret void
@@ -1589,7 +1589,7 @@ define amdgpu_kernel void @test_div_scale_f32_undef_val_val(ptr addrspace(1) %ou
15891589
; GFX11-NEXT: v_div_scale_f32 v0, null, 0x41000000, 0x41000000, s0
15901590
; GFX11-NEXT: global_store_b32 v1, v0, s[0:1]
15911591
; GFX11-NEXT: s_endpgm
1592-
%result = call { float, i1 } @llvm.amdgcn.div.scale.f32(float undef, float 8.0, i1 false)
1592+
%result = call { float, i1 } @llvm.amdgcn.div.scale.f32(float poison, float 8.0, i1 false)
15931593
%result0 = extractvalue { float, i1 } %result, 0
15941594
store float %result0, ptr addrspace(1) %out, align 4
15951595
ret void
@@ -1633,7 +1633,7 @@ define amdgpu_kernel void @test_div_scale_f32_undef_undef_val(ptr addrspace(1) %
16331633
; GFX11-NEXT: v_div_scale_f32 v0, null, s0, s0, s0
16341634
; GFX11-NEXT: global_store_b32 v1, v0, s[0:1]
16351635
; GFX11-NEXT: s_endpgm
1636-
%result = call { float, i1 } @llvm.amdgcn.div.scale.f32(float undef, float undef, i1 false)
1636+
%result = call { float, i1 } @llvm.amdgcn.div.scale.f32(float poison, float poison, i1 false)
16371637
%result0 = extractvalue { float, i1 } %result, 0
16381638
store float %result0, ptr addrspace(1) %out, align 4
16391639
ret void

‎llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.fmul.legacy.ll

+3-3
Original file line numberDiff line numberDiff line change
@@ -82,7 +82,7 @@ define float @v_mul_legacy_undef0_f32(float %a) {
8282
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
8383
; GFX11-NEXT: v_mul_dx9_zero_f32_e32 v0, s0, v0
8484
; GFX11-NEXT: s_setpc_b64 s[30:31]
85-
%result = call float @llvm.amdgcn.fmul.legacy(float undef, float %a)
85+
%result = call float @llvm.amdgcn.fmul.legacy(float poison, float %a)
8686
ret float %result
8787
}
8888

@@ -122,7 +122,7 @@ define float @v_mul_legacy_undef1_f32(float %a) {
122122
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
123123
; GFX11-NEXT: v_mul_dx9_zero_f32_e32 v0, s0, v0
124124
; GFX11-NEXT: s_setpc_b64 s[30:31]
125-
%result = call float @llvm.amdgcn.fmul.legacy(float %a, float undef)
125+
%result = call float @llvm.amdgcn.fmul.legacy(float %a, float poison)
126126
ret float %result
127127
}
128128

@@ -162,7 +162,7 @@ define float @v_mul_legacy_undef_f32() {
162162
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
163163
; GFX11-NEXT: v_mul_dx9_zero_f32_e64 v0, s0, s0
164164
; GFX11-NEXT: s_setpc_b64 s[30:31]
165-
%result = call float @llvm.amdgcn.fmul.legacy(float undef, float undef)
165+
%result = call float @llvm.amdgcn.fmul.legacy(float poison, float poison)
166166
ret float %result
167167
}
168168

‎llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.rsq.clamp.ll

+1-1
Original file line numberDiff line numberDiff line change
@@ -175,7 +175,7 @@ define float @v_rsq_clamp_undef_f32() #0 {
175175
; GFX12-NEXT: s_delay_alu instid0(TRANS32_DEP_1) | instid1(VALU_DEP_1)
176176
; GFX12-NEXT: v_minmax_num_f32 v0, s0, 0x7f7fffff, v0
177177
; GFX12-NEXT: s_setpc_b64 s[30:31]
178-
%rsq_clamp = call float @llvm.amdgcn.rsq.clamp.f32(float undef)
178+
%rsq_clamp = call float @llvm.amdgcn.rsq.clamp.f32(float poison)
179179
ret float %rsq_clamp
180180
}
181181

‎llvm/test/CodeGen/AMDGPU/adjust-writemask-invalid-copy.ll

+5-5
Original file line numberDiff line numberDiff line change
@@ -7,7 +7,7 @@
77
; GCN: buffer_store_dword v0
88
define amdgpu_ps void @adjust_writemask_crash_0_nochain() #0 {
99
main_body:
10-
%tmp = call <2 x float> @llvm.amdgcn.image.getlod.1d.v2f32.f32(i32 3, float undef, <8 x i32> poison, <4 x i32> poison, i1 0, i32 0, i32 0)
10+
%tmp = call <2 x float> @llvm.amdgcn.image.getlod.1d.v2f32.f32(i32 3, float poison, <8 x i32> poison, <4 x i32> poison, i1 0, i32 0, i32 0)
1111
%tmp1 = bitcast <2 x float> %tmp to <2 x i32>
1212
%tmp2 = shufflevector <2 x i32> %tmp1, <2 x i32> poison, <4 x i32> <i32 1, i32 poison, i32 poison, i32 poison>
1313
%tmp3 = bitcast <4 x i32> %tmp2 to <4 x float>
@@ -23,7 +23,7 @@ main_body:
2323
; GCN: buffer_store_dword v0
2424
define amdgpu_ps void @adjust_writemask_crash_1_nochain() #0 {
2525
main_body:
26-
%tmp = call <2 x float> @llvm.amdgcn.image.getlod.1d.v2f32.f32(i32 3, float undef, <8 x i32> poison, <4 x i32> poison, i1 0, i32 0, i32 0)
26+
%tmp = call <2 x float> @llvm.amdgcn.image.getlod.1d.v2f32.f32(i32 3, float poison, <8 x i32> poison, <4 x i32> poison, i1 0, i32 0, i32 0)
2727
%tmp1 = bitcast <2 x float> %tmp to <2 x i32>
2828
%tmp2 = shufflevector <2 x i32> %tmp1, <2 x i32> poison, <4 x i32> <i32 1, i32 0, i32 poison, i32 poison>
2929
%tmp3 = bitcast <4 x i32> %tmp2 to <4 x float>
@@ -39,7 +39,7 @@ main_body:
3939
; GCN: buffer_store_dword v0
4040
define amdgpu_ps void @adjust_writemask_crash_0_chain() #0 {
4141
main_body:
42-
%tmp = call <2 x float> @llvm.amdgcn.image.sample.1d.v2f32.f32(i32 3, float undef, <8 x i32> poison, <4 x i32> poison, i1 0, i32 0, i32 0)
42+
%tmp = call <2 x float> @llvm.amdgcn.image.sample.1d.v2f32.f32(i32 3, float poison, <8 x i32> poison, <4 x i32> poison, i1 0, i32 0, i32 0)
4343
%tmp1 = bitcast <2 x float> %tmp to <2 x i32>
4444
%tmp2 = shufflevector <2 x i32> %tmp1, <2 x i32> poison, <4 x i32> <i32 1, i32 poison, i32 poison, i32 poison>
4545
%tmp3 = bitcast <4 x i32> %tmp2 to <4 x float>
@@ -55,7 +55,7 @@ main_body:
5555
; GCN: buffer_store_dword v0
5656
define amdgpu_ps void @adjust_writemask_crash_1_chain() #0 {
5757
main_body:
58-
%tmp = call <2 x float> @llvm.amdgcn.image.sample.1d.v2f32.f32(i32 3, float undef, <8 x i32> poison, <4 x i32> poison, i1 0, i32 0, i32 0)
58+
%tmp = call <2 x float> @llvm.amdgcn.image.sample.1d.v2f32.f32(i32 3, float poison, <8 x i32> poison, <4 x i32> poison, i1 0, i32 0, i32 0)
5959
%tmp1 = bitcast <2 x float> %tmp to <2 x i32>
6060
%tmp2 = shufflevector <2 x i32> %tmp1, <2 x i32> poison, <4 x i32> <i32 1, i32 0, i32 poison, i32 poison>
6161
%tmp3 = bitcast <4 x i32> %tmp2 to <4 x float>
@@ -66,7 +66,7 @@ main_body:
6666

6767
define amdgpu_ps void @adjust_writemask_crash_0_v4() #0 {
6868
main_body:
69-
%tmp = call <4 x float> @llvm.amdgcn.image.getlod.1d.v4f32.f32(i32 5, float undef, <8 x i32> poison, <4 x i32> poison, i1 0, i32 0, i32 0)
69+
%tmp = call <4 x float> @llvm.amdgcn.image.getlod.1d.v4f32.f32(i32 5, float poison, <8 x i32> poison, <4 x i32> poison, i1 0, i32 0, i32 0)
7070
%tmp1 = bitcast <4 x float> %tmp to <4 x i32>
7171
%tmp2 = shufflevector <4 x i32> %tmp1, <4 x i32> poison, <4 x i32> <i32 1, i32 poison, i32 poison, i32 poison>
7272
%tmp3 = bitcast <4 x i32> %tmp2 to <4 x float>

‎llvm/test/CodeGen/AMDGPU/amdgpu-codegenprepare-fdiv.ll

+5-5
Original file line numberDiff line numberDiff line change
@@ -4009,7 +4009,7 @@ define <4 x float> @fdiv_constant_f32_vector(ptr addrspace(1) %out, <2 x float>
40094009
; IEEE-GOODFREXP-NEXT: [[TMP14:%.*]] = extractvalue { float, i32 } [[TMP13]], 0
40104010
; IEEE-GOODFREXP-NEXT: [[TMP15:%.*]] = extractvalue { float, i32 } [[TMP13]], 1
40114011
; IEEE-GOODFREXP-NEXT: [[TMP16:%.*]] = call float @llvm.amdgcn.rcp.f32(float [[TMP14]])
4012-
; IEEE-GOODFREXP-NEXT: [[TMP17:%.*]] = call { float, i32 } @llvm.frexp.f32.i32(float undef)
4012+
; IEEE-GOODFREXP-NEXT: [[TMP17:%.*]] = call { float, i32 } @llvm.frexp.f32.i32(float poison)
40134013
; IEEE-GOODFREXP-NEXT: [[TMP18:%.*]] = extractvalue { float, i32 } [[TMP17]], 0
40144014
; IEEE-GOODFREXP-NEXT: [[TMP19:%.*]] = extractvalue { float, i32 } [[TMP17]], 1
40154015
; IEEE-GOODFREXP-NEXT: [[TMP20:%.*]] = fmul float [[TMP18]], [[TMP16]]
@@ -4049,9 +4049,9 @@ define <4 x float> @fdiv_constant_f32_vector(ptr addrspace(1) %out, <2 x float>
40494049
; IEEE-BADFREXP-NEXT: [[TMP14:%.*]] = extractvalue { float, i32 } [[TMP13]], 0
40504050
; IEEE-BADFREXP-NEXT: [[TMP15:%.*]] = call i32 @llvm.amdgcn.frexp.exp.i32.f32(float 3.200000e+01)
40514051
; IEEE-BADFREXP-NEXT: [[TMP16:%.*]] = call float @llvm.amdgcn.rcp.f32(float [[TMP14]])
4052-
; IEEE-BADFREXP-NEXT: [[TMP17:%.*]] = call { float, i32 } @llvm.frexp.f32.i32(float undef)
4052+
; IEEE-BADFREXP-NEXT: [[TMP17:%.*]] = call { float, i32 } @llvm.frexp.f32.i32(float poison)
40534053
; IEEE-BADFREXP-NEXT: [[TMP18:%.*]] = extractvalue { float, i32 } [[TMP17]], 0
4054-
; IEEE-BADFREXP-NEXT: [[TMP19:%.*]] = call i32 @llvm.amdgcn.frexp.exp.i32.f32(float undef)
4054+
; IEEE-BADFREXP-NEXT: [[TMP19:%.*]] = call i32 @llvm.amdgcn.frexp.exp.i32.f32(float poison)
40554055
; IEEE-BADFREXP-NEXT: [[TMP20:%.*]] = fmul float [[TMP18]], [[TMP16]]
40564056
; IEEE-BADFREXP-NEXT: [[TMP21:%.*]] = sub i32 [[TMP19]], [[TMP15]]
40574057
; IEEE-BADFREXP-NEXT: [[TMP22:%.*]] = call float @llvm.ldexp.f32.i32(float [[TMP20]], i32 [[TMP21]])
@@ -4079,7 +4079,7 @@ define <4 x float> @fdiv_constant_f32_vector(ptr addrspace(1) %out, <2 x float>
40794079
; DAZ-NEXT: [[TMP4:%.*]] = extractvalue { float, i32 } [[TMP3]], 0
40804080
; DAZ-NEXT: [[TMP5:%.*]] = extractvalue { float, i32 } [[TMP3]], 1
40814081
; DAZ-NEXT: [[TMP6:%.*]] = call float @llvm.amdgcn.rcp.f32(float [[TMP4]])
4082-
; DAZ-NEXT: [[TMP7:%.*]] = call { float, i32 } @llvm.frexp.f32.i32(float undef)
4082+
; DAZ-NEXT: [[TMP7:%.*]] = call { float, i32 } @llvm.frexp.f32.i32(float poison)
40834083
; DAZ-NEXT: [[TMP8:%.*]] = extractvalue { float, i32 } [[TMP7]], 0
40844084
; DAZ-NEXT: [[TMP9:%.*]] = extractvalue { float, i32 } [[TMP7]], 1
40854085
; DAZ-NEXT: [[TMP10:%.*]] = fmul float [[TMP8]], [[TMP6]]
@@ -4101,7 +4101,7 @@ define <4 x float> @fdiv_constant_f32_vector(ptr addrspace(1) %out, <2 x float>
41014101
; DAZ-NEXT: [[CONST_PARTIAL_RCP:%.*]] = insertelement <4 x float> [[TMP25]], float [[TMP22]], i64 3
41024102
; DAZ-NEXT: ret <4 x float> [[CONST_PARTIAL_RCP]]
41034103
;
4104-
%const.partial.rcp = fdiv <4 x float> <float 1.0, float -1.0, float undef, float 2.0>, <float 0.5, float 2.0, float 32.0, float 10.0>, !fpmath !2
4104+
%const.partial.rcp = fdiv <4 x float> <float 1.0, float -1.0, float poison, float 2.0>, <float 0.5, float 2.0, float 32.0, float 10.0>, !fpmath !2
41054105
ret <4 x float> %const.partial.rcp
41064106
}
41074107

‎llvm/test/CodeGen/AMDGPU/amdgpu-reloc-const.ll

+1-1
Original file line numberDiff line numberDiff line change
@@ -17,7 +17,7 @@
1717
define amdgpu_ps void @ps_main(i32 %arg, i32 inreg %arg1, i32 inreg %arg2) local_unnamed_addr #0 {
1818
%rc = call i32 @llvm.amdgcn.reloc.constant(metadata !1)
1919
%rcf = bitcast i32 %rc to float
20-
call void @llvm.amdgcn.exp.f32(i32 40, i32 15, float %rcf, float undef, float undef, float undef, i1 false, i1 false) #0
20+
call void @llvm.amdgcn.exp.f32(i32 40, i32 15, float %rcf, float poison, float poison, float poison, i1 false, i1 false) #0
2121
ret void
2222
}
2323

‎llvm/test/CodeGen/AMDGPU/cndmask-no-def-vcc.ll

+1-1
Original file line numberDiff line numberDiff line change
@@ -37,7 +37,7 @@ bb2:
3737
define amdgpu_kernel void @preserve_condition_undef_flag(float %arg, i32 %arg1, float %arg2) {
3838
bb0:
3939
%tmp = icmp sgt i32 %arg1, 4
40-
%undef = call i1 @llvm.amdgcn.class.f32(float undef, i32 undef)
40+
%undef = call i1 @llvm.amdgcn.class.f32(float poison, i32 undef)
4141
%tmp4 = select i1 %undef, float %arg, float 1.000000e+00
4242
%tmp5 = fcmp ogt float %arg2, 0.000000e+00
4343
%tmp6 = fcmp olt float %arg2, 1.000000e+00

‎llvm/test/CodeGen/AMDGPU/commute-shifts.ll

+1-1
Original file line numberDiff line numberDiff line change
@@ -38,7 +38,7 @@ bb:
3838
%tmp5 = and i32 %tmp2, %tmp4
3939
%tmp6 = icmp eq i32 %tmp5, 0
4040
%tmp7 = select i1 %tmp6, float 0.000000e+00, float %arg1
41-
%tmp8 = call <2 x half> @llvm.amdgcn.cvt.pkrtz(float undef, float %tmp7)
41+
%tmp8 = call <2 x half> @llvm.amdgcn.cvt.pkrtz(float poison, float %tmp7)
4242
%tmp9 = bitcast <2 x half> %tmp8 to float
4343
ret float %tmp9
4444
}

‎llvm/test/CodeGen/AMDGPU/cse-phi-incoming-val.ll

+1-1
Original file line numberDiff line numberDiff line change
@@ -31,7 +31,7 @@ bb9: ; preds = %bb5
3131

3232
bb10: ; preds = %bb9, %bb5, %bb3, %bb
3333
%tmp11 = phi float [ 1.000000e+00, %bb3 ], [ 0.000000e+00, %bb9 ], [ 1.000000e+00, %bb ], [ poison, %bb5 ]
34-
call void @llvm.amdgcn.exp.f32(i32 40, i32 15, float %tmp11, float undef, float undef, float undef, i1 false, i1 false) #0
34+
call void @llvm.amdgcn.exp.f32(i32 40, i32 15, float %tmp11, float poison, float poison, float poison, i1 false, i1 false) #0
3535
ret void
3636
}
3737

‎llvm/test/CodeGen/AMDGPU/dagcombine-fma-fmad.ll

+10-10
Original file line numberDiff line numberDiff line change
@@ -143,21 +143,21 @@ define amdgpu_ps float @_amdgpu_ps_main() #0 {
143143
; GFX11-NEXT: v_max_f32_e32 v0, 0, v1
144144
; GFX11-NEXT: ; return to shader part epilog
145145
.entry:
146-
%0 = call <3 x float> @llvm.amdgcn.image.sample.2d.v3f32.f32(i32 7, float undef, float undef, <8 x i32> poison, <4 x i32> poison, i1 false, i32 0, i32 0)
146+
%0 = call <3 x float> @llvm.amdgcn.image.sample.2d.v3f32.f32(i32 7, float poison, float poison, <8 x i32> poison, <4 x i32> poison, i1 false, i32 0, i32 0)
147147
%.i2243 = extractelement <3 x float> %0, i32 2
148148
%1 = call <3 x i32> @llvm.amdgcn.s.buffer.load.v3i32(<4 x i32> poison, i32 0, i32 0)
149149
%2 = shufflevector <3 x i32> %1, <3 x i32> poison, <4 x i32> <i32 0, i32 1, i32 2, i32 poison>
150150
%3 = bitcast <4 x i32> %2 to <4 x float>
151151
%.i2248 = extractelement <4 x float> %3, i32 2
152152
%.i2249 = fmul reassoc nnan nsz arcp contract afn float %.i2243, %.i2248
153-
%4 = call reassoc nnan nsz arcp contract afn float @llvm.amdgcn.fmed3.f32(float undef, float 0.000000e+00, float 1.000000e+00)
154-
%5 = call <3 x float> @llvm.amdgcn.image.sample.2d.v3f32.f32(i32 7, float undef, float undef, <8 x i32> poison, <4 x i32> poison, i1 false, i32 0, i32 0)
153+
%4 = call reassoc nnan nsz arcp contract afn float @llvm.amdgcn.fmed3.f32(float poison, float 0.000000e+00, float 1.000000e+00)
154+
%5 = call <3 x float> @llvm.amdgcn.image.sample.2d.v3f32.f32(i32 7, float poison, float poison, <8 x i32> poison, <4 x i32> poison, i1 false, i32 0, i32 0)
155155
%.i2333 = extractelement <3 x float> %5, i32 2
156-
%6 = call reassoc nnan nsz arcp contract afn float @llvm.amdgcn.fmed3.f32(float undef, float 0.000000e+00, float 1.000000e+00)
157-
%7 = call <2 x float> @llvm.amdgcn.image.sample.2d.v2f32.f32(i32 3, float undef, float undef, <8 x i32> poison, <4 x i32> poison, i1 false, i32 0, i32 0)
156+
%6 = call reassoc nnan nsz arcp contract afn float @llvm.amdgcn.fmed3.f32(float poison, float 0.000000e+00, float 1.000000e+00)
157+
%7 = call <2 x float> @llvm.amdgcn.image.sample.2d.v2f32.f32(i32 3, float poison, float poison, <8 x i32> poison, <4 x i32> poison, i1 false, i32 0, i32 0)
158158
%.i1408 = extractelement <2 x float> %7, i32 1
159159
%.i0364 = extractelement <2 x float> %7, i32 0
160-
%8 = call float @llvm.amdgcn.image.sample.2d.f32.f32(i32 1, float undef, float undef, <8 x i32> poison, <4 x i32> poison, i1 false, i32 0, i32 0)
160+
%8 = call float @llvm.amdgcn.image.sample.2d.f32.f32(i32 1, float poison, float poison, <8 x i32> poison, <4 x i32> poison, i1 false, i32 0, i32 0)
161161
%9 = call <3 x i32> @llvm.amdgcn.s.buffer.load.v3i32(<4 x i32> poison, i32 112, i32 0)
162162
%10 = shufflevector <3 x i32> %9, <3 x i32> poison, <4 x i32> <i32 0, i32 1, i32 2, i32 poison>
163163
%11 = bitcast <4 x i32> %10 to <4 x float>
@@ -175,7 +175,7 @@ define amdgpu_ps float @_amdgpu_ps_main() #0 {
175175
%.i2376 = fsub reassoc nnan nsz arcp contract afn float %.i2373, %.i2370
176176
%.i2383 = fmul reassoc nnan nsz arcp contract afn float %.i2376, %6
177177
%.i2386 = fadd reassoc nnan nsz arcp contract afn float %.i2370, %.i2383
178-
%18 = call reassoc nnan nsz arcp contract afn float @llvm.amdgcn.fmed3.f32(float undef, float 0.000000e+00, float 1.000000e+00)
178+
%18 = call reassoc nnan nsz arcp contract afn float @llvm.amdgcn.fmed3.f32(float poison, float 0.000000e+00, float 1.000000e+00)
179179
%19 = fmul reassoc nnan nsz arcp contract afn float %18, %.i2363
180180
%.i2394 = fsub reassoc nnan nsz arcp contract afn float %.i2386, %19
181181
%.i2397 = fmul reassoc nnan nsz arcp contract afn float %.i2363, %18
@@ -206,8 +206,8 @@ define amdgpu_ps float @_amdgpu_ps_main() #0 {
206206
%.i2415 = fmul reassoc nnan nsz arcp contract afn float %.i2407, %41
207207
%42 = call <3 x float> @llvm.amdgcn.image.load.mip.2d.v3f32.i32(i32 7, i32 undef, i32 undef, i32 0, <8 x i32> poison, i32 0, i32 0)
208208
%.i2521 = extractelement <3 x float> %42, i32 2
209-
%43 = call reassoc nnan nsz arcp contract afn float @llvm.amdgcn.fmed3.f32(float undef, float 0.000000e+00, float 1.000000e+00)
210-
%44 = call <3 x float> @llvm.amdgcn.image.sample.2d.v3f32.f32(i32 7, float undef, float undef, <8 x i32> poison, <4 x i32> poison, i1 false, i32 0, i32 0)
209+
%43 = call reassoc nnan nsz arcp contract afn float @llvm.amdgcn.fmed3.f32(float poison, float 0.000000e+00, float 1.000000e+00)
210+
%44 = call <3 x float> @llvm.amdgcn.image.sample.2d.v3f32.f32(i32 7, float poison, float poison, <8 x i32> poison, <4 x i32> poison, i1 false, i32 0, i32 0)
211211
%.i2465 = extractelement <3 x float> %44, i32 2
212212
%.i2466 = fmul reassoc nnan nsz arcp contract afn float %.i2465, %43
213213
%.i2469 = fmul reassoc nnan nsz arcp contract afn float %.i2415, %.i2466
@@ -224,7 +224,7 @@ define amdgpu_ps float @_amdgpu_ps_main() #0 {
224224
%.i2488 = fmul reassoc nnan nsz arcp contract afn float %.i2249, %18
225225
%.i2491 = fmul reassoc nnan nsz arcp contract afn float %.i2485, %4
226226
%.i2494 = fadd reassoc nnan nsz arcp contract afn float %.i2479, %.i2491
227-
%51 = call <3 x float> @llvm.amdgcn.image.sample.2d.v3f32.f32(i32 7, float undef, float undef, <8 x i32> poison, <4 x i32> poison, i1 false, i32 0, i32 0)
227+
%51 = call <3 x float> @llvm.amdgcn.image.sample.2d.v3f32.f32(i32 7, float poison, float poison, <8 x i32> poison, <4 x i32> poison, i1 false, i32 0, i32 0)
228228
%.i2515 = extractelement <3 x float> %51, i32 2
229229
%.i2516 = fadd reassoc nnan nsz arcp contract afn float %.i2515, %.i2494
230230
%.i2522 = fadd reassoc nnan nsz arcp contract afn float %.i2521, %.i2516

‎llvm/test/CodeGen/AMDGPU/diverge-extra-formal-args.ll

+1-1
Original file line numberDiff line numberDiff line change
@@ -19,7 +19,7 @@ define dllexport amdgpu_vs void @_amdgpu_vs_main(i32 inreg %arg, i32 inreg %arg1
1919
%tmp11 = load <2 x float>, ptr addrspace(4) %tmp10, align 8
2020
%tmp12 = fadd nnan arcp contract <2 x float> zeroinitializer, %tmp11
2121
%tmp13 = extractelement <2 x float> %tmp12, i32 1
22-
call void @llvm.amdgcn.exp.f32(i32 12, i32 15, float undef, float %tmp13, float 0.000000e+00, float 1.000000e+00, i1 true, i1 false) #1
22+
call void @llvm.amdgcn.exp.f32(i32 12, i32 15, float poison, float %tmp13, float 0.000000e+00, float 1.000000e+00, i1 true, i1 false) #1
2323
ret void
2424
}
2525

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