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[WIP][AMDGPU][Attributor] Infer inreg attribute in AMDGPUAttributor 
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‎llvm/lib/Target/AMDGPU/AMDGPUAttributor.cpp

Lines changed: 82 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1009,6 +1009,82 @@ struct AAAMDGPUNoAGPR
10091009

10101010
const char AAAMDGPUNoAGPR::ID = 0;
10111011

1012+
struct AAAMDGPUInreg
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: public IRAttribute<Attribute::InReg,
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StateWrapper<BooleanState, AbstractAttribute>,
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AAAMDGPUInreg> {
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AAAMDGPUInreg(const IRPosition &IRP, Attributor &A) : IRAttribute(IRP) {}
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/// Create an abstract attribute view for the position \p IRP.
1019+
static AAAMDGPUInreg &createForPosition(const IRPosition &IRP, Attributor &A);
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/// See AbstractAttribute::getName()
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const std::string getName() const override { return "AAAMDGPUInreg"; }
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const std::string getAsStr(Attributor *A) const override {
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return getAssumed() ? "inreg" : "non-inreg";
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}
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void trackStatistics() const override {}
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/// See AbstractAttribute::getIdAddr()
1031+
const char *getIdAddr() const override { return &ID; }
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/// This function should return true if the type of the \p AA is AAAMDGPUInreg
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static bool classof(const AbstractAttribute *AA) {
1035+
return (AA->getIdAddr() == &ID);
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}
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/// Unique ID (due to the unique address)
1039+
static const char ID;
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};
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const char AAAMDGPUInreg::ID = 0;
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namespace {
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struct AAAMDGPUInregArgument : public AAAMDGPUInreg {
1047+
AAAMDGPUInregArgument(const IRPosition &IRP, Attributor &A)
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: AAAMDGPUInreg(IRP, A) {}
1049+
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void initialize(Attributor &A) override {
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if (getAssociatedArgument()->hasAttribute(Attribute::InReg))
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indicateOptimisticFixpoint();
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}
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ChangeStatus updateImpl(Attributor &A) override {
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const auto &InfoCache =
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static_cast<AMDGPUInformationCache &>(A.getInfoCache());
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unsigned ArgNo = getAssociatedArgument()->getArgNo();
1059+
1060+
auto Pred = [&](AbstractCallSite ACS) -> bool {
1061+
CallBase *CB = ACS.getInstruction();
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auto TTI = InfoCache.TM.getTargetTransformInfo(*CB->getFunction());
1063+
Value *V = CB->getArgOperandUse(ArgNo);
1064+
return TTI.isAlwaysUniform(V);
1065+
};
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bool UsedAssumedInformation = false;
1068+
if (!A.checkForAllCallSites(Pred, *this, /*RequireAllCallSites=*/true,
1069+
UsedAssumedInformation))
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return indicatePessimisticFixpoint();
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return ChangeStatus::UNCHANGED;
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}
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};
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} // namespace
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AAAMDGPUInreg &AAAMDGPUInreg::createForPosition(const IRPosition &IRP,
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Attributor &A) {
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switch (IRP.getPositionKind()) {
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case IRPosition::IRP_ARGUMENT:
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return *new (A.Allocator) AAAMDGPUInregArgument(IRP, A);
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default:
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llvm_unreachable("not a valid position for AAAMDGPUInreg");
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}
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}
1087+
10121088
static void addPreloadKernArgHint(Function &F, TargetMachine &TM) {
10131089
const GCNSubtarget &ST = TM.getSubtarget<GCNSubtarget>(F);
10141090
for (unsigned I = 0;
@@ -1041,7 +1117,7 @@ static bool runImpl(Module &M, AnalysisGetter &AG, TargetMachine &TM,
10411117
&AAAMDWavesPerEU::ID, &AAAMDGPUNoAGPR::ID, &AACallEdges::ID,
10421118
&AAPointerInfo::ID, &AAPotentialConstantValues::ID,
10431119
&AAUnderlyingObjects::ID, &AAAddressSpace::ID, &AAIndirectCallInfo::ID,
1044-
&AAInstanceInfo::ID});
1120+
&AAInstanceInfo::ID, &AAAMDGPUInreg::ID});
10451121

10461122
AttributorConfig AC(CGUpdater);
10471123
AC.IsClosedWorldModule = Options.IsClosedWorld;
@@ -1091,6 +1167,11 @@ static bool runImpl(Module &M, AnalysisGetter &AG, TargetMachine &TM,
10911167
IRPosition::value(*SI->getPointerOperand()));
10921168
}
10931169
}
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if (F.getCallingConv() != CallingConv::AMDGPU_KERNEL) {
1172+
for (auto &Arg : F.args())
1173+
A.getOrCreateAAFor<AAAMDGPUInreg>(IRPosition::argument(Arg));
1174+
}
10941175
}
10951176

10961177
ChangeStatus Change = A.run();

‎llvm/test/CodeGen/AMDGPU/inreg-inference.ll

Lines changed: 66 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,66 @@
1+
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --function-signature --check-globals
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; RUN: opt -S -mtriple=amdgcn-unknown-unknown -passes=amdgpu-attributor %s -o - | FileCheck %s
3+
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@g1 = protected addrspace(1) externally_initialized global i32 0, align 4
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@g2 = protected addrspace(1) externally_initialized global i32 0, align 4
6+
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;.
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; CHECK: @g1 = protected addrspace(1) externally_initialized global i32 0, align 4
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; CHECK: @g2 = protected addrspace(1) externally_initialized global i32 0, align 4
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;.
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define internal fastcc void @f(i32 %x.0.val, ptr nocapture noundef readonly %y) {
12+
; CHECK-LABEL: define {{[^@]+}}@f
13+
; CHECK-SAME: (i32 [[X_0_VAL:%.*]], ptr nocapture noundef readonly [[Y:%.*]]) #[[ATTR0:[0-9]+]] {
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; CHECK-NEXT: entry:
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; CHECK-NEXT: store i32 [[X_0_VAL]], ptr addrspace(1) @g1, align 4
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; CHECK-NEXT: [[LOAD:%.*]] = load i32, ptr [[Y]], align 4
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; CHECK-NEXT: store i32 [[LOAD]], ptr addrspace(1) @g2, align 4
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; CHECK-NEXT: ret void
19+
;
20+
entry:
21+
store i32 %x.0.val, ptr addrspace(1) @g1, align 4
22+
%load = load i32, ptr %y, align 4
23+
store i32 %load, ptr addrspace(1) @g2, align 4
24+
ret void
25+
}
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define protected amdgpu_kernel void @kernel(ptr addrspace(1) %x2, i32 %z) {
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; CHECK-LABEL: define {{[^@]+}}@kernel
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; CHECK-SAME: (ptr addrspace(1) [[X2:%.*]], i32 [[Z:%.*]]) #[[ATTR1:[0-9]+]] {
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; CHECK-NEXT: entry:
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; CHECK-NEXT: [[X2_CAST:%.*]] = addrspacecast ptr addrspace(1) [[X2]] to ptr
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; CHECK-NEXT: [[QUEUE_PTR:%.*]] = tail call ptr addrspace(4) @llvm.amdgcn.queue.ptr()
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; CHECK-NEXT: [[QUEUE_PTR_CAST:%.*]] = addrspacecast ptr addrspace(4) [[QUEUE_PTR]] to ptr
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; CHECK-NEXT: [[IMPLICITARG_PTR:%.*]] = tail call ptr addrspace(4) @llvm.amdgcn.implicitarg.ptr()
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; CHECK-NEXT: [[IMPLICITARG_PTR_CAST:%.*]] = addrspacecast ptr addrspace(4) [[IMPLICITARG_PTR]] to ptr
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; CHECK-NEXT: [[CMP:%.*]] = icmp sgt i32 [[Z]], 0
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; CHECK-NEXT: [[COND:%.*]] = select i1 [[CMP]], ptr [[QUEUE_PTR_CAST]], ptr [[X2_CAST]]
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; CHECK-NEXT: [[COND_VAL:%.*]] = load i32, ptr [[COND]], align 4
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; CHECK-NEXT: tail call fastcc void @f(i32 [[COND_VAL]], ptr noundef [[IMPLICITARG_PTR_CAST]])
40+
; CHECK-NEXT: [[DOTVAL:%.*]] = load i32, ptr addrspace(4) [[QUEUE_PTR]], align 4
41+
; CHECK-NEXT: tail call fastcc void @f(i32 [[DOTVAL]], ptr noundef [[IMPLICITARG_PTR_CAST]])
42+
; CHECK-NEXT: ret void
43+
;
44+
entry:
45+
%x2.cast = addrspacecast ptr addrspace(1) %x2 to ptr
46+
%queue.ptr = tail call ptr addrspace(4) @llvm.amdgcn.queue.ptr()
47+
%queue.ptr.cast = addrspacecast ptr addrspace(4) %queue.ptr to ptr
48+
%implicitarg.ptr = tail call ptr addrspace(4) @llvm.amdgcn.implicitarg.ptr()
49+
%implicitarg.ptr.cast = addrspacecast ptr addrspace(4) %implicitarg.ptr to ptr
50+
%cmp = icmp sgt i32 %z, 0
51+
%cond = select i1 %cmp, ptr %queue.ptr.cast, ptr %x2.cast
52+
%cond.val = load i32, ptr %cond, align 4
53+
tail call fastcc void @f(i32 %cond.val, ptr noundef %implicitarg.ptr.cast)
54+
%.val = load i32, ptr addrspace(4) %queue.ptr, align 4
55+
tail call fastcc void @f(i32 %.val, ptr noundef %implicitarg.ptr.cast)
56+
ret void
57+
}
58+
59+
declare align 4 ptr addrspace(4) @llvm.amdgcn.queue.ptr()
60+
61+
declare align 4 ptr addrspace(4) @llvm.amdgcn.implicitarg.ptr()
62+
;.
63+
; CHECK: attributes #[[ATTR0]] = { "amdgpu-no-agpr" "amdgpu-no-completion-action" "amdgpu-no-default-queue" "amdgpu-no-dispatch-id" "amdgpu-no-dispatch-ptr" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-implicitarg-ptr" "amdgpu-no-lds-kernel-id" "amdgpu-no-multigrid-sync-arg" "amdgpu-no-queue-ptr" "amdgpu-no-workgroup-id-x" "amdgpu-no-workgroup-id-y" "amdgpu-no-workgroup-id-z" "amdgpu-no-workitem-id-x" "amdgpu-no-workitem-id-y" "amdgpu-no-workitem-id-z" "amdgpu-waves-per-eu"="4,10" "uniform-work-group-size"="false" }
64+
; CHECK: attributes #[[ATTR1]] = { "amdgpu-no-agpr" "amdgpu-no-completion-action" "amdgpu-no-default-queue" "amdgpu-no-dispatch-id" "amdgpu-no-dispatch-ptr" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-lds-kernel-id" "amdgpu-no-multigrid-sync-arg" "amdgpu-no-workgroup-id-x" "amdgpu-no-workgroup-id-y" "amdgpu-no-workgroup-id-z" "amdgpu-no-workitem-id-x" "amdgpu-no-workitem-id-y" "amdgpu-no-workitem-id-z" "amdgpu-waves-per-eu"="4,10" "uniform-work-group-size"="false" }
65+
; CHECK: attributes #[[ATTR2:[0-9]+]] = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
66+
;.

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