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davemgreendavemgreen
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[ARM] Extra MVE reduction test cases. NFC
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‎llvm/test/Transforms/LoopVectorize/ARM/mve-reductions.ll

Lines changed: 162 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1664,5 +1664,167 @@ for.body:
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br i1 %cmp, label %for.body, label %for.cond.cleanup
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}
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define i64 @test_std_q31(ptr %x, i32 %n) #0 {
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; CHECK-LABEL: @test_std_q31(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: [[CMP11:%.*]] = icmp sgt i32 [[N:%.*]], 0
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; CHECK-NEXT: tail call void @llvm.assume(i1 [[CMP11]])
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; CHECK-NEXT: br label [[FOR_BODY1:%.*]]
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; CHECK: for.cond.cleanup:
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; CHECK-NEXT: [[DIV:%.*]] = sdiv i64 [[ADD3:%.*]], [[ADD:%.*]]
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; CHECK-NEXT: ret i64 [[DIV]]
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; CHECK: for.body:
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; CHECK-NEXT: [[S_014:%.*]] = phi i64 [ [[ADD]], [[FOR_BODY1]] ], [ 0, [[ENTRY:%.*]] ]
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; CHECK-NEXT: [[I_013:%.*]] = phi i32 [ [[ADD4:%.*]], [[FOR_BODY1]] ], [ 0, [[ENTRY]] ]
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; CHECK-NEXT: [[T_012:%.*]] = phi i64 [ [[ADD3]], [[FOR_BODY1]] ], [ 0, [[ENTRY]] ]
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; CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, ptr [[X:%.*]], i32 [[I_013]]
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; CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr [[ARRAYIDX]], align 4
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; CHECK-NEXT: [[SHR:%.*]] = ashr i32 [[TMP0]], 8
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; CHECK-NEXT: [[CONV:%.*]] = sext i32 [[SHR]] to i64
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; CHECK-NEXT: [[ADD]] = add nsw i64 [[S_014]], [[CONV]]
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; CHECK-NEXT: [[MUL:%.*]] = mul nsw i64 [[CONV]], [[CONV]]
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; CHECK-NEXT: [[ADD3]] = add nuw nsw i64 [[MUL]], [[T_012]]
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; CHECK-NEXT: [[ADD4]] = add nuw nsw i32 [[I_013]], 1
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; CHECK-NEXT: [[EXITCOND_NOT:%.*]] = icmp eq i32 [[ADD4]], [[N]]
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; CHECK-NEXT: br i1 [[EXITCOND_NOT]], label [[FOR_COND_CLEANUP:%.*]], label [[FOR_BODY1]]
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;
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entry:
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%cmp11 = icmp sgt i32 %n, 0
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tail call void @llvm.assume(i1 %cmp11)
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br label %for.body
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for.cond.cleanup: ; preds = %for.body
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%div = sdiv i64 %add3, %add
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ret i64 %div
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for.body: ; preds = %entry, %for.body
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%s.014 = phi i64 [ %add, %for.body ], [ 0, %entry ]
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%i.013 = phi i32 [ %add4, %for.body ], [ 0, %entry ]
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%t.012 = phi i64 [ %add3, %for.body ], [ 0, %entry ]
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%arrayidx = getelementptr inbounds i32, ptr %x, i32 %i.013
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%0 = load i32, ptr %arrayidx, align 4
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%shr = ashr i32 %0, 8
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%conv = sext i32 %shr to i64
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%add = add nsw i64 %s.014, %conv
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%mul = mul nsw i64 %conv, %conv
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%add3 = add nuw nsw i64 %mul, %t.012
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%add4 = add nuw nsw i32 %i.013, 1
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%exitcond.not = icmp eq i32 %add4, %n
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br i1 %exitcond.not, label %for.cond.cleanup, label %for.body
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}
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define i64 @test_fir_q15(ptr %x, ptr %y, i32 %n) #0 {
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; CHECK-LABEL: @test_fir_q15(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: [[CMP23:%.*]] = icmp sgt i32 [[N:%.*]], 0
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; CHECK-NEXT: br i1 [[CMP23]], label [[FOR_BODY_PREHEADER:%.*]], label [[FOR_COND_CLEANUP:%.*]]
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; CHECK: for.body.preheader:
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; CHECK-NEXT: [[TMP0:%.*]] = add nsw i32 [[N]], -1
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; CHECK-NEXT: [[TMP1:%.*]] = lshr i32 [[TMP0]], 1
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; CHECK-NEXT: [[TMP2:%.*]] = add nuw i32 [[TMP1]], 1
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; CHECK-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i32 [[N]], 7
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; CHECK-NEXT: br i1 [[MIN_ITERS_CHECK]], label [[SCALAR_PH:%.*]], label [[VECTOR_PH:%.*]]
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; CHECK: vector.ph:
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; CHECK-NEXT: [[N_VEC:%.*]] = and i32 [[TMP2]], -4
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; CHECK-NEXT: [[IND_END:%.*]] = shl i32 [[N_VEC]], 1
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; CHECK-NEXT: br label [[VECTOR_BODY:%.*]]
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; CHECK: vector.body:
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; CHECK-NEXT: [[INDEX:%.*]] = phi i32 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ]
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; CHECK-NEXT: [[VEC_PHI:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[TMP16:%.*]], [[VECTOR_BODY]] ]
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; CHECK-NEXT: [[OFFSET_IDX:%.*]] = shl i32 [[INDEX]], 1
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; CHECK-NEXT: [[TMP3:%.*]] = getelementptr inbounds i16, ptr [[X:%.*]], i32 [[OFFSET_IDX]]
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; CHECK-NEXT: [[WIDE_VEC:%.*]] = load <8 x i16>, ptr [[TMP3]], align 2
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; CHECK-NEXT: [[STRIDED_VEC:%.*]] = shufflevector <8 x i16> [[WIDE_VEC]], <8 x i16> poison, <4 x i32> <i32 0, i32 2, i32 4, i32 6>
1738+
; CHECK-NEXT: [[STRIDED_VEC1:%.*]] = shufflevector <8 x i16> [[WIDE_VEC]], <8 x i16> poison, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
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; CHECK-NEXT: [[TMP5:%.*]] = sext <4 x i16> [[STRIDED_VEC]] to <4 x i32>
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; CHECK-NEXT: [[TMP4:%.*]] = getelementptr inbounds i16, ptr [[Y:%.*]], i32 [[OFFSET_IDX]]
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; CHECK-NEXT: [[WIDE_VEC2:%.*]] = load <8 x i16>, ptr [[TMP4]], align 2
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; CHECK-NEXT: [[STRIDED_VEC3:%.*]] = shufflevector <8 x i16> [[WIDE_VEC2]], <8 x i16> poison, <4 x i32> <i32 0, i32 2, i32 4, i32 6>
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; CHECK-NEXT: [[STRIDED_VEC4:%.*]] = shufflevector <8 x i16> [[WIDE_VEC2]], <8 x i16> poison, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
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; CHECK-NEXT: [[TMP6:%.*]] = sext <4 x i16> [[STRIDED_VEC3]] to <4 x i32>
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; CHECK-NEXT: [[TMP7:%.*]] = mul nsw <4 x i32> [[TMP6]], [[TMP5]]
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; CHECK-NEXT: [[TMP8:%.*]] = sext <4 x i32> [[TMP7]] to <4 x i64>
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; CHECK-NEXT: [[TMP13:%.*]] = sext <4 x i16> [[STRIDED_VEC1]] to <4 x i32>
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; CHECK-NEXT: [[TMP14:%.*]] = sext <4 x i16> [[STRIDED_VEC4]] to <4 x i32>
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; CHECK-NEXT: [[TMP11:%.*]] = mul nsw <4 x i32> [[TMP14]], [[TMP13]]
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; CHECK-NEXT: [[TMP12:%.*]] = sext <4 x i32> [[TMP11]] to <4 x i64>
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; CHECK-NEXT: [[TMP9:%.*]] = call i64 @llvm.vector.reduce.add.v4i64(<4 x i64> [[TMP8]])
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; CHECK-NEXT: [[TMP10:%.*]] = add i64 [[TMP9]], [[VEC_PHI]]
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; CHECK-NEXT: [[TMP15:%.*]] = call i64 @llvm.vector.reduce.add.v4i64(<4 x i64> [[TMP12]])
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; CHECK-NEXT: [[TMP16]] = add i64 [[TMP15]], [[TMP10]]
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; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i32 [[INDEX]], 4
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; CHECK-NEXT: [[TMP17:%.*]] = icmp eq i32 [[INDEX_NEXT]], [[N_VEC]]
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; CHECK-NEXT: br i1 [[TMP17]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP37:![0-9]+]]
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; CHECK: middle.block:
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; CHECK-NEXT: [[CMP_N:%.*]] = icmp eq i32 [[TMP2]], [[N_VEC]]
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; CHECK-NEXT: br i1 [[CMP_N]], label [[FOR_COND_CLEANUP]], label [[SCALAR_PH]]
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; CHECK: scalar.ph:
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; CHECK-NEXT: [[BC_RESUME_VAL:%.*]] = phi i32 [ [[IND_END]], [[MIDDLE_BLOCK]] ], [ 0, [[FOR_BODY_PREHEADER]] ]
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; CHECK-NEXT: [[BC_MERGE_RDX:%.*]] = phi i64 [ [[TMP16]], [[MIDDLE_BLOCK]] ], [ 0, [[FOR_BODY_PREHEADER]] ]
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; CHECK-NEXT: br label [[FOR_BODY:%.*]]
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; CHECK: for.cond.cleanup:
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; CHECK-NEXT: [[S_0_LCSSA:%.*]] = phi i64 [ 0, [[ENTRY:%.*]] ], [ [[ADD12:%.*]], [[FOR_BODY]] ], [ [[TMP16]], [[MIDDLE_BLOCK]] ]
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; CHECK-NEXT: ret i64 [[S_0_LCSSA]]
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; CHECK: for.body:
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; CHECK-NEXT: [[I_025:%.*]] = phi i32 [ [[ADD13:%.*]], [[FOR_BODY]] ], [ [[BC_RESUME_VAL]], [[SCALAR_PH]] ]
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; CHECK-NEXT: [[S_024:%.*]] = phi i64 [ [[ADD12]], [[FOR_BODY]] ], [ [[BC_MERGE_RDX]], [[SCALAR_PH]] ]
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; CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, ptr [[X]], i32 [[I_025]]
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; CHECK-NEXT: [[TMP18:%.*]] = load i16, ptr [[ARRAYIDX]], align 2
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; CHECK-NEXT: [[CONV:%.*]] = sext i16 [[TMP18]] to i32
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; CHECK-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds i16, ptr [[Y]], i32 [[I_025]]
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; CHECK-NEXT: [[TMP19:%.*]] = load i16, ptr [[ARRAYIDX1]], align 2
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; CHECK-NEXT: [[CONV2:%.*]] = sext i16 [[TMP19]] to i32
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; CHECK-NEXT: [[MUL:%.*]] = mul nsw i32 [[CONV2]], [[CONV]]
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; CHECK-NEXT: [[CONV3:%.*]] = sext i32 [[MUL]] to i64
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; CHECK-NEXT: [[ADD:%.*]] = add nsw i64 [[S_024]], [[CONV3]]
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; CHECK-NEXT: [[ADD4:%.*]] = or disjoint i32 [[I_025]], 1
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; CHECK-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds i16, ptr [[X]], i32 [[ADD4]]
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; CHECK-NEXT: [[TMP20:%.*]] = load i16, ptr [[ARRAYIDX5]], align 2
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; CHECK-NEXT: [[CONV6:%.*]] = sext i16 [[TMP20]] to i32
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; CHECK-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds i16, ptr [[Y]], i32 [[ADD4]]
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; CHECK-NEXT: [[TMP21:%.*]] = load i16, ptr [[ARRAYIDX8]], align 2
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; CHECK-NEXT: [[CONV9:%.*]] = sext i16 [[TMP21]] to i32
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; CHECK-NEXT: [[MUL10:%.*]] = mul nsw i32 [[CONV9]], [[CONV6]]
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; CHECK-NEXT: [[CONV11:%.*]] = sext i32 [[MUL10]] to i64
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; CHECK-NEXT: [[ADD12]] = add nsw i64 [[ADD]], [[CONV11]]
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; CHECK-NEXT: [[ADD13]] = add nuw nsw i32 [[I_025]], 2
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; CHECK-NEXT: [[CMP:%.*]] = icmp slt i32 [[ADD13]], [[N]]
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; CHECK-NEXT: br i1 [[CMP]], label [[FOR_BODY]], label [[FOR_COND_CLEANUP]], !llvm.loop [[LOOP38:![0-9]+]]
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;
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entry:
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%cmp23 = icmp sgt i32 %n, 0
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br i1 %cmp23, label %for.body, label %for.cond.cleanup
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1798+
for.cond.cleanup: ; preds = %for.body, %entry
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%s.0.lcssa = phi i64 [ 0, %entry ], [ %add12, %for.body ]
1800+
ret i64 %s.0.lcssa
1801+
1802+
for.body: ; preds = %entry, %for.body
1803+
%i.025 = phi i32 [ %add13, %for.body ], [ 0, %entry ]
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%s.024 = phi i64 [ %add12, %for.body ], [ 0, %entry ]
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%arrayidx = getelementptr inbounds i16, ptr %x, i32 %i.025
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%0 = load i16, ptr %arrayidx, align 2
1807+
%conv = sext i16 %0 to i32
1808+
%arrayidx1 = getelementptr inbounds i16, ptr %y, i32 %i.025
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%1 = load i16, ptr %arrayidx1, align 2
1810+
%conv2 = sext i16 %1 to i32
1811+
%mul = mul nsw i32 %conv2, %conv
1812+
%conv3 = sext i32 %mul to i64
1813+
%add = add nsw i64 %s.024, %conv3
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%add4 = or disjoint i32 %i.025, 1
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%arrayidx5 = getelementptr inbounds i16, ptr %x, i32 %add4
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%2 = load i16, ptr %arrayidx5, align 2
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%conv6 = sext i16 %2 to i32
1818+
%arrayidx8 = getelementptr inbounds i16, ptr %y, i32 %add4
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%3 = load i16, ptr %arrayidx8, align 2
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%conv9 = sext i16 %3 to i32
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%mul10 = mul nsw i32 %conv9, %conv6
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%conv11 = sext i32 %mul10 to i64
1823+
%add12 = add nsw i64 %add, %conv11
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%add13 = add nuw nsw i32 %i.025, 2
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%cmp = icmp slt i32 %add13, %n
1826+
br i1 %cmp, label %for.body, label %for.cond.cleanup
1827+
}
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attributes #0 = { "target-features"="+mve" }

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