[RISCV] Prevent transform on >XLEN types

pfusik · pfusik · commit 75b5292de3b2 · 2025-04-09T08:31:41.000+02:00
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -14917,7 +14917,11 @@ static SDValue performSUBCombine(SDNode *N, SelectionDAG &DAG,
   if (SDValue V = combineSubShiftToOrcB(N, DAG, Subtarget))
     return V;
 
-  if (Subtarget.hasStdExtZbb()) {
+  const TargetLowering &TLI = DAG.getTargetLoweringInfo();
+  auto LK = TLI.getTypeConversion(*DAG.getContext(), VT);
+  if ((LK.first == TargetLoweringBase::TypeLegal ||
+       LK.first == TargetLoweringBase::TypePromoteInteger) &&
+      TLI.isOperationLegal(ISD::UMIN, LK.second)) {
     // fold (sub x, (select (ult x, y), 0, y)) -> (umin x, (sub x, y))
     using namespace llvm::SDPatternMatch;
     SDValue Y;
diff --git a/llvm/test/CodeGen/RISCV/rv32zbb.ll b/llvm/test/CodeGen/RISCV/rv32zbb.ll
@@ -1551,167 +1551,87 @@ define i32 @sub_if_uge_i32(i32 %x, i32 %y) {
 }
 
 define i64 @sub_if_uge_i64(i64 %x, i64 %y) {
-; RV32I-LABEL: sub_if_uge_i64:
-; RV32I:       # %bb.0:
-; RV32I-NEXT:    beq a1, a3, .LBB52_2
-; RV32I-NEXT:  # %bb.1:
-; RV32I-NEXT:    sltu a4, a1, a3
-; RV32I-NEXT:    j .LBB52_3
-; RV32I-NEXT:  .LBB52_2:
-; RV32I-NEXT:    sltu a4, a0, a2
-; RV32I-NEXT:  .LBB52_3:
-; RV32I-NEXT:    addi a4, a4, -1
-; RV32I-NEXT:    and a3, a4, a3
-; RV32I-NEXT:    and a2, a4, a2
-; RV32I-NEXT:    sltu a4, a0, a2
-; RV32I-NEXT:    sub a1, a1, a3
-; RV32I-NEXT:    sub a1, a1, a4
-; RV32I-NEXT:    sub a0, a0, a2
-; RV32I-NEXT:    ret
-;
-; RV32ZBB-LABEL: sub_if_uge_i64:
-; RV32ZBB:       # %bb.0:
-; RV32ZBB-NEXT:    sltu a4, a0, a2
-; RV32ZBB-NEXT:    sub a3, a1, a3
-; RV32ZBB-NEXT:    sub a3, a3, a4
-; RV32ZBB-NEXT:    sub a2, a0, a2
-; RV32ZBB-NEXT:    beq a1, a3, .LBB52_2
-; RV32ZBB-NEXT:  # %bb.1:
-; RV32ZBB-NEXT:    sltu a4, a1, a3
-; RV32ZBB-NEXT:    beqz a4, .LBB52_3
-; RV32ZBB-NEXT:    j .LBB52_4
-; RV32ZBB-NEXT:  .LBB52_2:
-; RV32ZBB-NEXT:    sltu a4, a0, a2
-; RV32ZBB-NEXT:    bnez a4, .LBB52_4
-; RV32ZBB-NEXT:  .LBB52_3:
-; RV32ZBB-NEXT:    mv a0, a2
-; RV32ZBB-NEXT:    mv a1, a3
-; RV32ZBB-NEXT:  .LBB52_4:
-; RV32ZBB-NEXT:    ret
+; CHECK-LABEL: sub_if_uge_i64:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    beq a1, a3, .LBB52_2
+; CHECK-NEXT:  # %bb.1:
+; CHECK-NEXT:    sltu a4, a1, a3
+; CHECK-NEXT:    j .LBB52_3
+; CHECK-NEXT:  .LBB52_2:
+; CHECK-NEXT:    sltu a4, a0, a2
+; CHECK-NEXT:  .LBB52_3:
+; CHECK-NEXT:    addi a4, a4, -1
+; CHECK-NEXT:    and a3, a4, a3
+; CHECK-NEXT:    and a2, a4, a2
+; CHECK-NEXT:    sltu a4, a0, a2
+; CHECK-NEXT:    sub a1, a1, a3
+; CHECK-NEXT:    sub a1, a1, a4
+; CHECK-NEXT:    sub a0, a0, a2
+; CHECK-NEXT:    ret
   %cmp = icmp ult i64 %x, %y
   %select = select i1 %cmp, i64 0, i64 %y
   %sub = sub nuw i64 %x, %select
   ret i64 %sub
 }
 
 define i128 @sub_if_uge_i128(i128 %x, i128 %y) {
-; RV32I-LABEL: sub_if_uge_i128:
-; RV32I:       # %bb.0:
-; RV32I-NEXT:    lw a7, 4(a2)
-; RV32I-NEXT:    lw a6, 8(a2)
-; RV32I-NEXT:    lw t0, 12(a2)
-; RV32I-NEXT:    lw a4, 12(a1)
-; RV32I-NEXT:    lw a3, 4(a1)
-; RV32I-NEXT:    lw a5, 8(a1)
-; RV32I-NEXT:    beq a4, t0, .LBB53_2
-; RV32I-NEXT:  # %bb.1:
-; RV32I-NEXT:    sltu t1, a4, t0
-; RV32I-NEXT:    j .LBB53_3
-; RV32I-NEXT:  .LBB53_2:
-; RV32I-NEXT:    sltu t1, a5, a6
-; RV32I-NEXT:  .LBB53_3:
-; RV32I-NEXT:    lw a2, 0(a2)
-; RV32I-NEXT:    lw a1, 0(a1)
-; RV32I-NEXT:    beq a3, a7, .LBB53_5
-; RV32I-NEXT:  # %bb.4:
-; RV32I-NEXT:    sltu t2, a3, a7
-; RV32I-NEXT:    j .LBB53_6
-; RV32I-NEXT:  .LBB53_5:
-; RV32I-NEXT:    sltu t2, a1, a2
-; RV32I-NEXT:  .LBB53_6:
-; RV32I-NEXT:    xor t3, a4, t0
-; RV32I-NEXT:    xor t4, a5, a6
-; RV32I-NEXT:    or t3, t4, t3
-; RV32I-NEXT:    beqz t3, .LBB53_8
-; RV32I-NEXT:  # %bb.7:
-; RV32I-NEXT:    mv t2, t1
-; RV32I-NEXT:  .LBB53_8:
-; RV32I-NEXT:    addi t2, t2, -1
-; RV32I-NEXT:    and t1, t2, t0
-; RV32I-NEXT:    and t0, t2, a2
-; RV32I-NEXT:    and a7, t2, a7
-; RV32I-NEXT:    sltu a2, a1, t0
-; RV32I-NEXT:    and t2, t2, a6
-; RV32I-NEXT:    mv a6, a2
-; RV32I-NEXT:    beq a3, a7, .LBB53_10
-; RV32I-NEXT:  # %bb.9:
-; RV32I-NEXT:    sltu a6, a3, a7
-; RV32I-NEXT:  .LBB53_10:
-; RV32I-NEXT:    sub t3, a5, t2
-; RV32I-NEXT:    sltu a5, a5, t2
-; RV32I-NEXT:    sub a4, a4, t1
-; RV32I-NEXT:    sub a3, a3, a7
-; RV32I-NEXT:    sub a1, a1, t0
-; RV32I-NEXT:    sltu a7, t3, a6
-; RV32I-NEXT:    sub a4, a4, a5
-; RV32I-NEXT:    sub a5, t3, a6
-; RV32I-NEXT:    sub a3, a3, a2
-; RV32I-NEXT:    sub a2, a4, a7
-; RV32I-NEXT:    sw a1, 0(a0)
-; RV32I-NEXT:    sw a3, 4(a0)
-; RV32I-NEXT:    sw a5, 8(a0)
-; RV32I-NEXT:    sw a2, 12(a0)
-; RV32I-NEXT:    ret
-;
-; RV32ZBB-LABEL: sub_if_uge_i128:
-; RV32ZBB:       # %bb.0:
-; RV32ZBB-NEXT:    lw a7, 0(a2)
-; RV32ZBB-NEXT:    lw t0, 4(a2)
-; RV32ZBB-NEXT:    lw a5, 8(a2)
-; RV32ZBB-NEXT:    lw a6, 12(a2)
-; RV32ZBB-NEXT:    lw a2, 8(a1)
-; RV32ZBB-NEXT:    lw a3, 12(a1)
-; RV32ZBB-NEXT:    lw a4, 0(a1)
-; RV32ZBB-NEXT:    lw a1, 4(a1)
-; RV32ZBB-NEXT:    sltu t1, a2, a5
-; RV32ZBB-NEXT:    sub a6, a3, a6
-; RV32ZBB-NEXT:    sltu t2, a4, a7
-; RV32ZBB-NEXT:    sub a6, a6, t1
-; RV32ZBB-NEXT:    mv t1, t2
-; RV32ZBB-NEXT:    beq a1, t0, .LBB53_2
-; RV32ZBB-NEXT:  # %bb.1:
-; RV32ZBB-NEXT:    sltu t1, a1, t0
-; RV32ZBB-NEXT:  .LBB53_2:
-; RV32ZBB-NEXT:    sub t3, a2, a5
-; RV32ZBB-NEXT:    sltu a5, t3, t1
-; RV32ZBB-NEXT:    sub a5, a6, a5
-; RV32ZBB-NEXT:    sub a6, t3, t1
-; RV32ZBB-NEXT:    beq a3, a5, .LBB53_4
-; RV32ZBB-NEXT:  # %bb.3:
-; RV32ZBB-NEXT:    sltu t1, a3, a5
-; RV32ZBB-NEXT:    j .LBB53_5
-; RV32ZBB-NEXT:  .LBB53_4:
-; RV32ZBB-NEXT:    sltu t1, a2, a6
-; RV32ZBB-NEXT:  .LBB53_5:
-; RV32ZBB-NEXT:    sub t0, a1, t0
-; RV32ZBB-NEXT:    sub t0, t0, t2
-; RV32ZBB-NEXT:    sub a7, a4, a7
-; RV32ZBB-NEXT:    beq a1, t0, .LBB53_7
-; RV32ZBB-NEXT:  # %bb.6:
-; RV32ZBB-NEXT:    sltu t2, a1, t0
-; RV32ZBB-NEXT:    j .LBB53_8
-; RV32ZBB-NEXT:  .LBB53_7:
-; RV32ZBB-NEXT:    sltu t2, a4, a7
-; RV32ZBB-NEXT:  .LBB53_8:
-; RV32ZBB-NEXT:    xor t3, a3, a5
-; RV32ZBB-NEXT:    xor t4, a2, a6
-; RV32ZBB-NEXT:    or t3, t4, t3
-; RV32ZBB-NEXT:    beqz t3, .LBB53_10
-; RV32ZBB-NEXT:  # %bb.9:
-; RV32ZBB-NEXT:    mv t2, t1
-; RV32ZBB-NEXT:  .LBB53_10:
-; RV32ZBB-NEXT:    bnez t2, .LBB53_12
-; RV32ZBB-NEXT:  # %bb.11:
-; RV32ZBB-NEXT:    mv a4, a7
-; RV32ZBB-NEXT:    mv a1, t0
-; RV32ZBB-NEXT:    mv a2, a6
-; RV32ZBB-NEXT:    mv a3, a5
-; RV32ZBB-NEXT:  .LBB53_12:
-; RV32ZBB-NEXT:    sw a4, 0(a0)
-; RV32ZBB-NEXT:    sw a1, 4(a0)
-; RV32ZBB-NEXT:    sw a2, 8(a0)
-; RV32ZBB-NEXT:    sw a3, 12(a0)
-; RV32ZBB-NEXT:    ret
+; CHECK-LABEL: sub_if_uge_i128:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lw a7, 4(a2)
+; CHECK-NEXT:    lw a6, 8(a2)
+; CHECK-NEXT:    lw t0, 12(a2)
+; CHECK-NEXT:    lw a4, 12(a1)
+; CHECK-NEXT:    lw a3, 4(a1)
+; CHECK-NEXT:    lw a5, 8(a1)
+; CHECK-NEXT:    beq a4, t0, .LBB53_2
+; CHECK-NEXT:  # %bb.1:
+; CHECK-NEXT:    sltu t1, a4, t0
+; CHECK-NEXT:    j .LBB53_3
+; CHECK-NEXT:  .LBB53_2:
+; CHECK-NEXT:    sltu t1, a5, a6
+; CHECK-NEXT:  .LBB53_3:
+; CHECK-NEXT:    lw a2, 0(a2)
+; CHECK-NEXT:    lw a1, 0(a1)
+; CHECK-NEXT:    beq a3, a7, .LBB53_5
+; CHECK-NEXT:  # %bb.4:
+; CHECK-NEXT:    sltu t2, a3, a7
+; CHECK-NEXT:    j .LBB53_6
+; CHECK-NEXT:  .LBB53_5:
+; CHECK-NEXT:    sltu t2, a1, a2
+; CHECK-NEXT:  .LBB53_6:
+; CHECK-NEXT:    xor t3, a4, t0
+; CHECK-NEXT:    xor t4, a5, a6
+; CHECK-NEXT:    or t3, t4, t3
+; CHECK-NEXT:    beqz t3, .LBB53_8
+; CHECK-NEXT:  # %bb.7:
+; CHECK-NEXT:    mv t2, t1
+; CHECK-NEXT:  .LBB53_8:
+; CHECK-NEXT:    addi t2, t2, -1
+; CHECK-NEXT:    and t1, t2, t0
+; CHECK-NEXT:    and t0, t2, a2
+; CHECK-NEXT:    and a7, t2, a7
+; CHECK-NEXT:    sltu a2, a1, t0
+; CHECK-NEXT:    and t2, t2, a6
+; CHECK-NEXT:    mv a6, a2
+; CHECK-NEXT:    beq a3, a7, .LBB53_10
+; CHECK-NEXT:  # %bb.9:
+; CHECK-NEXT:    sltu a6, a3, a7
+; CHECK-NEXT:  .LBB53_10:
+; CHECK-NEXT:    sub t3, a5, t2
+; CHECK-NEXT:    sltu a5, a5, t2
+; CHECK-NEXT:    sub a4, a4, t1
+; CHECK-NEXT:    sub a3, a3, a7
+; CHECK-NEXT:    sub a1, a1, t0
+; CHECK-NEXT:    sltu a7, t3, a6
+; CHECK-NEXT:    sub a4, a4, a5
+; CHECK-NEXT:    sub a5, t3, a6
+; CHECK-NEXT:    sub a3, a3, a2
+; CHECK-NEXT:    sub a2, a4, a7
+; CHECK-NEXT:    sw a1, 0(a0)
+; CHECK-NEXT:    sw a3, 4(a0)
+; CHECK-NEXT:    sw a5, 8(a0)
+; CHECK-NEXT:    sw a2, 12(a0)
+; CHECK-NEXT:    ret
   %cmp = icmp ult i128 %x, %y
   %select = select i1 %cmp, i128 0, i128 %y
   %sub = sub nuw i128 %x, %select
diff --git a/llvm/test/CodeGen/RISCV/rv64zbb.ll b/llvm/test/CodeGen/RISCV/rv64zbb.ll
@@ -1775,43 +1775,23 @@ define i64 @sub_if_uge_i64(i64 %x, i64 %y) {
 }
 
 define i128 @sub_if_uge_i128(i128 %x, i128 %y) {
-; RV64I-LABEL: sub_if_uge_i128:
-; RV64I:       # %bb.0:
-; RV64I-NEXT:    beq a1, a3, .LBB66_2
-; RV64I-NEXT:  # %bb.1:
-; RV64I-NEXT:    sltu a4, a1, a3
-; RV64I-NEXT:    j .LBB66_3
-; RV64I-NEXT:  .LBB66_2:
-; RV64I-NEXT:    sltu a4, a0, a2
-; RV64I-NEXT:  .LBB66_3:
-; RV64I-NEXT:    addi a4, a4, -1
-; RV64I-NEXT:    and a3, a4, a3
-; RV64I-NEXT:    and a2, a4, a2
-; RV64I-NEXT:    sltu a4, a0, a2
-; RV64I-NEXT:    sub a1, a1, a3
-; RV64I-NEXT:    sub a1, a1, a4
-; RV64I-NEXT:    sub a0, a0, a2
-; RV64I-NEXT:    ret
-;
-; RV64ZBB-LABEL: sub_if_uge_i128:
-; RV64ZBB:       # %bb.0:
-; RV64ZBB-NEXT:    sltu a4, a0, a2
-; RV64ZBB-NEXT:    sub a3, a1, a3
-; RV64ZBB-NEXT:    sub a3, a3, a4
-; RV64ZBB-NEXT:    sub a2, a0, a2
-; RV64ZBB-NEXT:    beq a1, a3, .LBB66_2
-; RV64ZBB-NEXT:  # %bb.1:
-; RV64ZBB-NEXT:    sltu a4, a1, a3
-; RV64ZBB-NEXT:    beqz a4, .LBB66_3
-; RV64ZBB-NEXT:    j .LBB66_4
-; RV64ZBB-NEXT:  .LBB66_2:
-; RV64ZBB-NEXT:    sltu a4, a0, a2
-; RV64ZBB-NEXT:    bnez a4, .LBB66_4
-; RV64ZBB-NEXT:  .LBB66_3:
-; RV64ZBB-NEXT:    mv a0, a2
-; RV64ZBB-NEXT:    mv a1, a3
-; RV64ZBB-NEXT:  .LBB66_4:
-; RV64ZBB-NEXT:    ret
+; CHECK-LABEL: sub_if_uge_i128:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    beq a1, a3, .LBB66_2
+; CHECK-NEXT:  # %bb.1:
+; CHECK-NEXT:    sltu a4, a1, a3
+; CHECK-NEXT:    j .LBB66_3
+; CHECK-NEXT:  .LBB66_2:
+; CHECK-NEXT:    sltu a4, a0, a2
+; CHECK-NEXT:  .LBB66_3:
+; CHECK-NEXT:    addi a4, a4, -1
+; CHECK-NEXT:    and a3, a4, a3
+; CHECK-NEXT:    and a2, a4, a2
+; CHECK-NEXT:    sltu a4, a0, a2
+; CHECK-NEXT:    sub a1, a1, a3
+; CHECK-NEXT:    sub a1, a1, a4
+; CHECK-NEXT:    sub a0, a0, a2
+; CHECK-NEXT:    ret
   %cmp = icmp ult i128 %x, %y
   %select = select i1 %cmp, i128 0, i128 %y
   %sub = sub nuw i128 %x, %select
