@@ -2200,14 +2200,9 @@ void SelectionDAGBuilder::visitRet(const ReturnInst &I) {
2200
2200
// Emit a store of the return value through the virtual register.
2201
2201
// Leave Outs empty so that LowerReturn won't try to load return
2202
2202
// registers the usual way.
2203
- SmallVector<EVT, 1> PtrValueVTs;
2204
- ComputeValueVTs(TLI, DL,
2205
- PointerType::get(F->getContext(),
2206
- DAG.getDataLayout().getAllocaAddrSpace()),
2207
- PtrValueVTs);
2208
-
2203
+ MVT PtrValueVT = TLI.getPointerTy (DL, DL.getAllocaAddrSpace ());
2209
2204
SDValue RetPtr =
2210
- DAG.getCopyFromReg(Chain, getCurSDLoc(), DemoteReg, PtrValueVTs[0] );
2205
+ DAG.getCopyFromReg (Chain, getCurSDLoc (), DemoteReg, PtrValueVT );
2211
2206
SDValue RetOp = getValue (I.getOperand (0 ));
2212
2207
2213
2208
SmallVector<EVT, 4 > ValueVTs, MemVTs;
@@ -11310,13 +11305,7 @@ TargetLowering::LowerCallTo(TargetLowering::CallLoweringInfo &CLI) const {
11310
11305
if (!CanLowerReturn) {
11311
11306
// The instruction result is the result of loading from the
11312
11307
// hidden sret parameter.
11313
- SmallVector<EVT, 1> PVTs;
11314
- Type *PtrRetTy =
11315
- PointerType::get(OrigRetTy->getContext(), DL.getAllocaAddrSpace());
11316
-
11317
- ComputeValueVTs(*this, DL, PtrRetTy, PVTs);
11318
- assert(PVTs.size() == 1 && "Pointers should fit in one register");
11319
- EVT PtrVT = PVTs[0];
11308
+ MVT PtrVT = getPointerTy (DL, DL.getAllocaAddrSpace ());
11320
11309
11321
11310
unsigned NumValues = RetTys.size ();
11322
11311
ReturnValues.resize (NumValues);
@@ -11636,18 +11625,12 @@ void SelectionDAGISel::LowerArguments(const Function &F) {
11636
11625
11637
11626
if (!FuncInfo->CanLowerReturn ) {
11638
11627
// Put in an sret pointer parameter before all the other parameters.
11639
- SmallVector<EVT, 1> ValueVTs;
11640
- ComputeValueVTs(*TLI, DAG.getDataLayout(),
11641
- PointerType::get(F.getContext(),
11642
- DAG.getDataLayout().getAllocaAddrSpace()),
11643
- ValueVTs);
11644
-
11645
- // NOTE: Assuming that a pointer will never break down to more than one VT
11646
- // or one register.
11628
+ MVT ValueVT = TLI->getPointerTy (DL, DL.getAllocaAddrSpace ());
11629
+
11647
11630
ISD::ArgFlagsTy Flags;
11648
11631
Flags.setSRet ();
11649
- MVT RegisterVT = TLI->getRegisterType(*DAG.getContext(), ValueVTs[0] );
11650
- ISD::InputArg RetArg(Flags, RegisterVT, ValueVTs[0] , true,
11632
+ MVT RegisterVT = TLI->getRegisterType (*DAG.getContext (), ValueVT );
11633
+ ISD::InputArg RetArg (Flags, RegisterVT, ValueVT , true ,
11651
11634
ISD::InputArg::NoArgIndex, 0 );
11652
11635
Ins.push_back (RetArg);
11653
11636
}
@@ -11830,12 +11813,7 @@ void SelectionDAGISel::LowerArguments(const Function &F) {
11830
11813
if (!FuncInfo->CanLowerReturn ) {
11831
11814
// Create a virtual register for the sret pointer, and put in a copy
11832
11815
// from the sret argument into it.
11833
- SmallVector<EVT, 1> ValueVTs;
11834
- ComputeValueVTs(*TLI, DAG.getDataLayout(),
11835
- PointerType::get(F.getContext(),
11836
- DAG.getDataLayout().getAllocaAddrSpace()),
11837
- ValueVTs);
11838
- MVT VT = ValueVTs[0].getSimpleVT();
11816
+ MVT VT = TLI->getPointerTy (DL, DL.getAllocaAddrSpace ());
11839
11817
MVT RegVT = TLI->getRegisterType (*CurDAG->getContext (), VT);
11840
11818
std::optional<ISD::NodeType> AssertOp;
11841
11819
SDValue ArgValue =
0 commit comments