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BoyaoWang430BoyaoWang430
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[RISCV] Add load/store clustering in post machine schedule (#111504)
#73789 added load clustering and #73796 tried to add store clustering. If post machine schedule is used, previous cluster of load/store which formed in machine schedule may break. In order to solve this, add load/sotre clustering to post machine schedule.
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‎llvm/lib/Target/RISCV/RISCVTargetMachine.cpp

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@@ -99,6 +99,11 @@ static cl::opt<bool> EnableMISchedLoadStoreClustering(
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cl::desc("Enable load and store clustering in the machine scheduler"),
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cl::init(true));
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static cl::opt<bool> EnablePostMISchedLoadStoreClustering(
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"riscv-postmisched-load-store-clustering", cl::Hidden,
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cl::desc("Enable PostRA load and store clustering in the machine scheduler"),
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cl::init(true));
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static cl::opt<bool>
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EnableVLOptimizer("riscv-enable-vl-optimizer",
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cl::desc("Enable the RISC-V VL Optimizer pass"),
@@ -360,6 +365,19 @@ class RISCVPassConfig : public TargetPassConfig {
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return DAG;
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}
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ScheduleDAGInstrs *
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createPostMachineScheduler(MachineSchedContext *C) const override {
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ScheduleDAGMI *DAG = nullptr;
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if (EnablePostMISchedLoadStoreClustering) {
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DAG = createGenericSchedPostRA(C);
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DAG->addMutation(createLoadClusterDAGMutation(
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DAG->TII, DAG->TRI, /*ReorderWhileClustering=*/true));
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DAG->addMutation(createStoreClusterDAGMutation(
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DAG->TII, DAG->TRI, /*ReorderWhileClustering=*/true));
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}
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return DAG;
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}
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void addIRPasses() override;
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bool addPreISel() override;
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void addCodeGenPrepare() override;

‎llvm/test/CodeGen/RISCV/misched-mem-clustering.mir

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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5
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# RUN: llc -mtriple=riscv64 -x mir -mcpu=sifive-p470 -verify-misched -enable-post-misched=false \
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# RUN: -riscv-postmisched-load-store-clustering=false -debug-only=machine-scheduler \
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# RUN: -start-before=machine-scheduler -stop-after=postmisched -o - 2>&1 < %s \
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# RUN: | FileCheck -check-prefix=NOPOSTMISCHED %s
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# RUN: llc -mtriple=riscv64 -x mir -mcpu=sifive-p470 -mattr=+use-postra-scheduler -verify-misched -enable-post-misched=true \
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# RUN: -riscv-postmisched-load-store-clustering=false -debug-only=machine-scheduler \
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# RUN: -start-before=machine-scheduler -stop-after=postmisched -o - 2>&1 < %s \
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# RUN: | FileCheck -check-prefix=NOCLUSTER %s
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# RUN: llc -mtriple=riscv64 -x mir -mcpu=sifive-p470 -mattr=+use-postra-scheduler -verify-misched -enable-post-misched=true \
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# RUN: -debug-only=machine-scheduler \
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# RUN: -start-before=machine-scheduler -stop-after=postmisched -o - 2>&1 < %s \
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# RUN: | FileCheck -check-prefix=MEMCLUSTER %s
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...
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---
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name: mem_clustering_1
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $x6, $x10, $x14, $x15, $x16, $x17
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; NOPOSTMISCHED-LABEL: name: mem_clustering_1
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; NOPOSTMISCHED: liveins: $x6, $x10, $x14, $x15, $x16, $x17
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; NOPOSTMISCHED-NEXT: {{ $}}
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; NOPOSTMISCHED-NEXT: renamable $x5 = LW renamable $x15, 0 :: (load (s32))
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; NOPOSTMISCHED-NEXT: renamable $x7 = LW renamable $x15, 8 :: (load (s32))
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; NOPOSTMISCHED-NEXT: renamable $x28 = LW renamable $x15, 16 :: (load (s32))
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; NOPOSTMISCHED-NEXT: renamable $x29 = LW renamable $x15, 24 :: (load (s32))
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; NOPOSTMISCHED-NEXT: renamable $x11 = ADDW renamable $x6, killed renamable $x5
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; NOPOSTMISCHED-NEXT: renamable $x13 = ADDW killed renamable $x7, killed renamable $x28
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; NOPOSTMISCHED-NEXT: renamable $x11 = ADDW killed renamable $x11, killed renamable $x13
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; NOPOSTMISCHED-NEXT: renamable $x6 = ADDW killed renamable $x11, killed renamable $x29
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; NOPOSTMISCHED-NEXT: SW renamable $x14, renamable $x15, 0 :: (store (s32))
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; NOPOSTMISCHED-NEXT: SW renamable $x14, renamable $x15, 8 :: (store (s32))
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; NOPOSTMISCHED-NEXT: SW renamable $x14, renamable $x15, 16 :: (store (s32))
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; NOPOSTMISCHED-NEXT: SW renamable $x14, renamable $x15, 24 :: (store (s32))
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; NOPOSTMISCHED-NEXT: PseudoRET
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;
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; NOCLUSTER-LABEL: name: mem_clustering_1
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; NOCLUSTER: liveins: $x6, $x10, $x14, $x15, $x16, $x17
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; NOCLUSTER-NEXT: {{ $}}
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; NOCLUSTER-NEXT: renamable $x5 = LW renamable $x15, 0 :: (load (s32))
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; NOCLUSTER-NEXT: SW renamable $x14, renamable $x15, 0 :: (store (s32))
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; NOCLUSTER-NEXT: renamable $x11 = ADDW killed renamable $x6, killed renamable $x5
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; NOCLUSTER-NEXT: renamable $x7 = LW renamable $x15, 8 :: (load (s32))
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; NOCLUSTER-NEXT: renamable $x28 = LW renamable $x15, 16 :: (load (s32))
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; NOCLUSTER-NEXT: renamable $x29 = LW renamable $x15, 24 :: (load (s32))
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; NOCLUSTER-NEXT: renamable $x13 = ADDW killed renamable $x7, killed renamable $x28
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; NOCLUSTER-NEXT: SW renamable $x14, renamable $x15, 8 :: (store (s32))
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; NOCLUSTER-NEXT: SW renamable $x14, renamable $x15, 16 :: (store (s32))
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; NOCLUSTER-NEXT: SW killed renamable $x14, killed renamable $x15, 24 :: (store (s32))
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; NOCLUSTER-NEXT: renamable $x11 = ADDW killed renamable $x11, killed renamable $x13
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; NOCLUSTER-NEXT: renamable $x6 = ADDW killed renamable $x11, killed renamable $x29
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; NOCLUSTER-NEXT: PseudoRET
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;
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; MEMCLUSTER-LABEL: name: mem_clustering_1
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; MEMCLUSTER: liveins: $x6, $x10, $x14, $x15, $x16, $x17
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; MEMCLUSTER-NEXT: {{ $}}
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; MEMCLUSTER-NEXT: renamable $x5 = LW renamable $x15, 0 :: (load (s32))
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; MEMCLUSTER-NEXT: renamable $x7 = LW renamable $x15, 8 :: (load (s32))
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; MEMCLUSTER-NEXT: renamable $x28 = LW renamable $x15, 16 :: (load (s32))
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; MEMCLUSTER-NEXT: renamable $x29 = LW renamable $x15, 24 :: (load (s32))
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; MEMCLUSTER-NEXT: SW renamable $x14, renamable $x15, 0 :: (store (s32))
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; MEMCLUSTER-NEXT: SW renamable $x14, renamable $x15, 8 :: (store (s32))
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; MEMCLUSTER-NEXT: SW renamable $x14, renamable $x15, 16 :: (store (s32))
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; MEMCLUSTER-NEXT: SW killed renamable $x14, killed renamable $x15, 24 :: (store (s32))
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; MEMCLUSTER-NEXT: renamable $x11 = ADDW killed renamable $x6, killed renamable $x5
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; MEMCLUSTER-NEXT: renamable $x13 = ADDW killed renamable $x7, killed renamable $x28
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; MEMCLUSTER-NEXT: renamable $x11 = ADDW killed renamable $x11, killed renamable $x13
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; MEMCLUSTER-NEXT: renamable $x6 = ADDW killed renamable $x11, killed renamable $x29
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; MEMCLUSTER-NEXT: PseudoRET
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renamable $x5 = LW renamable $x15, 0 :: (load (s32))
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renamable $x7 = LW renamable $x15, 8 :: (load (s32))
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renamable $x28 = LW renamable $x15, 16 :: (load (s32))
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renamable $x29 = LW renamable $x15, 24 :: (load (s32))
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renamable $x11 = ADDW killed renamable $x6, killed renamable $x5
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renamable $x13 = ADDW killed renamable $x7, killed renamable $x28
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renamable $x11 = ADDW killed renamable $x11, killed renamable $x13
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renamable $x6 = ADDW killed renamable $x11, killed renamable $x29
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SW renamable $x14, renamable $x15, 0 :: (store (s32))
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SW renamable $x14, renamable $x15, 8 :: (store (s32))
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SW renamable $x14, renamable $x15, 16 :: (store (s32))
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SW renamable $x14, renamable $x15, 24 :: (store (s32))
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PseudoRET
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...

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