AMDGPU: Fix true16 d16 entry table for DS pseudos (#156419)

arsenm · web-flow · commit 681046e3a5d9 · 2025-09-03T00:45:11.000Z
This should be trying to use the _gfx9 variants of DS pseudos,
not the base form with m0 uses.
diff --git a/llvm/lib/Target/AMDGPU/DSInstructions.td b/llvm/lib/Target/AMDGPU/DSInstructions.td
@@ -127,11 +127,12 @@ multiclass DS_1A1D_NORET_mc<string opName, RegisterClass rc = VGPR_32> {
   }
 }
 
-multiclass DS_1A1D_NORET_t16<string opName, RegisterClass rc = VGPR_32> 
+multiclass DS_1A1D_NORET_t16<string opName, RegisterClass rc = VGPR_32>
 : DS_1A1D_NORET_mc<opName, rc> {
   let has_m0_read = 0 in {
     let True16Predicate = UseRealTrue16Insts in {
-      def "_t16" : DS_1A1D_NORET<opName#"_t16", VGPR_16>, True16D16Table<NAME#"_D16_HI", NAME>;
+      def "_t16" : DS_1A1D_NORET<opName#"_t16", VGPR_16>,
+        True16D16Table<NAME#"_D16_HI", NAME#"_gfx9">;
     }
   }
 }

Original file line number	Diff line number	Diff line change
`@@ -127,11 +127,12 @@ multiclass DS_1A1D_NORET_mc<string opName, RegisterClass rc = VGPR_32> {`
`127`	`127`	`}`
`128`	`128`	`}`
`129`	`129`
`130`		`-multiclass DS_1A1D_NORET_t16<string opName, RegisterClass rc = VGPR_32>`
	`130`	`+multiclass DS_1A1D_NORET_t16<string opName, RegisterClass rc = VGPR_32>`
`131`	`131`	`: DS_1A1D_NORET_mc<opName, rc> {`
`132`	`132`	`let has_m0_read = 0 in {`
`133`	`133`	`let True16Predicate = UseRealTrue16Insts in {`
`134`		`- def "_t16" : DS_1A1D_NORET<opName#"_t16", VGPR_16>, True16D16Table<NAME#"_D16_HI", NAME>;`
	`134`	`+ def "_t16" : DS_1A1D_NORET<opName#"_t16", VGPR_16>,`
	`135`	`+ True16D16Table<NAME#"_D16_HI", NAME#"_gfx9">;`
`135`	`136`	`}`
`136`	`137`	`}`
`137`	`138`	`}`