2
2
; RUN: opt < %s -passes=msan -S | FileCheck %s
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;
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4
; Forked from llvm/test/CodeGen/AArch64/arm64-uminv.ll
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- ;
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- ; Handled suboptimally (visitInstruction):
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- ; - llvm.aarch64.neon.smaxv
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5
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target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"
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target triple = "aarch64--linux-android9001"
@@ -15,16 +12,12 @@ define signext i8 @test_vmaxv_s8(<8 x i8> %a1) #0 {
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; CHECK-NEXT: [[ENTRY:.*:]]
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; CHECK-NEXT: [[TMP0:%.*]] = load <8 x i8>, ptr @__msan_param_tls, align 8
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; CHECK-NEXT: call void @llvm.donothing()
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- ; CHECK-NEXT: [[TMP1:%.*]] = bitcast <8 x i8> [[TMP0]] to i64
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- ; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 0
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- ; CHECK-NEXT: br i1 [[_MSCMP]], label %[[BB2:.*]], label %[[BB3:.*]], !prof [[PROF1:![0-9]+]]
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- ; CHECK: [[BB2]]:
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- ; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR3:[0-9]+]]
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- ; CHECK-NEXT: unreachable
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- ; CHECK: [[BB3]]:
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+ ; CHECK-NEXT: [[TMP1:%.*]] = call i8 @llvm.vector.reduce.or.v8i8(<8 x i8> [[TMP0]])
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+ ; CHECK-NEXT: [[TMP2:%.*]] = zext i8 [[TMP1]] to i32
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; CHECK-NEXT: [[VMAXV_I:%.*]] = tail call i32 @llvm.aarch64.neon.smaxv.i32.v8i8(<8 x i8> [[A1]])
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+ ; CHECK-NEXT: [[_MSPROP:%.*]] = trunc i32 [[TMP2]] to i8
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; CHECK-NEXT: [[TMP4:%.*]] = trunc i32 [[VMAXV_I]] to i8
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- ; CHECK-NEXT: store i8 0 , ptr @__msan_retval_tls, align 8
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+ ; CHECK-NEXT: store i8 [[_MSPROP]] , ptr @__msan_retval_tls, align 8
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; CHECK-NEXT: ret i8 [[TMP4]]
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;
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entry:
@@ -39,16 +32,12 @@ define signext i16 @test_vmaxv_s16(<4 x i16> %a1) #0 {
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; CHECK-NEXT: [[ENTRY:.*:]]
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; CHECK-NEXT: [[TMP0:%.*]] = load <4 x i16>, ptr @__msan_param_tls, align 8
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; CHECK-NEXT: call void @llvm.donothing()
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- ; CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x i16> [[TMP0]] to i64
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- ; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 0
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- ; CHECK-NEXT: br i1 [[_MSCMP]], label %[[BB2:.*]], label %[[BB3:.*]], !prof [[PROF1]]
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- ; CHECK: [[BB2]]:
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- ; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR3]]
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- ; CHECK-NEXT: unreachable
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- ; CHECK: [[BB3]]:
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+ ; CHECK-NEXT: [[TMP1:%.*]] = call i16 @llvm.vector.reduce.or.v4i16(<4 x i16> [[TMP0]])
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+ ; CHECK-NEXT: [[TMP2:%.*]] = zext i16 [[TMP1]] to i32
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; CHECK-NEXT: [[VMAXV_I:%.*]] = tail call i32 @llvm.aarch64.neon.smaxv.i32.v4i16(<4 x i16> [[A1]])
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+ ; CHECK-NEXT: [[_MSPROP:%.*]] = trunc i32 [[TMP2]] to i16
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; CHECK-NEXT: [[TMP4:%.*]] = trunc i32 [[VMAXV_I]] to i16
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- ; CHECK-NEXT: store i16 0 , ptr @__msan_retval_tls, align 8
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+ ; CHECK-NEXT: store i16 [[_MSPROP]] , ptr @__msan_retval_tls, align 8
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; CHECK-NEXT: ret i16 [[TMP4]]
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;
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entry:
@@ -63,15 +52,9 @@ define i32 @test_vmaxv_s32(<2 x i32> %a1) #0 {
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; CHECK-NEXT: [[ENTRY:.*:]]
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; CHECK-NEXT: [[TMP0:%.*]] = load <2 x i32>, ptr @__msan_param_tls, align 8
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; CHECK-NEXT: call void @llvm.donothing()
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- ; CHECK-NEXT: [[TMP1:%.*]] = bitcast <2 x i32> [[TMP0]] to i64
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- ; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 0
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- ; CHECK-NEXT: br i1 [[_MSCMP]], label %[[BB2:.*]], label %[[BB3:.*]], !prof [[PROF1]]
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- ; CHECK: [[BB2]]:
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- ; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR3]]
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- ; CHECK-NEXT: unreachable
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- ; CHECK: [[BB3]]:
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+ ; CHECK-NEXT: [[TMP1:%.*]] = call i32 @llvm.vector.reduce.or.v2i32(<2 x i32> [[TMP0]])
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; CHECK-NEXT: [[VMAXV_I:%.*]] = tail call i32 @llvm.aarch64.neon.smaxv.i32.v2i32(<2 x i32> [[A1]])
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- ; CHECK-NEXT: store i32 0 , ptr @__msan_retval_tls, align 8
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+ ; CHECK-NEXT: store i32 [[TMP1]] , ptr @__msan_retval_tls, align 8
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; CHECK-NEXT: ret i32 [[VMAXV_I]]
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;
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entry:
@@ -85,16 +68,12 @@ define signext i8 @test_vmaxvq_s8(<16 x i8> %a1) #0 {
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; CHECK-NEXT: [[ENTRY:.*:]]
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; CHECK-NEXT: [[TMP0:%.*]] = load <16 x i8>, ptr @__msan_param_tls, align 8
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; CHECK-NEXT: call void @llvm.donothing()
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- ; CHECK-NEXT: [[TMP1:%.*]] = bitcast <16 x i8> [[TMP0]] to i128
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- ; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i128 [[TMP1]], 0
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- ; CHECK-NEXT: br i1 [[_MSCMP]], label %[[BB2:.*]], label %[[BB3:.*]], !prof [[PROF1]]
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- ; CHECK: [[BB2]]:
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- ; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR3]]
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- ; CHECK-NEXT: unreachable
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- ; CHECK: [[BB3]]:
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+ ; CHECK-NEXT: [[TMP1:%.*]] = call i8 @llvm.vector.reduce.or.v16i8(<16 x i8> [[TMP0]])
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+ ; CHECK-NEXT: [[TMP2:%.*]] = zext i8 [[TMP1]] to i32
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; CHECK-NEXT: [[VMAXV_I:%.*]] = tail call i32 @llvm.aarch64.neon.smaxv.i32.v16i8(<16 x i8> [[A1]])
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+ ; CHECK-NEXT: [[_MSPROP:%.*]] = trunc i32 [[TMP2]] to i8
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; CHECK-NEXT: [[TMP4:%.*]] = trunc i32 [[VMAXV_I]] to i8
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- ; CHECK-NEXT: store i8 0 , ptr @__msan_retval_tls, align 8
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+ ; CHECK-NEXT: store i8 [[_MSPROP]] , ptr @__msan_retval_tls, align 8
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; CHECK-NEXT: ret i8 [[TMP4]]
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;
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entry:
@@ -109,16 +88,12 @@ define signext i16 @test_vmaxvq_s16(<8 x i16> %a1) #0 {
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; CHECK-NEXT: [[ENTRY:.*:]]
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; CHECK-NEXT: [[TMP0:%.*]] = load <8 x i16>, ptr @__msan_param_tls, align 8
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; CHECK-NEXT: call void @llvm.donothing()
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- ; CHECK-NEXT: [[TMP1:%.*]] = bitcast <8 x i16> [[TMP0]] to i128
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- ; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i128 [[TMP1]], 0
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- ; CHECK-NEXT: br i1 [[_MSCMP]], label %[[BB2:.*]], label %[[BB3:.*]], !prof [[PROF1]]
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- ; CHECK: [[BB2]]:
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- ; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR3]]
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- ; CHECK-NEXT: unreachable
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- ; CHECK: [[BB3]]:
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+ ; CHECK-NEXT: [[TMP1:%.*]] = call i16 @llvm.vector.reduce.or.v8i16(<8 x i16> [[TMP0]])
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+ ; CHECK-NEXT: [[TMP2:%.*]] = zext i16 [[TMP1]] to i32
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; CHECK-NEXT: [[VMAXV_I:%.*]] = tail call i32 @llvm.aarch64.neon.smaxv.i32.v8i16(<8 x i16> [[A1]])
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+ ; CHECK-NEXT: [[_MSPROP:%.*]] = trunc i32 [[TMP2]] to i16
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; CHECK-NEXT: [[TMP4:%.*]] = trunc i32 [[VMAXV_I]] to i16
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- ; CHECK-NEXT: store i16 0 , ptr @__msan_retval_tls, align 8
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+ ; CHECK-NEXT: store i16 [[_MSPROP]] , ptr @__msan_retval_tls, align 8
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; CHECK-NEXT: ret i16 [[TMP4]]
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;
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entry:
@@ -133,15 +108,9 @@ define i32 @test_vmaxvq_s32(<4 x i32> %a1) #0 {
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; CHECK-NEXT: [[ENTRY:.*:]]
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; CHECK-NEXT: [[TMP0:%.*]] = load <4 x i32>, ptr @__msan_param_tls, align 8
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; CHECK-NEXT: call void @llvm.donothing()
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- ; CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x i32> [[TMP0]] to i128
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- ; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i128 [[TMP1]], 0
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- ; CHECK-NEXT: br i1 [[_MSCMP]], label %[[BB2:.*]], label %[[BB3:.*]], !prof [[PROF1]]
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- ; CHECK: [[BB2]]:
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- ; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR3]]
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- ; CHECK-NEXT: unreachable
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- ; CHECK: [[BB3]]:
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+ ; CHECK-NEXT: [[TMP1:%.*]] = call i32 @llvm.vector.reduce.or.v4i32(<4 x i32> [[TMP0]])
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; CHECK-NEXT: [[VMAXV_I:%.*]] = tail call i32 @llvm.aarch64.neon.smaxv.i32.v4i32(<4 x i32> [[A1]])
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- ; CHECK-NEXT: store i32 0 , ptr @__msan_retval_tls, align 8
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+ ; CHECK-NEXT: store i32 [[TMP1]] , ptr @__msan_retval_tls, align 8
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; CHECK-NEXT: ret i32 [[VMAXV_I]]
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;
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entry:
@@ -156,16 +125,12 @@ define <8 x i8> @test_vmaxv_s8_used_by_laneop(<8 x i8> %a1, <8 x i8> %a2) #0 {
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; CHECK-NEXT: [[TMP0:%.*]] = load <8 x i8>, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 8) to ptr), align 8
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; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i8>, ptr @__msan_param_tls, align 8
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; CHECK-NEXT: call void @llvm.donothing()
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- ; CHECK-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[TMP0]] to i64
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- ; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP2]], 0
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- ; CHECK-NEXT: br i1 [[_MSCMP]], label %[[BB3:.*]], label %[[BB4:.*]], !prof [[PROF1]]
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- ; CHECK: [[BB3]]:
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- ; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR3]]
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- ; CHECK-NEXT: unreachable
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- ; CHECK: [[BB4]]:
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+ ; CHECK-NEXT: [[TMP2:%.*]] = call i8 @llvm.vector.reduce.or.v8i8(<8 x i8> [[TMP0]])
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+ ; CHECK-NEXT: [[TMP3:%.*]] = zext i8 [[TMP2]] to i32
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; CHECK-NEXT: [[TMP5:%.*]] = tail call i32 @llvm.aarch64.neon.smaxv.i32.v8i8(<8 x i8> [[A2]])
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+ ; CHECK-NEXT: [[_MSPROP1:%.*]] = trunc i32 [[TMP3]] to i8
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; CHECK-NEXT: [[TMP6:%.*]] = trunc i32 [[TMP5]] to i8
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- ; CHECK-NEXT: [[_MSPROP:%.*]] = insertelement <8 x i8> [[TMP1]], i8 0 , i32 3
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+ ; CHECK-NEXT: [[_MSPROP:%.*]] = insertelement <8 x i8> [[TMP1]], i8 [[_MSPROP1]] , i32 3
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; CHECK-NEXT: [[TMP7:%.*]] = insertelement <8 x i8> [[A1]], i8 [[TMP6]], i32 3
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; CHECK-NEXT: store <8 x i8> [[_MSPROP]], ptr @__msan_retval_tls, align 8
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; CHECK-NEXT: ret <8 x i8> [[TMP7]]
@@ -184,16 +149,12 @@ define <4 x i16> @test_vmaxv_s16_used_by_laneop(<4 x i16> %a1, <4 x i16> %a2) #0
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; CHECK-NEXT: [[TMP0:%.*]] = load <4 x i16>, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 8) to ptr), align 8
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; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i16>, ptr @__msan_param_tls, align 8
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; CHECK-NEXT: call void @llvm.donothing()
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- ; CHECK-NEXT: [[TMP2:%.*]] = bitcast <4 x i16> [[TMP0]] to i64
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- ; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP2]], 0
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- ; CHECK-NEXT: br i1 [[_MSCMP]], label %[[BB3:.*]], label %[[BB4:.*]], !prof [[PROF1]]
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- ; CHECK: [[BB3]]:
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- ; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR3]]
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- ; CHECK-NEXT: unreachable
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- ; CHECK: [[BB4]]:
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+ ; CHECK-NEXT: [[TMP2:%.*]] = call i16 @llvm.vector.reduce.or.v4i16(<4 x i16> [[TMP0]])
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+ ; CHECK-NEXT: [[TMP3:%.*]] = zext i16 [[TMP2]] to i32
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; CHECK-NEXT: [[TMP5:%.*]] = tail call i32 @llvm.aarch64.neon.smaxv.i32.v4i16(<4 x i16> [[A2]])
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+ ; CHECK-NEXT: [[_MSPROP1:%.*]] = trunc i32 [[TMP3]] to i16
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; CHECK-NEXT: [[TMP6:%.*]] = trunc i32 [[TMP5]] to i16
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- ; CHECK-NEXT: [[_MSPROP:%.*]] = insertelement <4 x i16> [[TMP1]], i16 0 , i32 3
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+ ; CHECK-NEXT: [[_MSPROP:%.*]] = insertelement <4 x i16> [[TMP1]], i16 [[_MSPROP1]] , i32 3
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; CHECK-NEXT: [[TMP7:%.*]] = insertelement <4 x i16> [[A1]], i16 [[TMP6]], i32 3
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; CHECK-NEXT: store <4 x i16> [[_MSPROP]], ptr @__msan_retval_tls, align 8
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; CHECK-NEXT: ret <4 x i16> [[TMP7]]
@@ -212,15 +173,9 @@ define <2 x i32> @test_vmaxv_s32_used_by_laneop(<2 x i32> %a1, <2 x i32> %a2) #0
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; CHECK-NEXT: [[TMP0:%.*]] = load <2 x i32>, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 8) to ptr), align 8
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; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i32>, ptr @__msan_param_tls, align 8
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; CHECK-NEXT: call void @llvm.donothing()
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- ; CHECK-NEXT: [[TMP2:%.*]] = bitcast <2 x i32> [[TMP0]] to i64
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- ; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP2]], 0
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- ; CHECK-NEXT: br i1 [[_MSCMP]], label %[[BB3:.*]], label %[[BB4:.*]], !prof [[PROF1]]
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- ; CHECK: [[BB3]]:
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- ; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR3]]
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- ; CHECK-NEXT: unreachable
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- ; CHECK: [[BB4]]:
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+ ; CHECK-NEXT: [[TMP2:%.*]] = call i32 @llvm.vector.reduce.or.v2i32(<2 x i32> [[TMP0]])
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; CHECK-NEXT: [[TMP5:%.*]] = tail call i32 @llvm.aarch64.neon.smaxv.i32.v2i32(<2 x i32> [[A2]])
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- ; CHECK-NEXT: [[_MSPROP:%.*]] = insertelement <2 x i32> [[TMP1]], i32 0 , i32 1
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+ ; CHECK-NEXT: [[_MSPROP:%.*]] = insertelement <2 x i32> [[TMP1]], i32 [[TMP2]] , i32 1
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; CHECK-NEXT: [[TMP6:%.*]] = insertelement <2 x i32> [[A1]], i32 [[TMP5]], i32 1
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; CHECK-NEXT: store <2 x i32> [[_MSPROP]], ptr @__msan_retval_tls, align 8
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; CHECK-NEXT: ret <2 x i32> [[TMP6]]
@@ -238,16 +193,12 @@ define <16 x i8> @test_vmaxvq_s8_used_by_laneop(<16 x i8> %a1, <16 x i8> %a2) #0
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; CHECK-NEXT: [[TMP0:%.*]] = load <16 x i8>, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 16) to ptr), align 8
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; CHECK-NEXT: [[TMP1:%.*]] = load <16 x i8>, ptr @__msan_param_tls, align 8
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; CHECK-NEXT: call void @llvm.donothing()
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- ; CHECK-NEXT: [[TMP2:%.*]] = bitcast <16 x i8> [[TMP0]] to i128
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- ; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i128 [[TMP2]], 0
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- ; CHECK-NEXT: br i1 [[_MSCMP]], label %[[BB3:.*]], label %[[BB4:.*]], !prof [[PROF1]]
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- ; CHECK: [[BB3]]:
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- ; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR3]]
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- ; CHECK-NEXT: unreachable
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- ; CHECK: [[BB4]]:
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+ ; CHECK-NEXT: [[TMP2:%.*]] = call i8 @llvm.vector.reduce.or.v16i8(<16 x i8> [[TMP0]])
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+ ; CHECK-NEXT: [[TMP3:%.*]] = zext i8 [[TMP2]] to i32
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; CHECK-NEXT: [[TMP5:%.*]] = tail call i32 @llvm.aarch64.neon.smaxv.i32.v16i8(<16 x i8> [[A2]])
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+ ; CHECK-NEXT: [[_MSPROP1:%.*]] = trunc i32 [[TMP3]] to i8
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; CHECK-NEXT: [[TMP6:%.*]] = trunc i32 [[TMP5]] to i8
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- ; CHECK-NEXT: [[_MSPROP:%.*]] = insertelement <16 x i8> [[TMP1]], i8 0 , i32 3
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+ ; CHECK-NEXT: [[_MSPROP:%.*]] = insertelement <16 x i8> [[TMP1]], i8 [[_MSPROP1]] , i32 3
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; CHECK-NEXT: [[TMP7:%.*]] = insertelement <16 x i8> [[A1]], i8 [[TMP6]], i32 3
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; CHECK-NEXT: store <16 x i8> [[_MSPROP]], ptr @__msan_retval_tls, align 8
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; CHECK-NEXT: ret <16 x i8> [[TMP7]]
@@ -266,16 +217,12 @@ define <8 x i16> @test_vmaxvq_s16_used_by_laneop(<8 x i16> %a1, <8 x i16> %a2) #
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; CHECK-NEXT: [[TMP0:%.*]] = load <8 x i16>, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 16) to ptr), align 8
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; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i16>, ptr @__msan_param_tls, align 8
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; CHECK-NEXT: call void @llvm.donothing()
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- ; CHECK-NEXT: [[TMP2:%.*]] = bitcast <8 x i16> [[TMP0]] to i128
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- ; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i128 [[TMP2]], 0
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- ; CHECK-NEXT: br i1 [[_MSCMP]], label %[[BB3:.*]], label %[[BB4:.*]], !prof [[PROF1]]
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- ; CHECK: [[BB3]]:
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- ; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR3]]
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- ; CHECK-NEXT: unreachable
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- ; CHECK: [[BB4]]:
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+ ; CHECK-NEXT: [[TMP2:%.*]] = call i16 @llvm.vector.reduce.or.v8i16(<8 x i16> [[TMP0]])
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+ ; CHECK-NEXT: [[TMP3:%.*]] = zext i16 [[TMP2]] to i32
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; CHECK-NEXT: [[TMP5:%.*]] = tail call i32 @llvm.aarch64.neon.smaxv.i32.v8i16(<8 x i16> [[A2]])
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+ ; CHECK-NEXT: [[_MSPROP1:%.*]] = trunc i32 [[TMP3]] to i16
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; CHECK-NEXT: [[TMP6:%.*]] = trunc i32 [[TMP5]] to i16
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- ; CHECK-NEXT: [[_MSPROP:%.*]] = insertelement <8 x i16> [[TMP1]], i16 0 , i32 3
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+ ; CHECK-NEXT: [[_MSPROP:%.*]] = insertelement <8 x i16> [[TMP1]], i16 [[_MSPROP1]] , i32 3
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; CHECK-NEXT: [[TMP7:%.*]] = insertelement <8 x i16> [[A1]], i16 [[TMP6]], i32 3
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; CHECK-NEXT: store <8 x i16> [[_MSPROP]], ptr @__msan_retval_tls, align 8
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; CHECK-NEXT: ret <8 x i16> [[TMP7]]
@@ -294,15 +241,9 @@ define <4 x i32> @test_vmaxvq_s32_used_by_laneop(<4 x i32> %a1, <4 x i32> %a2) #
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; CHECK-NEXT: [[TMP0:%.*]] = load <4 x i32>, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 16) to ptr), align 8
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; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i32>, ptr @__msan_param_tls, align 8
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; CHECK-NEXT: call void @llvm.donothing()
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- ; CHECK-NEXT: [[TMP2:%.*]] = bitcast <4 x i32> [[TMP0]] to i128
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- ; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i128 [[TMP2]], 0
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- ; CHECK-NEXT: br i1 [[_MSCMP]], label %[[BB3:.*]], label %[[BB4:.*]], !prof [[PROF1]]
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- ; CHECK: [[BB3]]:
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- ; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR3]]
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- ; CHECK-NEXT: unreachable
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- ; CHECK: [[BB4]]:
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+ ; CHECK-NEXT: [[TMP2:%.*]] = call i32 @llvm.vector.reduce.or.v4i32(<4 x i32> [[TMP0]])
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; CHECK-NEXT: [[TMP5:%.*]] = tail call i32 @llvm.aarch64.neon.smaxv.i32.v4i32(<4 x i32> [[A2]])
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- ; CHECK-NEXT: [[_MSPROP:%.*]] = insertelement <4 x i32> [[TMP1]], i32 0 , i32 3
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+ ; CHECK-NEXT: [[_MSPROP:%.*]] = insertelement <4 x i32> [[TMP1]], i32 [[TMP2]] , i32 3
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; CHECK-NEXT: [[TMP6:%.*]] = insertelement <4 x i32> [[A1]], i32 [[TMP5]], i32 3
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; CHECK-NEXT: store <4 x i32> [[_MSPROP]], ptr @__msan_retval_tls, align 8
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; CHECK-NEXT: ret <4 x i32> [[TMP6]]
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