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LiqinWengLiqinWeng
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[LV][EVL] Support cast instruction with EVL-vectorization
1 parent 63dab72 commit 636eb6f

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7 files changed

+365
-16
lines changed

7 files changed

+365
-16
lines changed

‎llvm/lib/Transforms/Vectorize/LoopVectorize.cpp

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -4490,6 +4490,7 @@ static bool willGenerateVectors(VPlan &Plan, ElementCount VF,
44904490
case VPDef::VPWidenCallSC:
44914491
case VPDef::VPWidenCanonicalIVSC:
44924492
case VPDef::VPWidenCastSC:
4493+
case VPDef::VPWidenCastEVLSC:
44934494
case VPDef::VPWidenGEPSC:
44944495
case VPDef::VPWidenSC:
44954496
case VPDef::VPWidenSelectSC:

‎llvm/lib/Transforms/Vectorize/VPlan.h

Lines changed: 72 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -921,6 +921,7 @@ class VPSingleDefRecipe : public VPRecipeBase, public VPValue {
921921
case VPRecipeBase::VPWidenCallSC:
922922
case VPRecipeBase::VPWidenCanonicalIVSC:
923923
case VPRecipeBase::VPWidenCastSC:
924+
case VPRecipeBase::VPWidenCastEVLSC:
924925
case VPRecipeBase::VPWidenGEPSC:
925926
case VPRecipeBase::VPWidenSC:
926927
case VPRecipeBase::VPWidenEVLSC:
@@ -1111,6 +1112,7 @@ class VPRecipeWithIRFlags : public VPSingleDefRecipe {
11111112
R->getVPDefID() == VPRecipeBase::VPWidenEVLSC ||
11121113
R->getVPDefID() == VPRecipeBase::VPWidenGEPSC ||
11131114
R->getVPDefID() == VPRecipeBase::VPWidenCastSC ||
1115+
R->getVPDefID() == VPRecipeBase::VPWidenCastEVLSC ||
11141116
R->getVPDefID() == VPRecipeBase::VPReplicateSC ||
11151117
R->getVPDefID() == VPRecipeBase::VPVectorPointerSC;
11161118
}
@@ -1514,19 +1516,28 @@ class VPWidenCastRecipe : public VPRecipeWithIRFlags {
15141516
/// Result type for the cast.
15151517
Type *ResultTy;
15161518

1517-
public:
1518-
VPWidenCastRecipe(Instruction::CastOps Opcode, VPValue *Op, Type *ResultTy,
1519-
CastInst &UI)
1519+
protected:
1520+
VPWidenCastRecipe(unsigned VPDefOpcode, Instruction::CastOps Opcode,
1521+
VPValue *Op, Type *ResultTy, CastInst &UI)
15201522
: VPRecipeWithIRFlags(VPDef::VPWidenCastSC, Op, UI), Opcode(Opcode),
15211523
ResultTy(ResultTy) {
15221524
assert(UI.getOpcode() == Opcode &&
15231525
"opcode of underlying cast doesn't match");
15241526
}
15251527

1526-
VPWidenCastRecipe(Instruction::CastOps Opcode, VPValue *Op, Type *ResultTy)
1528+
VPWidenCastRecipe(unsigned VPDefOpcode, Instruction::CastOps Opcode,
1529+
VPValue *Op, Type *ResultTy)
15271530
: VPRecipeWithIRFlags(VPDef::VPWidenCastSC, Op), Opcode(Opcode),
15281531
ResultTy(ResultTy) {}
15291532

1533+
public:
1534+
VPWidenCastRecipe(Instruction::CastOps Opcode, VPValue *Op, Type *ResultTy,
1535+
CastInst &UI)
1536+
: VPWidenCastRecipe(VPDef::VPWidenCastSC, Opcode, Op, ResultTy, UI) {}
1537+
1538+
VPWidenCastRecipe(Instruction::CastOps Opcode, VPValue *Op, Type *ResultTy)
1539+
: VPWidenCastRecipe(VPDef::VPWidenCastSC, Opcode, Op, ResultTy) {}
1540+
15301541
~VPWidenCastRecipe() override = default;
15311542

15321543
VPWidenCastRecipe *clone() override {
@@ -1537,7 +1548,15 @@ class VPWidenCastRecipe : public VPRecipeWithIRFlags {
15371548
return new VPWidenCastRecipe(Opcode, getOperand(0), ResultTy);
15381549
}
15391550

1540-
VP_CLASSOF_IMPL(VPDef::VPWidenCastSC)
1551+
static inline bool classof(const VPRecipeBase *R) {
1552+
return R->getVPDefID() == VPRecipeBase::VPWidenCastSC ||
1553+
R->getVPDefID() == VPRecipeBase::VPWidenCastEVLSC;
1554+
}
1555+
1556+
static inline bool classof(const VPUser *U) {
1557+
auto *R = dyn_cast<VPRecipeBase>(U);
1558+
return R && classof(R);
1559+
}
15411560

15421561
/// Produce widened copies of the cast.
15431562
void execute(VPTransformState &State) override;
@@ -1554,6 +1573,54 @@ class VPWidenCastRecipe : public VPRecipeWithIRFlags {
15541573
Type *getResultType() const { return ResultTy; }
15551574
};
15561575

1576+
// A recipe for widening cast operation with vector-predication intrinsics with
1577+
/// explicit vector length (EVL).
1578+
class VPWidenCastEVLRecipe : public VPWidenCastRecipe {
1579+
using VPRecipeWithIRFlags::transferFlags;
1580+
1581+
public:
1582+
VPWidenCastEVLRecipe(Instruction::CastOps Opcode, VPValue *Op, Type *ResultTy,
1583+
VPValue &EVL)
1584+
: VPWidenCastRecipe(VPDef::VPWidenCastEVLSC, Opcode, Op, ResultTy) {
1585+
addOperand(&EVL);
1586+
}
1587+
VPWidenCastEVLRecipe(VPWidenCastRecipe &W, VPValue &EVL)
1588+
: VPWidenCastEVLRecipe(W.getOpcode(), W.getOperand(0), W.getResultType(),
1589+
EVL) {
1590+
transferFlags(W);
1591+
}
1592+
1593+
~VPWidenCastEVLRecipe() override = default;
1594+
1595+
VPWidenCastEVLRecipe *clone() final {
1596+
llvm_unreachable("VPWidenEVLRecipe cannot be cloned");
1597+
return nullptr;
1598+
}
1599+
1600+
VP_CLASSOF_IMPL(VPDef::VPWidenCastEVLSC)
1601+
1602+
VPValue *getEVL() { return getOperand(getNumOperands() - 1); }
1603+
const VPValue *getEVL() const { return getOperand(getNumOperands() - 1); }
1604+
1605+
/// Produce a vp-intrinsic copies of the cast.
1606+
void execute(VPTransformState &State) final;
1607+
1608+
/// Returns true if the recipe only uses the first lane of operand \p Op.
1609+
bool onlyFirstLaneUsed(const VPValue *Op) const override {
1610+
assert(is_contained(operands(), Op) &&
1611+
"Op must be an operand of the recipe");
1612+
// EVL in that recipe is always the last operand, thus any use before means
1613+
// the VPValue should be vectorized.
1614+
return getEVL() == Op;
1615+
}
1616+
1617+
#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
1618+
/// Print the recipe.
1619+
void print(raw_ostream &O, const Twine &Indent,
1620+
VPSlotTracker &SlotTracker) const final;
1621+
#endif
1622+
};
1623+
15571624
/// VPScalarCastRecipe is a recipe to create scalar cast instructions.
15581625
class VPScalarCastRecipe : public VPSingleDefRecipe {
15591626
Instruction::CastOps Opcode;

‎llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp

Lines changed: 45 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -69,6 +69,7 @@ bool VPRecipeBase::mayWriteToMemory() const {
6969
case VPReductionSC:
7070
case VPWidenCanonicalIVSC:
7171
case VPWidenCastSC:
72+
case VPWidenCastEVLSC:
7273
case VPWidenGEPSC:
7374
case VPWidenIntOrFpInductionSC:
7475
case VPWidenLoadEVLSC:
@@ -112,6 +113,7 @@ bool VPRecipeBase::mayReadFromMemory() const {
112113
case VPReductionSC:
113114
case VPWidenCanonicalIVSC:
114115
case VPWidenCastSC:
116+
case VPWidenCastEVLSC:
115117
case VPWidenGEPSC:
116118
case VPWidenIntOrFpInductionSC:
117119
case VPWidenPHISC:
@@ -162,6 +164,7 @@ bool VPRecipeBase::mayHaveSideEffects() const {
162164
case VPScalarIVStepsSC:
163165
case VPWidenCanonicalIVSC:
164166
case VPWidenCastSC:
167+
case VPWidenCastEVLSC:
165168
case VPWidenGEPSC:
166169
case VPWidenIntOrFpInductionSC:
167170
case VPWidenPHISC:
@@ -1344,12 +1347,53 @@ void VPWidenCastRecipe::execute(VPTransformState &State) {
13441347
}
13451348
}
13461349

1350+
void VPWidenCastEVLRecipe::execute(VPTransformState &State) {
1351+
unsigned Opcode = getOpcode();
1352+
State.setDebugLocFrom(getDebugLoc());
1353+
assert(State.UF == 1 && "Expected only UF == 1 when vectorizing with "
1354+
"explicit vector length.");
1355+
1356+
// TODO: add more cast instruction, eg: fptoint/inttofp/inttoptr/fptofp
1357+
if (Opcode == Instruction::SExt || Opcode == Instruction::ZExt ||
1358+
Opcode == Instruction::Trunc) {
1359+
Value *SrcVal = State.get(getOperand(0), 0);
1360+
VectorType *DsType = VectorType::get(getResultType(), State.VF);
1361+
1362+
IRBuilderBase &BuilderIR = State.Builder;
1363+
VectorBuilder Builder(BuilderIR);
1364+
Value *Mask = BuilderIR.CreateVectorSplat(State.VF, BuilderIR.getTrue());
1365+
Builder.setMask(Mask).setEVL(State.get(getEVL(), 0, /*NeedsScalar=*/true));
1366+
1367+
Value *VPInst =
1368+
Builder.createVectorInstruction(Opcode, DsType, {SrcVal}, "vp.cast");
1369+
1370+
if (VPInst) {
1371+
if (auto *VecOp = dyn_cast<CastInst>(VPInst))
1372+
VecOp->copyIRFlags(getUnderlyingInstr());
1373+
}
1374+
1375+
State.set(this, VPInst, 0);
1376+
State.addMetadata(VPInst,
1377+
dyn_cast_or_null<Instruction>(getUnderlyingValue()));
1378+
}
1379+
}
1380+
13471381
#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
13481382
void VPWidenCastRecipe::print(raw_ostream &O, const Twine &Indent,
13491383
VPSlotTracker &SlotTracker) const {
13501384
O << Indent << "WIDEN-CAST ";
13511385
printAsOperand(O, SlotTracker);
1352-
O << " = " << Instruction::getOpcodeName(Opcode) << " ";
1386+
O << " = " << Instruction::getOpcodeName(Opcode);
1387+
printFlags(O);
1388+
printOperands(O, SlotTracker);
1389+
O << " to " << *getResultType();
1390+
}
1391+
1392+
void VPWidenCastEVLRecipe::print(raw_ostream &O, const Twine &Indent,
1393+
VPSlotTracker &SlotTracker) const {
1394+
O << Indent << "WIDEN-CAST ";
1395+
printAsOperand(O, SlotTracker);
1396+
O << " = vp." << Instruction::getOpcodeName(getOpcode());
13531397
printFlags(O);
13541398
printOperands(O, SlotTracker);
13551399
O << " to " << *getResultType();

‎llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp

Lines changed: 9 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1349,6 +1349,15 @@ static void transformRecipestoEVLRecipes(VPlan &Plan, VPValue &EVL) {
13491349
return nullptr;
13501350
return new VPWidenEVLRecipe(*W, EVL);
13511351
})
1352+
.Case<VPWidenCastRecipe>(
1353+
[&](VPWidenCastRecipe *W) -> VPRecipeBase * {
1354+
unsigned Opcode = W->getOpcode();
1355+
if (Opcode != Instruction::SExt &&
1356+
Opcode != Instruction::ZExt &&
1357+
Opcode != Instruction::Trunc)
1358+
return nullptr;
1359+
return new VPWidenCastEVLRecipe(*W, EVL);
1360+
})
13521361
.Case<VPReductionRecipe>([&](VPReductionRecipe *Red) {
13531362
VPValue *NewMask = GetNewMask(Red->getCondOp());
13541363
return new VPReductionEVLRecipe(*Red, EVL, NewMask);

‎llvm/lib/Transforms/Vectorize/VPlanValue.h

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -350,6 +350,7 @@ class VPDef {
350350
VPWidenCallSC,
351351
VPWidenCanonicalIVSC,
352352
VPWidenCastSC,
353+
VPWidenCastEVLSC,
353354
VPWidenGEPSC,
354355
VPWidenLoadEVLSC,
355356
VPWidenLoadSC,

‎llvm/test/Transforms/LoopVectorize/RISCV/inloop-reduction.ll

Lines changed: 10 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -159,38 +159,38 @@ define i32 @add_i16_i32(ptr nocapture readonly %x, i32 %n) {
159159
; IF-EVL-INLOOP: vector.body:
160160
; IF-EVL-INLOOP-NEXT: [[INDEX:%.*]] = phi i32 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ]
161161
; IF-EVL-INLOOP-NEXT: [[EVL_BASED_IV:%.*]] = phi i32 [ 0, [[VECTOR_PH]] ], [ [[INDEX_EVL_NEXT:%.*]], [[VECTOR_BODY]] ]
162-
; IF-EVL-INLOOP-NEXT: [[VEC_PHI:%.*]] = phi i32 [ 0, [[VECTOR_PH]] ], [ [[TMP12:%.*]], [[VECTOR_BODY]] ]
162+
; IF-EVL-INLOOP-NEXT: [[VEC_PHI:%.*]] = phi i32 [ 0, [[VECTOR_PH]] ], [ [[TMP11:%.*]], [[VECTOR_BODY]] ]
163163
; IF-EVL-INLOOP-NEXT: [[TMP5:%.*]] = sub i32 [[N]], [[EVL_BASED_IV]]
164164
; IF-EVL-INLOOP-NEXT: [[TMP6:%.*]] = call i32 @llvm.experimental.get.vector.length.i32(i32 [[TMP5]], i32 8, i1 true)
165165
; IF-EVL-INLOOP-NEXT: [[TMP7:%.*]] = add i32 [[EVL_BASED_IV]], 0
166166
; IF-EVL-INLOOP-NEXT: [[TMP8:%.*]] = getelementptr inbounds i16, ptr [[X:%.*]], i32 [[TMP7]]
167167
; IF-EVL-INLOOP-NEXT: [[TMP9:%.*]] = getelementptr inbounds i16, ptr [[TMP8]], i32 0
168168
; IF-EVL-INLOOP-NEXT: [[VP_OP_LOAD:%.*]] = call <vscale x 8 x i16> @llvm.vp.load.nxv8i16.p0(ptr align 2 [[TMP9]], <vscale x 8 x i1> shufflevector (<vscale x 8 x i1> insertelement (<vscale x 8 x i1> poison, i1 true, i64 0), <vscale x 8 x i1> poison, <vscale x 8 x i32> zeroinitializer), i32 [[TMP6]])
169-
; IF-EVL-INLOOP-NEXT: [[TMP10:%.*]] = sext <vscale x 8 x i16> [[VP_OP_LOAD]] to <vscale x 8 x i32>
170-
; IF-EVL-INLOOP-NEXT: [[TMP11:%.*]] = call i32 @llvm.vp.reduce.add.nxv8i32(i32 0, <vscale x 8 x i32> [[TMP10]], <vscale x 8 x i1> shufflevector (<vscale x 8 x i1> insertelement (<vscale x 8 x i1> poison, i1 true, i64 0), <vscale x 8 x i1> poison, <vscale x 8 x i32> zeroinitializer), i32 [[TMP6]])
171-
; IF-EVL-INLOOP-NEXT: [[TMP12]] = add i32 [[TMP11]], [[VEC_PHI]]
169+
; IF-EVL-INLOOP-NEXT: [[VP_CAST:%.*]] = call <vscale x 8 x i32> @llvm.vp.sext.nxv8i32.nxv8i16(<vscale x 8 x i16> [[VP_OP_LOAD]], <vscale x 8 x i1> shufflevector (<vscale x 8 x i1> insertelement (<vscale x 8 x i1> poison, i1 true, i64 0), <vscale x 8 x i1> poison, <vscale x 8 x i32> zeroinitializer), i32 [[TMP6]])
170+
; IF-EVL-INLOOP-NEXT: [[TMP10:%.*]] = call i32 @llvm.vp.reduce.add.nxv8i32(i32 0, <vscale x 8 x i32> [[VP_CAST]], <vscale x 8 x i1> shufflevector (<vscale x 8 x i1> insertelement (<vscale x 8 x i1> poison, i1 true, i64 0), <vscale x 8 x i1> poison, <vscale x 8 x i32> zeroinitializer), i32 [[TMP6]])
171+
; IF-EVL-INLOOP-NEXT: [[TMP11]] = add i32 [[TMP10]], [[VEC_PHI]]
172172
; IF-EVL-INLOOP-NEXT: [[INDEX_EVL_NEXT]] = add i32 [[TMP6]], [[EVL_BASED_IV]]
173173
; IF-EVL-INLOOP-NEXT: [[INDEX_NEXT]] = add i32 [[INDEX]], [[TMP4]]
174-
; IF-EVL-INLOOP-NEXT: [[TMP13:%.*]] = icmp eq i32 [[INDEX_NEXT]], [[N_VEC]]
175-
; IF-EVL-INLOOP-NEXT: br i1 [[TMP13]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]]
174+
; IF-EVL-INLOOP-NEXT: [[TMP12:%.*]] = icmp eq i32 [[INDEX_NEXT]], [[N_VEC]]
175+
; IF-EVL-INLOOP-NEXT: br i1 [[TMP12]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]]
176176
; IF-EVL-INLOOP: middle.block:
177177
; IF-EVL-INLOOP-NEXT: br i1 true, label [[FOR_COND_CLEANUP_LOOPEXIT:%.*]], label [[SCALAR_PH]]
178178
; IF-EVL-INLOOP: scalar.ph:
179179
; IF-EVL-INLOOP-NEXT: [[BC_RESUME_VAL:%.*]] = phi i32 [ [[N_VEC]], [[MIDDLE_BLOCK]] ], [ 0, [[FOR_BODY_PREHEADER]] ]
180-
; IF-EVL-INLOOP-NEXT: [[BC_MERGE_RDX:%.*]] = phi i32 [ [[TMP12]], [[MIDDLE_BLOCK]] ], [ 0, [[FOR_BODY_PREHEADER]] ]
180+
; IF-EVL-INLOOP-NEXT: [[BC_MERGE_RDX:%.*]] = phi i32 [ [[TMP11]], [[MIDDLE_BLOCK]] ], [ 0, [[FOR_BODY_PREHEADER]] ]
181181
; IF-EVL-INLOOP-NEXT: br label [[FOR_BODY:%.*]]
182182
; IF-EVL-INLOOP: for.body:
183183
; IF-EVL-INLOOP-NEXT: [[I_08:%.*]] = phi i32 [ [[INC:%.*]], [[FOR_BODY]] ], [ [[BC_RESUME_VAL]], [[SCALAR_PH]] ]
184184
; IF-EVL-INLOOP-NEXT: [[R_07:%.*]] = phi i32 [ [[ADD:%.*]], [[FOR_BODY]] ], [ [[BC_MERGE_RDX]], [[SCALAR_PH]] ]
185185
; IF-EVL-INLOOP-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, ptr [[X]], i32 [[I_08]]
186-
; IF-EVL-INLOOP-NEXT: [[TMP14:%.*]] = load i16, ptr [[ARRAYIDX]], align 2
187-
; IF-EVL-INLOOP-NEXT: [[CONV:%.*]] = sext i16 [[TMP14]] to i32
186+
; IF-EVL-INLOOP-NEXT: [[TMP13:%.*]] = load i16, ptr [[ARRAYIDX]], align 2
187+
; IF-EVL-INLOOP-NEXT: [[CONV:%.*]] = sext i16 [[TMP13]] to i32
188188
; IF-EVL-INLOOP-NEXT: [[ADD]] = add nsw i32 [[R_07]], [[CONV]]
189189
; IF-EVL-INLOOP-NEXT: [[INC]] = add nuw nsw i32 [[I_08]], 1
190190
; IF-EVL-INLOOP-NEXT: [[EXITCOND:%.*]] = icmp eq i32 [[INC]], [[N]]
191191
; IF-EVL-INLOOP-NEXT: br i1 [[EXITCOND]], label [[FOR_COND_CLEANUP_LOOPEXIT]], label [[FOR_BODY]], !llvm.loop [[LOOP3:![0-9]+]]
192192
; IF-EVL-INLOOP: for.cond.cleanup.loopexit:
193-
; IF-EVL-INLOOP-NEXT: [[ADD_LCSSA:%.*]] = phi i32 [ [[ADD]], [[FOR_BODY]] ], [ [[TMP12]], [[MIDDLE_BLOCK]] ]
193+
; IF-EVL-INLOOP-NEXT: [[ADD_LCSSA:%.*]] = phi i32 [ [[ADD]], [[FOR_BODY]] ], [ [[TMP11]], [[MIDDLE_BLOCK]] ]
194194
; IF-EVL-INLOOP-NEXT: br label [[FOR_COND_CLEANUP]]
195195
; IF-EVL-INLOOP: for.cond.cleanup:
196196
; IF-EVL-INLOOP-NEXT: [[R_0_LCSSA:%.*]] = phi i32 [ 0, [[ENTRY:%.*]] ], [ [[ADD_LCSSA]], [[FOR_COND_CLEANUP_LOOPEXIT]] ]

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