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petar-avramovicpetar-avramovic
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AMDGPU/GlobalISel: Add regbanklegalize rule for load and readanylane tests
Add tests for missing readanylane combines from regbanklegalize. Add rule for uniform 64 bit addrspace(1) load that has to be regbanklegalized to vgpr dst that is readanylaned bask to sgpr.
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‎llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp

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@@ -646,6 +646,7 @@ RegBankLegalizeRules::RegBankLegalizeRules(const GCNSubtarget &_ST,
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.Any({{{UniB256, UniP1}, isAlign4 && isUL}, {{SgprB256}, {SgprP1}}})
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.Any({{{UniB512, UniP1}, isAlign4 && isUL}, {{SgprB512}, {SgprP1}}})
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.Any({{{UniB32, UniP1}, !isAlign4 || !isUL}, {{UniInVgprB32}, {SgprP1}}})
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.Any({{{UniB64, UniP1}, !isAlign4 || !isUL}, {{UniInVgprB64}, {SgprP1}}})
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.Any({{{UniB256, UniP1}, !isAlign4 || !isUL}, {{UniInVgprB256}, {VgprP1}, SplitLoad}})
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.Any({{{UniB512, UniP1}, !isAlign4 || !isUL}, {{UniInVgprB512}, {VgprP1}, SplitLoad}})
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‎llvm/test/CodeGen/AMDGPU/GlobalISel/readanylane-combines.ll

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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
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; RUN: llc -global-isel -mtriple=amdgcn-amd-amdpal -mcpu=gfx1010 -new-reg-bank-select < %s | FileCheck %s
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define amdgpu_ps void @readanylane_to_virtual_vgpr(ptr addrspace(1) inreg %ptr0, ptr addrspace(1) inreg %ptr1) {
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; CHECK-LABEL: readanylane_to_virtual_vgpr:
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; CHECK: ; %bb.0:
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; CHECK-NEXT: v_mov_b32_e32 v0, 0
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; CHECK-NEXT: global_load_dword v1, v0, s[0:1] glc dlc
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; CHECK-NEXT: s_waitcnt vmcnt(0)
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; CHECK-NEXT: global_store_dword v0, v1, s[2:3]
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; CHECK-NEXT: s_endpgm
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%load = load volatile float, ptr addrspace(1) %ptr0
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store float %load, ptr addrspace(1) %ptr1
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ret void
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}
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define amdgpu_ps float @readanylane_to_physical_vgpr(ptr addrspace(1) inreg %ptr) {
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; CHECK-LABEL: readanylane_to_physical_vgpr:
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; CHECK: ; %bb.0:
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; CHECK-NEXT: v_mov_b32_e32 v0, 0
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; CHECK-NEXT: global_load_dword v0, v0, s[0:1] glc dlc
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; CHECK-NEXT: s_waitcnt vmcnt(0)
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; CHECK-NEXT: v_readfirstlane_b32 s0, v0
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; CHECK-NEXT: v_mov_b32_e32 v0, s0
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; CHECK-NEXT: ; return to shader part epilog
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%load = load volatile float, ptr addrspace(1) %ptr
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ret float %load
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}
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define amdgpu_ps void @readanylane_to_bitcast_to_virtual_vgpr(ptr addrspace(1) inreg %ptr0, ptr addrspace(1) inreg %ptr1) {
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; CHECK-LABEL: readanylane_to_bitcast_to_virtual_vgpr:
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; CHECK: ; %bb.0:
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; CHECK-NEXT: v_mov_b32_e32 v0, 0
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; CHECK-NEXT: global_load_dword v1, v0, s[0:1] glc dlc
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; CHECK-NEXT: s_waitcnt vmcnt(0)
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; CHECK-NEXT: v_readfirstlane_b32 s0, v1
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; CHECK-NEXT: v_mov_b32_e32 v1, s0
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; CHECK-NEXT: global_store_dword v0, v1, s[2:3]
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; CHECK-NEXT: s_endpgm
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%load = load volatile <2 x i16>, ptr addrspace(1) %ptr0
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%bitcast = bitcast <2 x i16> %load to i32
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store i32 %bitcast, ptr addrspace(1) %ptr1
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ret void
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}
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define amdgpu_ps float @readanylane_to_bitcast_to_physical_vgpr(ptr addrspace(1) inreg %ptr0, ptr addrspace(1) inreg %ptr1) {
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; CHECK-LABEL: readanylane_to_bitcast_to_physical_vgpr:
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; CHECK: ; %bb.0:
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; CHECK-NEXT: v_mov_b32_e32 v0, 0
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; CHECK-NEXT: global_load_dword v0, v0, s[0:1] glc dlc
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; CHECK-NEXT: s_waitcnt vmcnt(0)
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; CHECK-NEXT: v_readfirstlane_b32 s0, v0
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; CHECK-NEXT: v_mov_b32_e32 v0, s0
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; CHECK-NEXT: ; return to shader part epilog
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%load = load volatile <2 x i16>, ptr addrspace(1) %ptr0
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%bitcast = bitcast <2 x i16> %load to float
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ret float %bitcast
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}
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define amdgpu_ps void @unmerge_readanylane_merge_to_virtual_vgpr(ptr addrspace(1) inreg %ptr0, ptr addrspace(1) inreg %ptr1) {
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; CHECK-LABEL: unmerge_readanylane_merge_to_virtual_vgpr:
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; CHECK: ; %bb.0:
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; CHECK-NEXT: v_mov_b32_e32 v2, 0
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; CHECK-NEXT: global_load_dwordx2 v[0:1], v2, s[0:1] glc dlc
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; CHECK-NEXT: s_waitcnt vmcnt(0)
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; CHECK-NEXT: v_readfirstlane_b32 s0, v0
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; CHECK-NEXT: v_readfirstlane_b32 s1, v1
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; CHECK-NEXT: v_mov_b32_e32 v0, s0
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; CHECK-NEXT: v_mov_b32_e32 v1, s1
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; CHECK-NEXT: global_store_dwordx2 v2, v[0:1], s[2:3]
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; CHECK-NEXT: s_endpgm
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%load = load volatile i64, ptr addrspace(1) %ptr0
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store i64 %load, ptr addrspace(1) %ptr1
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ret void
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}
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;define amdgpu_ps double @unmerge_readanylane_merge_to_physical_vgpr(ptr addrspace(1) inreg %ptr0, ptr addrspace(1) inreg %ptr1) {
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; %load = load volatile double, ptr addrspace(1) %ptr0
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; ret double %load
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;}
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define amdgpu_ps void @unmerge_readanylane_merge_bitcast_to_virtual_vgpr(ptr addrspace(1) inreg %ptr0, ptr addrspace(1) inreg %ptr1) {
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; CHECK-LABEL: unmerge_readanylane_merge_bitcast_to_virtual_vgpr:
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; CHECK: ; %bb.0:
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; CHECK-NEXT: v_mov_b32_e32 v2, 0
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; CHECK-NEXT: global_load_dwordx2 v[0:1], v2, s[0:1] glc dlc
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; CHECK-NEXT: s_waitcnt vmcnt(0)
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; CHECK-NEXT: v_readfirstlane_b32 s0, v0
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; CHECK-NEXT: v_readfirstlane_b32 s1, v1
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; CHECK-NEXT: v_mov_b32_e32 v0, s0
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; CHECK-NEXT: v_mov_b32_e32 v1, s1
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; CHECK-NEXT: global_store_dwordx2 v2, v[0:1], s[2:3]
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; CHECK-NEXT: s_endpgm
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%load = load volatile <2 x i32>, ptr addrspace(1) %ptr0
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%bitcast = bitcast <2 x i32> %load to double
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store double %bitcast, ptr addrspace(1) %ptr1
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ret void
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}
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;define amdgpu_ps double @unmerge_readanylane_merge_bitcast_to_physical_vgpr(ptr addrspace(1) inreg %ptr0, ptr addrspace(1) inreg %ptr1) {
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; %load = load volatile <2 x i32>, ptr addrspace(1) %ptr0
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; %bitcast = bitcast <2 x i32> %load to double
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; ret double %bitcast
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;}
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define amdgpu_ps void @unmerge_readanylane_merge_extract_to_virtual_vgpr(ptr addrspace(1) inreg %ptr0, ptr addrspace(1) inreg %ptr1) {
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; CHECK-LABEL: unmerge_readanylane_merge_extract_to_virtual_vgpr:
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; CHECK: ; %bb.0:
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; CHECK-NEXT: v_mov_b32_e32 v2, 0
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; CHECK-NEXT: global_load_dwordx2 v[0:1], v2, s[0:1] glc dlc
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; CHECK-NEXT: s_waitcnt vmcnt(0)
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; CHECK-NEXT: v_readfirstlane_b32 s0, v1
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; CHECK-NEXT: v_mov_b32_e32 v0, s0
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; CHECK-NEXT: global_store_dword v2, v0, s[2:3]
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; CHECK-NEXT: s_endpgm
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%load = load volatile <2 x i32>, ptr addrspace(1) %ptr0
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%extracted = extractelement <2 x i32> %load, i32 1
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store i32 %extracted, ptr addrspace(1) %ptr1
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ret void
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}
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define amdgpu_ps float @unmerge_readanylane_merge_extract_to_physical_vgpr(ptr addrspace(1) inreg %ptr0, ptr addrspace(1) inreg %ptr1) {
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; CHECK-LABEL: unmerge_readanylane_merge_extract_to_physical_vgpr:
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; CHECK: ; %bb.0:
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; CHECK-NEXT: v_mov_b32_e32 v0, 0
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; CHECK-NEXT: global_load_dwordx2 v[0:1], v0, s[0:1] glc dlc
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; CHECK-NEXT: s_waitcnt vmcnt(0)
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; CHECK-NEXT: v_readfirstlane_b32 s0, v1
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; CHECK-NEXT: v_mov_b32_e32 v0, s0
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; CHECK-NEXT: ; return to shader part epilog
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%load = load volatile <2 x float>, ptr addrspace(1) %ptr0
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%extracted = extractelement <2 x float> %load, i32 1
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ret float %extracted
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}
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define amdgpu_ps void @unmerge_readanylane_merge_extract_bitcast_to_virtual_vgpr(ptr addrspace(1) inreg %ptr0, ptr addrspace(1) inreg %ptr1) {
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; CHECK-LABEL: unmerge_readanylane_merge_extract_bitcast_to_virtual_vgpr:
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; CHECK: ; %bb.0:
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; CHECK-NEXT: v_mov_b32_e32 v2, 0
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; CHECK-NEXT: global_load_dwordx2 v[0:1], v2, s[0:1] glc dlc
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; CHECK-NEXT: s_waitcnt vmcnt(0)
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; CHECK-NEXT: v_readfirstlane_b32 s0, v0
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; CHECK-NEXT: v_mov_b32_e32 v0, s0
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; CHECK-NEXT: global_store_dword v2, v0, s[2:3]
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; CHECK-NEXT: s_endpgm
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%load = load volatile <4 x i16>, ptr addrspace(1) %ptr0
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%extracted = shufflevector <4 x i16> %load, <4 x i16> %load, <2 x i32> <i32 0, i32 1>
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%bitcast = bitcast <2 x i16> %extracted to float
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store float %bitcast, ptr addrspace(1) %ptr1
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ret void
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}
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define amdgpu_ps float @unmerge_readanylane_merge_extract_bitcast_to_physical_vgpr(ptr addrspace(1) inreg %ptr0, ptr addrspace(1) inreg %ptr1) {
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; CHECK-LABEL: unmerge_readanylane_merge_extract_bitcast_to_physical_vgpr:
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; CHECK: ; %bb.0:
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; CHECK-NEXT: v_mov_b32_e32 v0, 0
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; CHECK-NEXT: global_load_dwordx2 v[0:1], v0, s[0:1] glc dlc
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; CHECK-NEXT: s_waitcnt vmcnt(0)
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; CHECK-NEXT: v_readfirstlane_b32 s0, v0
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; CHECK-NEXT: v_mov_b32_e32 v0, s0
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; CHECK-NEXT: ; return to shader part epilog
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%load = load volatile <4 x i16>, ptr addrspace(1) %ptr0
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%extracted = shufflevector <4 x i16> %load, <4 x i16> %load, <2 x i32> <i32 0, i32 1>
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%bitcast = bitcast <2 x i16> %extracted to float
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ret float %bitcast
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}

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