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[PowerPC] option -msoft-float should not block the PC-relative address instruction (#92543)
The Prefix instruction is introduced on PowerPC ISA3_1. In the PR, 1. The `FeaturePrefixInstrs` do not imply the `FeatureP8Vector` ,`FeatureP9Vector` . 2. `FeaturePrefixInstrs` implies only the FeatureISA3_1. 3. For the prefix instructions `paddi` and `pli` , they have `Predicates = [PrefixInstrs] ` 4. For the prefix instructions `plfs` and `plfd`, they have `Predicates = [PrefixInstrs, HasFPU] ` 5. For the prefix instructions "plxv` , "plxssp` and `plxsd` , they have `Predicates = [PrefixInstrs, HasP10Vector]` Fixes #62372
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5 files changed

+104
-62
lines changed

‎llvm/lib/Target/PowerPC/PPC.td

Lines changed: 1 addition & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -296,8 +296,7 @@ def FeatureVectorsUseTwoUnits : SubtargetFeature<"vectors-use-two-units",
296296
def FeaturePrefixInstrs : SubtargetFeature<"prefix-instrs", "HasPrefixInstrs",
297297
"true",
298298
"Enable prefixed instructions",
299-
[FeatureISA3_0, FeatureP8Vector,
300-
FeatureP9Altivec]>;
299+
[FeatureISA3_1]>;
301300
def FeaturePCRelativeMemops :
302301
SubtargetFeature<"pcrelative-memops", "HasPCRelativeMemops", "true",
303302
"Enable PC relative Memory Ops",

‎llvm/lib/Target/PowerPC/PPCISelLowering.cpp

Lines changed: 10 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -9460,7 +9460,7 @@ SDValue PPCTargetLowering::LowerBUILD_VECTOR(SDValue Op,
94609460
// double. This is to exploit the XXSPLTIDP instruction.
94619461
// If we lose precision, we use XXSPLTI32DX.
94629462
if (BVNIsConstantSplat && (SplatBitSize == 64) &&
9463-
Subtarget.hasPrefixInstrs()) {
9463+
Subtarget.hasPrefixInstrs() && Subtarget.hasP10Vector()) {
94649464
// Check the type first to short-circuit so we don't modify APSplatBits if
94659465
// this block isn't executed.
94669466
if ((Op->getValueType(0) == MVT::v2f64) &&
@@ -9605,11 +9605,11 @@ SDValue PPCTargetLowering::LowerBUILD_VECTOR(SDValue Op,
96059605
// with 4-byte splats. We replicate the SplatBits in case of 2-byte splat to
96069606
// make a 4-byte splat element. For example: 2-byte splat of 0xABAB can be
96079607
// turned into a 4-byte splat of 0xABABABAB.
9608-
if (Subtarget.hasPrefixInstrs() && SplatSize == 2)
9608+
if (Subtarget.hasPrefixInstrs() && Subtarget.hasP10Vector() && SplatSize == 2)
96099609
return getCanonicalConstSplat(SplatBits | (SplatBits << 16), SplatSize * 2,
96109610
Op.getValueType(), DAG, dl);
96119611

9612-
if (Subtarget.hasPrefixInstrs() && SplatSize == 4)
9612+
if (Subtarget.hasPrefixInstrs() && Subtarget.hasP10Vector() && SplatSize == 4)
96139613
return getCanonicalConstSplat(SplatBits, SplatSize, Op.getValueType(), DAG,
96149614
dl);
96159615

@@ -10242,7 +10242,7 @@ SDValue PPCTargetLowering::LowerVECTOR_SHUFFLE(SDValue Op,
1024210242
return DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, Ins);
1024310243
}
1024410244

10245-
if (Subtarget.hasPrefixInstrs()) {
10245+
if (Subtarget.hasPrefixInstrs() && Subtarget.hasP10Vector()) {
1024610246
SDValue SplatInsertNode;
1024710247
if ((SplatInsertNode = lowerToXXSPLTI32DX(SVOp, DAG)))
1024810248
return SplatInsertNode;
@@ -17730,7 +17730,7 @@ bool PPCTargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT,
1773017730
return false;
1773117731
case MVT::f32:
1773217732
case MVT::f64: {
17733-
if (Subtarget.hasPrefixInstrs()) {
17733+
if (Subtarget.hasPrefixInstrs() && Subtarget.hasP10Vector()) {
1773417734
// we can materialize all immediatess via XXSPLTI32DX and XXSPLTIDP.
1773517735
return true;
1773617736
}
@@ -18314,11 +18314,12 @@ unsigned PPCTargetLowering::computeMOFlags(const SDNode *Parent, SDValue N,
1831418314
// Compute subtarget flags.
1831518315
if (!Subtarget.hasP9Vector())
1831618316
FlagSet |= PPC::MOF_SubtargetBeforeP9;
18317-
else {
18317+
else
1831818318
FlagSet |= PPC::MOF_SubtargetP9;
18319-
if (Subtarget.hasPrefixInstrs())
18320-
FlagSet |= PPC::MOF_SubtargetP10;
18321-
}
18319+
18320+
if (Subtarget.hasPrefixInstrs())
18321+
FlagSet |= PPC::MOF_SubtargetP10;
18322+
1832218323
if (Subtarget.hasSPE())
1832318324
FlagSet |= PPC::MOF_SubtargetSPE;
1832418325

‎llvm/lib/Target/PowerPC/PPCInstrP10.td

Lines changed: 79 additions & 50 deletions
Original file line numberDiff line numberDiff line change
@@ -654,13 +654,10 @@ let Predicates = [PrefixInstrs] in {
654654
(ins s34imm:$SI),
655655
"pli $RT, $SI", IIC_IntSimple, []>;
656656
}
657+
}
657658

659+
let Predicates = [PrefixInstrs, HasFPU] in {
658660
let mayLoad = 1, mayStore = 0 in {
659-
defm PLXV :
660-
8LS_DForm_R_SI34_XT6_RA5_MEM_p<25, (outs vsrc:$XST), (ins (memri34 $D, $RA):$addr),
661-
(ins (memri34_pcrel $D, $RA):$addr),
662-
(ins s34imm_pcrel:$D),
663-
"plxv $XST, $addr", "plxv $XST, $D", IIC_LdStLFD>;
664661
defm PLFS :
665662
MLS_DForm_R_SI34_RTA5_MEM_p<48, (outs f4rc:$RST), (ins (memri34 $D, $RA):$addr),
666663
(ins (memri34_pcrel $D, $RA):$addr),
@@ -671,6 +668,28 @@ let Predicates = [PrefixInstrs] in {
671668
(ins (memri34_pcrel $D, $RA):$addr),
672669
(ins s34imm_pcrel:$D), "plfd $RST, $addr",
673670
"plfd $RST, $D", IIC_LdStLFD>;
671+
}
672+
let mayStore = 1, mayLoad = 0 in {
673+
defm PSTFS :
674+
MLS_DForm_R_SI34_RTA5_MEM_p<52, (outs), (ins f4rc:$RST, (memri34 $D, $RA):$addr),
675+
(ins f4rc:$RST, (memri34_pcrel $D, $RA):$addr),
676+
(ins f4rc:$RST, s34imm_pcrel:$D),
677+
"pstfs $RST, $addr", "pstfs $RST, $D", IIC_LdStLFD>;
678+
defm PSTFD :
679+
MLS_DForm_R_SI34_RTA5_MEM_p<54, (outs), (ins f8rc:$RST, (memri34 $D, $RA):$addr),
680+
(ins f8rc:$RST, (memri34_pcrel $D, $RA):$addr),
681+
(ins f8rc:$RST, s34imm_pcrel:$D),
682+
"pstfd $RST, $addr", "pstfd $RST, $D", IIC_LdStLFD>;
683+
}
684+
}
685+
686+
let Predicates = [PrefixInstrs, HasP10Vector] in {
687+
let mayLoad = 1, mayStore = 0 in {
688+
defm PLXV :
689+
8LS_DForm_R_SI34_XT6_RA5_MEM_p<25, (outs vsrc:$XST), (ins (memri34 $D, $RA):$addr),
690+
(ins (memri34_pcrel $D, $RA):$addr),
691+
(ins s34imm_pcrel:$D),
692+
"plxv $XST, $addr", "plxv $XST, $D", IIC_LdStLFD>;
674693
defm PLXSSP :
675694
8LS_DForm_R_SI34_RTA5_MEM_p<43, (outs vfrc:$RST), (ins (memri34 $D, $RA):$addr),
676695
(ins (memri34_pcrel $D, $RA):$addr),
@@ -683,6 +702,28 @@ let Predicates = [PrefixInstrs] in {
683702
(ins s34imm_pcrel:$D),
684703
"plxsd $RST, $addr", "plxsd $RST, $D",
685704
IIC_LdStLFD>;
705+
}
706+
let mayStore = 1, mayLoad = 0 in {
707+
defm PSTXV :
708+
8LS_DForm_R_SI34_XT6_RA5_MEM_p<27, (outs), (ins vsrc:$XST, (memri34 $D, $RA):$addr),
709+
(ins vsrc:$XST, (memri34_pcrel $D, $RA):$addr),
710+
(ins vsrc:$XST, s34imm_pcrel:$D),
711+
"pstxv $XST, $addr", "pstxv $XST, $D", IIC_LdStLFD>;
712+
defm PSTXSSP :
713+
8LS_DForm_R_SI34_RTA5_MEM_p<47, (outs), (ins vfrc:$RST, (memri34 $D, $RA):$addr),
714+
(ins vfrc:$RST, (memri34_pcrel $D, $RA):$addr),
715+
(ins vfrc:$RST, s34imm_pcrel:$D),
716+
"pstxssp $RST, $addr", "pstxssp $RST, $D", IIC_LdStLFD>;
717+
defm PSTXSD :
718+
8LS_DForm_R_SI34_RTA5_MEM_p<46, (outs), (ins vfrc:$RST, (memri34 $D, $RA):$addr),
719+
(ins vfrc:$RST, (memri34_pcrel $D, $RA):$addr),
720+
(ins vfrc:$RST, s34imm_pcrel:$D),
721+
"pstxsd $RST, $addr", "pstxsd $RST, $D", IIC_LdStLFD>;
722+
}
723+
}
724+
725+
let Predicates = [PrefixInstrs] in {
726+
let mayLoad = 1, mayStore = 0 in {
686727
let Interpretation64Bit = 1, isCodeGenOnly = 1 in {
687728
defm PLBZ8 :
688729
MLS_DForm_R_SI34_RTA5_MEM_p<34, (outs g8rc:$RST), (ins (memri34 $D, $RA):$addr),
@@ -745,31 +786,6 @@ let Predicates = [PrefixInstrs] in {
745786
}
746787

747788
let mayStore = 1, mayLoad = 0 in {
748-
defm PSTXV :
749-
8LS_DForm_R_SI34_XT6_RA5_MEM_p<27, (outs), (ins vsrc:$XST, (memri34 $D, $RA):$addr),
750-
(ins vsrc:$XST, (memri34_pcrel $D, $RA):$addr),
751-
(ins vsrc:$XST, s34imm_pcrel:$D),
752-
"pstxv $XST, $addr", "pstxv $XST, $D", IIC_LdStLFD>;
753-
defm PSTFS :
754-
MLS_DForm_R_SI34_RTA5_MEM_p<52, (outs), (ins f4rc:$RST, (memri34 $D, $RA):$addr),
755-
(ins f4rc:$RST, (memri34_pcrel $D, $RA):$addr),
756-
(ins f4rc:$RST, s34imm_pcrel:$D),
757-
"pstfs $RST, $addr", "pstfs $RST, $D", IIC_LdStLFD>;
758-
defm PSTFD :
759-
MLS_DForm_R_SI34_RTA5_MEM_p<54, (outs), (ins f8rc:$RST, (memri34 $D, $RA):$addr),
760-
(ins f8rc:$RST, (memri34_pcrel $D, $RA):$addr),
761-
(ins f8rc:$RST, s34imm_pcrel:$D),
762-
"pstfd $RST, $addr", "pstfd $RST, $D", IIC_LdStLFD>;
763-
defm PSTXSSP :
764-
8LS_DForm_R_SI34_RTA5_MEM_p<47, (outs), (ins vfrc:$RST, (memri34 $D, $RA):$addr),
765-
(ins vfrc:$RST, (memri34_pcrel $D, $RA):$addr),
766-
(ins vfrc:$RST, s34imm_pcrel:$D),
767-
"pstxssp $RST, $addr", "pstxssp $RST, $D", IIC_LdStLFD>;
768-
defm PSTXSD :
769-
8LS_DForm_R_SI34_RTA5_MEM_p<46, (outs), (ins vfrc:$RST, (memri34 $D, $RA):$addr),
770-
(ins vfrc:$RST, (memri34_pcrel $D, $RA):$addr),
771-
(ins vfrc:$RST, s34imm_pcrel:$D),
772-
"pstxsd $RST, $addr", "pstxsd $RST, $D", IIC_LdStLFD>;
773789
let Interpretation64Bit = 1, isCodeGenOnly = 1 in {
774790
defm PSTB8 :
775791
MLS_DForm_R_SI34_RTA5_MEM_p<38, (outs), (ins g8rc:$RST, (memri34 $D, $RA):$addr),
@@ -1136,7 +1152,7 @@ let mayLoad = 0, mayStore = 1, Predicates = [PairedVectorMemops] in {
11361152
[]>;
11371153
}
11381154

1139-
let mayLoad = 1, mayStore = 0, Predicates = [PairedVectorMemops, PrefixInstrs] in {
1155+
let mayLoad = 1, mayStore = 0, Predicates = [PairedVectorMemops, PrefixInstrs, HasP10Vector] in {
11401156
defm PLXVP :
11411157
8LS_DForm_R_XTp5_SI34_MEM_p<58, (outs vsrprc:$XTp), (ins (memri34 $D, $RA):$addr),
11421158
(ins (memri34_pcrel $D, $RA):$addr),
@@ -1145,7 +1161,7 @@ let mayLoad = 1, mayStore = 0, Predicates = [PairedVectorMemops, PrefixInstrs] i
11451161
IIC_LdStLFD>;
11461162
}
11471163

1148-
let mayLoad = 0, mayStore = 1, Predicates = [PairedVectorMemops, PrefixInstrs] in {
1164+
let mayLoad = 0, mayStore = 1, Predicates = [PairedVectorMemops, PrefixInstrs, HasP10Vector] in {
11491165
defm PSTXVP :
11501166
8LS_DForm_R_XTp5_SI34_MEM_p<62, (outs), (ins vsrprc:$XTp, (memri34 $D, $RA):$addr),
11511167
(ins vsrprc:$XTp, (memri34_pcrel $D, $RA):$addr),
@@ -1157,15 +1173,15 @@ let Predicates = [PairedVectorMemops] in {
11571173
// Intrinsics for Paired Vector Loads.
11581174
def : Pat<(v256i1 (int_ppc_vsx_lxvp DQForm:$src)), (LXVP memrix16:$src)>;
11591175
def : Pat<(v256i1 (int_ppc_vsx_lxvp XForm:$src)), (LXVPX XForm:$src)>;
1160-
let Predicates = [PairedVectorMemops, PrefixInstrs] in {
1176+
let Predicates = [PairedVectorMemops, PrefixInstrs, HasP10Vector] in {
11611177
def : Pat<(v256i1 (int_ppc_vsx_lxvp PDForm:$src)), (PLXVP memri34:$src)>;
11621178
}
11631179
// Intrinsics for Paired Vector Stores.
11641180
def : Pat<(int_ppc_vsx_stxvp v256i1:$XSp, DQForm:$dst),
11651181
(STXVP $XSp, memrix16:$dst)>;
11661182
def : Pat<(int_ppc_vsx_stxvp v256i1:$XSp, XForm:$dst),
11671183
(STXVPX $XSp, XForm:$dst)>;
1168-
let Predicates = [PairedVectorMemops, PrefixInstrs] in {
1184+
let Predicates = [PairedVectorMemops, PrefixInstrs, HasP10Vector] in {
11691185
def : Pat<(int_ppc_vsx_stxvp v256i1:$XSp, PDForm:$dst),
11701186
(PSTXVP $XSp, memri34:$dst)>;
11711187
}
@@ -1236,6 +1252,9 @@ let Predicates = [PCRelativeMemops] in {
12361252
def : Pat<(store i64:$RS, (PPCmatpcreladdr PCRelForm:$ga)),
12371253
(PSTDpc $RS, $ga, 0)>;
12381254

1255+
}
1256+
1257+
let Predicates = [PCRelativeMemops, HasFPU] in {
12391258
// Load f32
12401259
def : Pat<(f32 (load (PPCmatpcreladdr PCRelForm:$addr))), (PLFSpc $addr, 0)>;
12411260

@@ -1252,6 +1271,11 @@ let Predicates = [PCRelativeMemops] in {
12521271
def : Pat<(store f64:$FRS, (PPCmatpcreladdr PCRelForm:$ga)),
12531272
(PSTFDpc $FRS, $ga, 0)>;
12541273

1274+
def : Pat<(v4f32 (PPCldvsxlh (PPCmatpcreladdr PCRelForm:$addr))),
1275+
(SUBREG_TO_REG (i64 1), (PLFDpc $addr, 0), sub_64)>;
1276+
}
1277+
1278+
let Predicates = [PCRelativeMemops, HasP10Vector] in {
12551279
// Load f128
12561280
def : Pat<(f128 (load (PPCmatpcreladdr PCRelForm:$addr))),
12571281
(COPY_TO_REGCLASS (PLXVpc $addr, 0), VRRC)>;
@@ -1288,6 +1312,14 @@ let Predicates = [PCRelativeMemops] in {
12881312
def : Pat<(store v2f64:$XS, (PPCmatpcreladdr PCRelForm:$ga)),
12891313
(PSTXVpc $XS, $ga, 0)>;
12901314

1315+
// Special Cases For PPCstore_scal_int_from_vsr
1316+
def : Pat<(PPCstore_scal_int_from_vsr f64:$src, (PPCmatpcreladdr PCRelForm:$dst), 8),
1317+
(PSTXSDpc $src, $dst, 0)>;
1318+
def : Pat<(PPCstore_scal_int_from_vsr f128:$src, (PPCmatpcreladdr PCRelForm:$dst), 8),
1319+
(PSTXSDpc (COPY_TO_REGCLASS $src, VFRC), $dst, 0)>;
1320+
}
1321+
1322+
let Predicates = [PCRelativeMemops] in {
12911323
// Atomic Load
12921324
def : Pat<(i32 (atomic_load_8 (PPCmatpcreladdr PCRelForm:$ga))),
12931325
(PLBZpc $ga, 0)>;
@@ -1314,15 +1346,6 @@ let Predicates = [PCRelativeMemops] in {
13141346
def : Pat<(atomic_store_64 i64:$RS, (PPCmatpcreladdr PCRelForm:$ga)),
13151347
(PSTDpc $RS, $ga, 0)>;
13161348

1317-
// Special Cases For PPCstore_scal_int_from_vsr
1318-
def : Pat<(PPCstore_scal_int_from_vsr f64:$src, (PPCmatpcreladdr PCRelForm:$dst), 8),
1319-
(PSTXSDpc $src, $dst, 0)>;
1320-
def : Pat<(PPCstore_scal_int_from_vsr f128:$src, (PPCmatpcreladdr PCRelForm:$dst), 8),
1321-
(PSTXSDpc (COPY_TO_REGCLASS $src, VFRC), $dst, 0)>;
1322-
1323-
def : Pat<(v4f32 (PPCldvsxlh (PPCmatpcreladdr PCRelForm:$addr))),
1324-
(SUBREG_TO_REG (i64 1), (PLFDpc $addr, 0), sub_64)>;
1325-
13261349
// If the PPCmatpcreladdr node is not caught by any other pattern it should be
13271350
// caught here and turned into a paddi instruction to materialize the address.
13281351
def : Pat<(PPCmatpcreladdr PCRelForm:$addr), (PADDI8pc 0, $addr)>;
@@ -1335,7 +1358,7 @@ let Predicates = [PCRelativeMemops] in {
13351358
(PADDI8 $in, $addr)>;
13361359
}
13371360

1338-
let Predicates = [PrefixInstrs] in {
1361+
let Predicates = [PrefixInstrs, HasP10Vector] in {
13391362
def XXPERMX :
13401363
8RR_XX4Form_IMM3_XTABC6<34, 0, (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB,
13411364
vsrc:$XC, u3imm:$IMM),
@@ -2142,7 +2165,7 @@ let AddedComplexity = 400, Predicates = [IsISA3_1, HasVSX] in {
21422165
class xxevalPattern <dag pattern, bits<8> imm> :
21432166
Pat<(v4i32 pattern), (XXEVAL $vA, $vB, $vC, imm)> {}
21442167

2145-
let AddedComplexity = 400, Predicates = [PrefixInstrs] in {
2168+
let AddedComplexity = 400, Predicates = [PrefixInstrs, HasP10Vector] in {
21462169
def : Pat<(v4i32 (build_vector i32immNonAllOneNonZero:$A,
21472170
i32immNonAllOneNonZero:$A,
21482171
i32immNonAllOneNonZero:$A,
@@ -2279,7 +2302,7 @@ def : Pat<(f64 nzFPImmAsi64:$A),
22792302
(PSTXSD (COPY_TO_REGCLASS $src, VFRC), PDForm:$dst)>;
22802303
}
22812304

2282-
let Predicates = [PrefixInstrs] in {
2305+
let Predicates = [PrefixInstrs, HasP10Vector] in {
22832306
def : Pat<(i32 imm34:$imm), (PLI (getImmAs64BitInt imm:$imm))>;
22842307
def : Pat<(i64 imm34:$imm), (PLI8 (getImmAs64BitInt imm:$imm))>;
22852308
def : Pat<(v16i8 (int_ppc_vsx_xxpermx v16i8:$A, v16i8:$B, v16i8:$C, timm:$D)),
@@ -2300,7 +2323,9 @@ let Predicates = [PrefixInstrs] in {
23002323
(XXBLENDVW $A, $B, $C)>;
23012324
def : Pat<(int_ppc_vsx_xxblendvd v2i64:$A, v2i64:$B, v2i64:$C),
23022325
(XXBLENDVD $A, $B, $C)>;
2326+
}
23032327

2328+
let Predicates = [PrefixInstrs] in {
23042329
// Anonymous patterns to select prefixed loads and stores.
23052330
// Load i32
23062331
def : Pat<(i32 (extloadi1 PDForm:$src)), (PLBZ memri34:$src)>;
@@ -2335,7 +2360,9 @@ let Predicates = [PrefixInstrs] in {
23352360
def : Pat<(truncstorei16 i64:$rS, PDForm:$dst), (PSTH8 g8rc:$rS, memri34:$dst)>;
23362361
def : Pat<(truncstorei32 i64:$rS, PDForm:$dst), (PSTW8 g8rc:$rS, memri34:$dst)>;
23372362
def : Pat<(store i64:$rS, PDForm:$dst), (PSTD g8rc:$rS, memri34:$dst)>;
2363+
}
23382364

2365+
let Predicates = [PrefixInstrs, HasFPU] in {
23392366
// Load / Store f32
23402367
def : Pat<(f32 (load PDForm:$src)), (PLFS memri34:$src)>;
23412368
def : Pat<(store f32:$FRS, PDForm:$dst), (PSTFS $FRS, memri34:$dst)>;
@@ -2345,7 +2372,13 @@ let Predicates = [PrefixInstrs] in {
23452372
(COPY_TO_REGCLASS (PLFS memri34:$src), VSFRC)>;
23462373
def : Pat<(f64 (load PDForm:$src)), (PLFD memri34:$src)>;
23472374
def : Pat<(store f64:$FRS, PDForm:$dst), (PSTFD $FRS, memri34:$dst)>;
2375+
// Prefixed fpext to v2f64
2376+
def : Pat<(v4f32 (PPCldvsxlh PDForm:$src)),
2377+
(SUBREG_TO_REG (i64 1), (PLFD PDForm:$src), sub_64)>;
23482378

2379+
}
2380+
2381+
let Predicates = [PrefixInstrs] in {
23492382
// Atomic Load
23502383
def : Pat<(i32 (atomic_load_8 PDForm:$src)), (PLBZ memri34:$src)>;
23512384
def : Pat<(i32 (atomic_load_16 PDForm:$src)), (PLHZ memri34:$src)>;
@@ -2357,10 +2390,6 @@ let Predicates = [PrefixInstrs] in {
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def : Pat<(atomic_store_16 i32:$RS, PDForm:$dst), (PSTH $RS, memri34:$dst)>;
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def : Pat<(atomic_store_32 i32:$RS, PDForm:$dst), (PSTW $RS, memri34:$dst)>;
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def : Pat<(atomic_store_64 i64:$RS, PDForm:$dst), (PSTD $RS, memri34:$dst)>;
2360-
2361-
// Prefixed fpext to v2f64
2362-
def : Pat<(v4f32 (PPCldvsxlh PDForm:$src)),
2363-
(SUBREG_TO_REG (i64 1), (PLFD PDForm:$src), sub_64)>;
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}
23652394

23662395
def InsertEltShift {

‎llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1695,7 +1695,7 @@ PPCRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
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// transform it to the prefixed version so we don't have to use the XForm.
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if ((OpC == PPC::LXVP || OpC == PPC::STXVP) &&
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(!isInt<16>(Offset) || (Offset % offsetMinAlign(MI)) != 0) &&
1698-
Subtarget.hasPrefixInstrs()) {
1698+
Subtarget.hasPrefixInstrs() && Subtarget.hasP10Vector()) {
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unsigned NewOpc = OpC == PPC::LXVP ? PPC::PLXVP : PPC::PSTXVP;
17001700
MI.setDesc(TII.get(NewOpc));
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OpC = NewOpc;

‎llvm/test/CodeGen/PowerPC/pr62372.ll

Lines changed: 13 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,13 @@
1+
; RUN: llc -ppc-asm-full-reg-names -mcpu=pwr10 -mtriple powerpc64le-unknown-linux-gnu \
2+
; RUN: -o - %s | FileCheck %s
3+
4+
@bar = dso_local global i32 0, align 4
5+
6+
define dso_local ptr @foo() #0 {
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entry:
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ret ptr @bar
9+
}
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attributes #0 = { "use-soft-float"="true" }
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13+
; CHECK: paddi r3, 0, bar@PCREL, 1

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