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[X86] cmp-shiftX-maskX.ll - add AVX1 test coverage
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‎llvm/test/CodeGen/X86/cmp-shiftX-maskX.ll

Lines changed: 54 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -1,7 +1,8 @@
11
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 3
22
; RUN: llc < %s -mtriple=x86_64-unknown-unknown | FileCheck %s --check-prefixes=CHECK,CHECK-NOBMI,CHECK-NOBMI-SSE2
33
; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+bmi2 | FileCheck %s --check-prefixes=CHECK,CHECK-BMI2,CHECK-BMI2-SSE2
4-
; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+bmi2,+avx2 | FileCheck %s --check-prefixes=CHECK,CHECK-BMI2,CHECK-AVX,CHECK-AVX2
4+
; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+bmi2,+avx | FileCheck %s --check-prefixes=CHECK,CHECK-BMI2,CHECK-AVX,CHECK-AVX12,CHECK-AVX1
5+
; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+bmi2,+avx2 | FileCheck %s --check-prefixes=CHECK,CHECK-BMI2,CHECK-AVX,CHECK-AVX12,CHECK-AVX2
56
; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+bmi2,+avx512f,+avx512vl | FileCheck %s --check-prefixes=CHECK,CHECK-BMI2,CHECK-AVX,CHECK-AVX512
67
declare <4 x i32> @llvm.fshl.v4i32(<4 x i32>, <4 x i32>, <4 x i32>)
78
declare <4 x i32> @llvm.fshr.v4i32(<4 x i32>, <4 x i32>, <4 x i32>)
@@ -353,6 +354,15 @@ define <4 x i1> @shr_to_ror_eq_4xi32_s4(<4 x i32> %x) {
353354
; CHECK-BMI2-SSE2-NEXT: pxor %xmm1, %xmm0
354355
; CHECK-BMI2-SSE2-NEXT: retq
355356
;
357+
; CHECK-AVX1-LABEL: shr_to_ror_eq_4xi32_s4:
358+
; CHECK-AVX1: # %bb.0:
359+
; CHECK-AVX1-NEXT: vpsrld $4, %xmm0, %xmm1
360+
; CHECK-AVX1-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
361+
; CHECK-AVX1-NEXT: vpcmpeqd %xmm0, %xmm1, %xmm0
362+
; CHECK-AVX1-NEXT: vpcmpeqd %xmm1, %xmm1, %xmm1
363+
; CHECK-AVX1-NEXT: vpxor %xmm1, %xmm0, %xmm0
364+
; CHECK-AVX1-NEXT: retq
365+
;
356366
; CHECK-AVX2-LABEL: shr_to_ror_eq_4xi32_s4:
357367
; CHECK-AVX2: # %bb.0:
358368
; CHECK-AVX2-NEXT: vpsrld $4, %xmm0, %xmm1
@@ -396,14 +406,14 @@ define <4 x i1> @shl_to_ror_eq_4xi32_s8(<4 x i32> %x) {
396406
; CHECK-BMI2-SSE2-NEXT: pxor %xmm1, %xmm0
397407
; CHECK-BMI2-SSE2-NEXT: retq
398408
;
399-
; CHECK-AVX2-LABEL: shl_to_ror_eq_4xi32_s8:
400-
; CHECK-AVX2: # %bb.0:
401-
; CHECK-AVX2-NEXT: vpslld $8, %xmm0, %xmm1
402-
; CHECK-AVX2-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
403-
; CHECK-AVX2-NEXT: vpcmpeqd %xmm0, %xmm1, %xmm0
404-
; CHECK-AVX2-NEXT: vpcmpeqd %xmm1, %xmm1, %xmm1
405-
; CHECK-AVX2-NEXT: vpxor %xmm1, %xmm0, %xmm0
406-
; CHECK-AVX2-NEXT: retq
409+
; CHECK-AVX12-LABEL: shl_to_ror_eq_4xi32_s8:
410+
; CHECK-AVX12: # %bb.0:
411+
; CHECK-AVX12-NEXT: vpslld $8, %xmm0, %xmm1
412+
; CHECK-AVX12-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
413+
; CHECK-AVX12-NEXT: vpcmpeqd %xmm0, %xmm1, %xmm0
414+
; CHECK-AVX12-NEXT: vpcmpeqd %xmm1, %xmm1, %xmm1
415+
; CHECK-AVX12-NEXT: vpxor %xmm1, %xmm0, %xmm0
416+
; CHECK-AVX12-NEXT: retq
407417
;
408418
; CHECK-AVX512-LABEL: shl_to_ror_eq_4xi32_s8:
409419
; CHECK-AVX512: # %bb.0:
@@ -438,6 +448,15 @@ define <4 x i1> @shl_to_ror_eq_4xi32_s7_fail_no_p2(<4 x i32> %x) {
438448
; CHECK-BMI2-SSE2-NEXT: pxor %xmm1, %xmm0
439449
; CHECK-BMI2-SSE2-NEXT: retq
440450
;
451+
; CHECK-AVX1-LABEL: shl_to_ror_eq_4xi32_s7_fail_no_p2:
452+
; CHECK-AVX1: # %bb.0:
453+
; CHECK-AVX1-NEXT: vpslld $7, %xmm0, %xmm1
454+
; CHECK-AVX1-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
455+
; CHECK-AVX1-NEXT: vpcmpeqd %xmm0, %xmm1, %xmm0
456+
; CHECK-AVX1-NEXT: vpcmpeqd %xmm1, %xmm1, %xmm1
457+
; CHECK-AVX1-NEXT: vpxor %xmm1, %xmm0, %xmm0
458+
; CHECK-AVX1-NEXT: retq
459+
;
441460
; CHECK-AVX2-LABEL: shl_to_ror_eq_4xi32_s7_fail_no_p2:
442461
; CHECK-AVX2: # %bb.0:
443462
; CHECK-AVX2-NEXT: vpslld $7, %xmm0, %xmm1
@@ -490,6 +509,17 @@ define <4 x i1> @shr_to_ror_eq_4xi32_s4_fail_no_splat(<4 x i32> %x) {
490509
; CHECK-BMI2-SSE2-NEXT: pxor %xmm1, %xmm0
491510
; CHECK-BMI2-SSE2-NEXT: retq
492511
;
512+
; CHECK-AVX1-LABEL: shr_to_ror_eq_4xi32_s4_fail_no_splat:
513+
; CHECK-AVX1: # %bb.0:
514+
; CHECK-AVX1-NEXT: vpsrld $8, %xmm0, %xmm1
515+
; CHECK-AVX1-NEXT: vpsrld $4, %xmm0, %xmm2
516+
; CHECK-AVX1-NEXT: vpblendw {{.*#+}} xmm1 = xmm2[0,1,2,3,4,5],xmm1[6,7]
517+
; CHECK-AVX1-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
518+
; CHECK-AVX1-NEXT: vpcmpeqd %xmm0, %xmm1, %xmm0
519+
; CHECK-AVX1-NEXT: vpcmpeqd %xmm1, %xmm1, %xmm1
520+
; CHECK-AVX1-NEXT: vpxor %xmm1, %xmm0, %xmm0
521+
; CHECK-AVX1-NEXT: retq
522+
;
493523
; CHECK-AVX2-LABEL: shr_to_ror_eq_4xi32_s4_fail_no_splat:
494524
; CHECK-AVX2: # %bb.0:
495525
; CHECK-AVX2-NEXT: vpsrlvd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1
@@ -546,6 +576,21 @@ define <16 x i1> @shl_to_ror_eq_16xi16_s8_fail_preserve_i16(<16 x i16> %x) {
546576
; CHECK-BMI2-SSE2-NEXT: pxor %xmm1, %xmm0
547577
; CHECK-BMI2-SSE2-NEXT: retq
548578
;
579+
; CHECK-AVX1-LABEL: shl_to_ror_eq_16xi16_s8_fail_preserve_i16:
580+
; CHECK-AVX1: # %bb.0:
581+
; CHECK-AVX1-NEXT: vpsllw $8, %xmm0, %xmm1
582+
; CHECK-AVX1-NEXT: vextractf128 $1, %ymm0, %xmm2
583+
; CHECK-AVX1-NEXT: vpsllw $8, %xmm2, %xmm2
584+
; CHECK-AVX1-NEXT: vandps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
585+
; CHECK-AVX1-NEXT: vextractf128 $1, %ymm0, %xmm3
586+
; CHECK-AVX1-NEXT: vpcmpeqw %xmm3, %xmm2, %xmm2
587+
; CHECK-AVX1-NEXT: vpcmpeqw %xmm0, %xmm1, %xmm0
588+
; CHECK-AVX1-NEXT: vpacksswb %xmm2, %xmm0, %xmm0
589+
; CHECK-AVX1-NEXT: vpcmpeqd %xmm1, %xmm1, %xmm1
590+
; CHECK-AVX1-NEXT: vpxor %xmm1, %xmm0, %xmm0
591+
; CHECK-AVX1-NEXT: vzeroupper
592+
; CHECK-AVX1-NEXT: retq
593+
;
549594
; CHECK-AVX2-LABEL: shl_to_ror_eq_16xi16_s8_fail_preserve_i16:
550595
; CHECK-AVX2: # %bb.0:
551596
; CHECK-AVX2-NEXT: vpsllw $8, %ymm0, %ymm1

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