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[ValueTracking] Infer knownbits from fp classes
1 parent 3516f12 commit 5462c2c

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6 files changed

+64
-57
lines changed

6 files changed

+64
-57
lines changed

‎llvm/include/llvm/Analysis/ValueTracking.h

Lines changed: 5 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -263,6 +263,11 @@ struct KnownFPClass {
263263
return (KnownFPClasses & Mask) == fcNone;
264264
}
265265

266+
/// Return true if it's known this can only be one of the mask entries.
267+
bool isKnownOnly(FPClassTest Mask) const {
268+
return (KnownFPClasses & ~Mask) == fcNone;
269+
}
270+
266271
bool isUnknown() const {
267272
return KnownFPClasses == fcAllFlags && !SignBit;
268273
}

‎llvm/lib/Analysis/ValueTracking.cpp

Lines changed: 31 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1105,6 +1105,37 @@ static void computeKnownBitsFromOperator(const Operator *I,
11051105
break;
11061106
}
11071107

1108+
Value *V;
1109+
// Handle bitcast from floating point to integer.
1110+
if (match(const_cast<Operator *>(I), m_ElementWiseBitCast(m_Value(V))) &&
1111+
V->getType()->isFPOrFPVectorTy()) {
1112+
KnownFPClass Result = computeKnownFPClass(V, fcAllFlags, Depth + 1, Q);
1113+
if (Result.SignBit) {
1114+
if (*Result.SignBit)
1115+
Known.makeNegative();
1116+
else
1117+
Known.makeNonNegative();
1118+
}
1119+
1120+
Type *FPType = V->getType()->getScalarType();
1121+
int MantissaWidth = FPType->getFPMantissaWidth();
1122+
if (MantissaWidth != -1) {
1123+
if (Result.isKnownOnly(fcInf)) {
1124+
Known.Zero.setLowBits(MantissaWidth);
1125+
Known.One.setBits(MantissaWidth, BitWidth - 1);
1126+
} else if (Result.isKnownOnly(fcZero))
1127+
Known.Zero.setLowBits(BitWidth - 1);
1128+
else if (Result.isKnownOnly(fcInf | fcNan))
1129+
Known.One.setBits(MantissaWidth, BitWidth - 1);
1130+
else if (Result.isKnownOnly(fcSubnormal | fcZero))
1131+
Known.Zero.setBits(MantissaWidth, BitWidth - 1);
1132+
else if (Result.isKnownOnly(fcInf | fcZero))
1133+
Known.Zero.setLowBits(MantissaWidth);
1134+
}
1135+
1136+
break;
1137+
}
1138+
11081139
// Handle cast from vector integer type to scalar or vector integer.
11091140
auto *SrcVecTy = dyn_cast<FixedVectorType>(SrcTy);
11101141
if (!SrcVecTy || !SrcVecTy->getElementType()->isIntegerTy() ||

‎llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-pow.ll

Lines changed: 7 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -2216,7 +2216,7 @@ define float @test_pow_afn_nnan_ninf_f32_known_integral_sitofp(float %x, i32 %y)
22162216
; CHECK-NEXT: [[TMP2:%.*]] = bitcast float [[X]] to i32
22172217
; CHECK-NEXT: [[__POW_SIGN:%.*]] = and i32 [[__YEVEN]], [[TMP2]]
22182218
; CHECK-NEXT: [[TMP3:%.*]] = bitcast float [[__EXP2]] to i32
2219-
; CHECK-NEXT: [[TMP4:%.*]] = or i32 [[__POW_SIGN]], [[TMP3]]
2219+
; CHECK-NEXT: [[TMP4:%.*]] = or disjoint i32 [[__POW_SIGN]], [[TMP3]]
22202220
; CHECK-NEXT: [[TMP5:%.*]] = bitcast i32 [[TMP4]] to float
22212221
; CHECK-NEXT: ret float [[TMP5]]
22222222
;
@@ -2304,7 +2304,7 @@ define float @test_pow_afn_nnan_ninf_f32_known_integral_uitofp(float %x, i32 %y)
23042304
; CHECK-NEXT: [[TMP2:%.*]] = bitcast float [[X]] to i32
23052305
; CHECK-NEXT: [[__POW_SIGN:%.*]] = and i32 [[__YEVEN]], [[TMP2]]
23062306
; CHECK-NEXT: [[TMP3:%.*]] = bitcast float [[__EXP2]] to i32
2307-
; CHECK-NEXT: [[TMP4:%.*]] = or i32 [[__POW_SIGN]], [[TMP3]]
2307+
; CHECK-NEXT: [[TMP4:%.*]] = or disjoint i32 [[__POW_SIGN]], [[TMP3]]
23082308
; CHECK-NEXT: [[TMP5:%.*]] = bitcast i32 [[TMP4]] to float
23092309
; CHECK-NEXT: ret float [[TMP5]]
23102310
;
@@ -2353,7 +2353,7 @@ define float @test_pow_afn_nnan_ninf_f32_known_integral_uitofp_i256(float %x, i2
23532353
; CHECK-NEXT: [[TMP2:%.*]] = bitcast float [[X]] to i32
23542354
; CHECK-NEXT: [[__POW_SIGN:%.*]] = and i32 [[__YEVEN]], [[TMP2]]
23552355
; CHECK-NEXT: [[TMP3:%.*]] = bitcast float [[__EXP2]] to i32
2356-
; CHECK-NEXT: [[TMP4:%.*]] = or i32 [[__POW_SIGN]], [[TMP3]]
2356+
; CHECK-NEXT: [[TMP4:%.*]] = or disjoint i32 [[__POW_SIGN]], [[TMP3]]
23572357
; CHECK-NEXT: [[TMP5:%.*]] = bitcast i32 [[TMP4]] to float
23582358
; CHECK-NEXT: ret float [[TMP5]]
23592359
;
@@ -2376,7 +2376,7 @@ define float @test_pow_afn_nnan_ninf_f32_known_integral_sitofp_i256(float %x, i2
23762376
; CHECK-NEXT: [[TMP2:%.*]] = bitcast float [[X]] to i32
23772377
; CHECK-NEXT: [[__POW_SIGN:%.*]] = and i32 [[__YEVEN]], [[TMP2]]
23782378
; CHECK-NEXT: [[TMP3:%.*]] = bitcast float [[__EXP2]] to i32
2379-
; CHECK-NEXT: [[TMP4:%.*]] = or i32 [[__POW_SIGN]], [[TMP3]]
2379+
; CHECK-NEXT: [[TMP4:%.*]] = or disjoint i32 [[__POW_SIGN]], [[TMP3]]
23802380
; CHECK-NEXT: [[TMP5:%.*]] = bitcast i32 [[TMP4]] to float
23812381
; CHECK-NEXT: ret float [[TMP5]]
23822382
;
@@ -2399,7 +2399,7 @@ define <2 x float> @test_pow_afn_nnan_ninf_v2f32_known_integral_sitofp(<2 x floa
23992399
; CHECK-NEXT: [[TMP2:%.*]] = bitcast <2 x float> [[X]] to <2 x i32>
24002400
; CHECK-NEXT: [[__POW_SIGN:%.*]] = and <2 x i32> [[__YEVEN]], [[TMP2]]
24012401
; CHECK-NEXT: [[TMP3:%.*]] = bitcast <2 x float> [[__EXP2]] to <2 x i32>
2402-
; CHECK-NEXT: [[TMP4:%.*]] = or <2 x i32> [[__POW_SIGN]], [[TMP3]]
2402+
; CHECK-NEXT: [[TMP4:%.*]] = or disjoint <2 x i32> [[__POW_SIGN]], [[TMP3]]
24032403
; CHECK-NEXT: [[TMP5:%.*]] = bitcast <2 x i32> [[TMP4]] to <2 x float>
24042404
; CHECK-NEXT: ret <2 x float> [[TMP5]]
24052405
;
@@ -2448,7 +2448,7 @@ define <2 x float> @test_pow_afn_nnan_ninf_v2f32_known_integral_uitofp(<2 x floa
24482448
; CHECK-NEXT: [[TMP2:%.*]] = bitcast <2 x float> [[X]] to <2 x i32>
24492449
; CHECK-NEXT: [[__POW_SIGN:%.*]] = and <2 x i32> [[__YEVEN]], [[TMP2]]
24502450
; CHECK-NEXT: [[TMP3:%.*]] = bitcast <2 x float> [[__EXP2]] to <2 x i32>
2451-
; CHECK-NEXT: [[TMP4:%.*]] = or <2 x i32> [[__POW_SIGN]], [[TMP3]]
2451+
; CHECK-NEXT: [[TMP4:%.*]] = or disjoint <2 x i32> [[__POW_SIGN]], [[TMP3]]
24522452
; CHECK-NEXT: [[TMP5:%.*]] = bitcast <2 x i32> [[TMP4]] to <2 x float>
24532453
; CHECK-NEXT: ret <2 x float> [[TMP5]]
24542454
;
@@ -2560,7 +2560,7 @@ define float @test_pow_afn_f32_nnan_ninf__y_known_integral_trunc(float %x, float
25602560
; CHECK-NEXT: [[TMP2:%.*]] = bitcast float [[X]] to i32
25612561
; CHECK-NEXT: [[__POW_SIGN:%.*]] = and i32 [[__YEVEN]], [[TMP2]]
25622562
; CHECK-NEXT: [[TMP3:%.*]] = bitcast float [[__EXP2]] to i32
2563-
; CHECK-NEXT: [[TMP4:%.*]] = or i32 [[__POW_SIGN]], [[TMP3]]
2563+
; CHECK-NEXT: [[TMP4:%.*]] = or disjoint i32 [[__POW_SIGN]], [[TMP3]]
25642564
; CHECK-NEXT: [[TMP5:%.*]] = bitcast i32 [[TMP4]] to float
25652565
; CHECK-NEXT: ret float [[TMP5]]
25662566
;

‎llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-pown.ll

Lines changed: 6 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -680,7 +680,7 @@ define float @test_pown_afn_nnan_ninf_f32(float %x, i32 %y) {
680680
; CHECK-NEXT: [[TMP0:%.*]] = bitcast float [[X]] to i32
681681
; CHECK-NEXT: [[__POW_SIGN:%.*]] = and i32 [[__YEVEN]], [[TMP0]]
682682
; CHECK-NEXT: [[TMP1:%.*]] = bitcast float [[__EXP2]] to i32
683-
; CHECK-NEXT: [[TMP2:%.*]] = or i32 [[__POW_SIGN]], [[TMP1]]
683+
; CHECK-NEXT: [[TMP2:%.*]] = or disjoint i32 [[__POW_SIGN]], [[TMP1]]
684684
; CHECK-NEXT: [[TMP3:%.*]] = bitcast i32 [[TMP2]] to float
685685
; CHECK-NEXT: ret float [[TMP3]]
686686
;
@@ -703,7 +703,7 @@ define <2 x float> @test_pown_afn_nnan_ninf_v2f32(<2 x float> %x, <2 x i32> %y)
703703
; CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x float> [[X]] to <2 x i32>
704704
; CHECK-NEXT: [[__POW_SIGN:%.*]] = and <2 x i32> [[__YEVEN]], [[TMP0]]
705705
; CHECK-NEXT: [[TMP1:%.*]] = bitcast <2 x float> [[__EXP2]] to <2 x i32>
706-
; CHECK-NEXT: [[TMP2:%.*]] = or <2 x i32> [[__POW_SIGN]], [[TMP1]]
706+
; CHECK-NEXT: [[TMP2:%.*]] = or disjoint <2 x i32> [[__POW_SIGN]], [[TMP1]]
707707
; CHECK-NEXT: [[TMP3:%.*]] = bitcast <2 x i32> [[TMP2]] to <2 x float>
708708
; CHECK-NEXT: ret <2 x float> [[TMP3]]
709709
;
@@ -772,7 +772,7 @@ define half @test_pown_afn_nnan_ninf_f16(half %x, i32 %y) {
772772
; CHECK-NEXT: [[TMP0:%.*]] = bitcast half [[X]] to i16
773773
; CHECK-NEXT: [[__POW_SIGN:%.*]] = and i16 [[__YEVEN]], [[TMP0]]
774774
; CHECK-NEXT: [[TMP1:%.*]] = bitcast half [[__EXP2]] to i16
775-
; CHECK-NEXT: [[TMP2:%.*]] = or i16 [[__POW_SIGN]], [[TMP1]]
775+
; CHECK-NEXT: [[TMP2:%.*]] = or disjoint i16 [[__POW_SIGN]], [[TMP1]]
776776
; CHECK-NEXT: [[TMP3:%.*]] = bitcast i16 [[TMP2]] to half
777777
; CHECK-NEXT: ret half [[TMP3]]
778778
;
@@ -795,7 +795,7 @@ define <2 x half> @test_pown_afn_nnan_ninf_v2f16(<2 x half> %x, <2 x i32> %y) {
795795
; CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x half> [[X]] to <2 x i16>
796796
; CHECK-NEXT: [[__POW_SIGN:%.*]] = and <2 x i16> [[__YEVEN]], [[TMP0]]
797797
; CHECK-NEXT: [[TMP1:%.*]] = bitcast <2 x half> [[__EXP2]] to <2 x i16>
798-
; CHECK-NEXT: [[TMP2:%.*]] = or <2 x i16> [[__POW_SIGN]], [[TMP1]]
798+
; CHECK-NEXT: [[TMP2:%.*]] = or disjoint <2 x i16> [[__POW_SIGN]], [[TMP1]]
799799
; CHECK-NEXT: [[TMP3:%.*]] = bitcast <2 x i16> [[TMP2]] to <2 x half>
800800
; CHECK-NEXT: ret <2 x half> [[TMP3]]
801801
;
@@ -829,7 +829,7 @@ define float @test_pown_fast_f32_strictfp(float %x, i32 %y) #1 {
829829
; CHECK-NEXT: [[TMP0:%.*]] = bitcast float [[X]] to i32
830830
; CHECK-NEXT: [[__POW_SIGN:%.*]] = and i32 [[__YEVEN]], [[TMP0]]
831831
; CHECK-NEXT: [[TMP1:%.*]] = bitcast float [[__EXP2]] to i32
832-
; CHECK-NEXT: [[TMP2:%.*]] = or i32 [[__POW_SIGN]], [[TMP1]]
832+
; CHECK-NEXT: [[TMP2:%.*]] = or disjoint i32 [[__POW_SIGN]], [[TMP1]]
833833
; CHECK-NEXT: [[TMP3:%.*]] = bitcast i32 [[TMP2]] to float
834834
; CHECK-NEXT: ret float [[TMP3]]
835835
;
@@ -1075,7 +1075,7 @@ define float @test_pown_afn_ninf_nnan_f32__x_known_positive(float nofpclass(ninf
10751075
; CHECK-NEXT: [[TMP0:%.*]] = bitcast float [[X]] to i32
10761076
; CHECK-NEXT: [[__POW_SIGN:%.*]] = and i32 [[__YEVEN]], [[TMP0]]
10771077
; CHECK-NEXT: [[TMP1:%.*]] = bitcast float [[__EXP2]] to i32
1078-
; CHECK-NEXT: [[TMP2:%.*]] = or i32 [[__POW_SIGN]], [[TMP1]]
1078+
; CHECK-NEXT: [[TMP2:%.*]] = or disjoint i32 [[__POW_SIGN]], [[TMP1]]
10791079
; CHECK-NEXT: [[TMP3:%.*]] = bitcast i32 [[TMP2]] to float
10801080
; CHECK-NEXT: ret float [[TMP3]]
10811081
;

‎llvm/test/CodeGen/AMDGPU/simplify-libcalls.ll

Lines changed: 5 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -360,7 +360,7 @@ declare half @_Z4pownDhi(half, i32)
360360
; GCN-NATIVE: %0 = bitcast half %x to i16
361361
; GCN-NATIVE: %__pow_sign = and i16 %__yeven, %0
362362
; GCN-NATIVE: %1 = bitcast half %__exp2 to i16
363-
; GCN-NATIVE: %2 = or i16 %__pow_sign, %1
363+
; GCN-NATIVE: %2 = or disjoint i16 %__pow_sign, %1
364364
; GCN-NATIVE: %3 = bitcast i16 %2 to half
365365
define half @test_pown_f16(half %x, i32 %y) {
366366
entry:
@@ -378,7 +378,7 @@ declare float @_Z4pownfi(float, i32)
378378
; GCN: %[[r0:.*]] = bitcast float %tmp to i32
379379
; GCN: %__pow_sign = and i32 %[[r0]], -2147483648
380380
; GCN: %[[r1:.*]] = bitcast float %__exp2 to i32
381-
; GCN: %[[r2:.*]] = or i32 %__pow_sign, %[[r1]]
381+
; GCN: %[[r2:.*]] = or disjoint i32 %__pow_sign, %[[r1]]
382382
; GCN: store i32 %[[r2]], ptr addrspace(1) %a, align 4
383383
define amdgpu_kernel void @test_pow(ptr addrspace(1) nocapture %a) {
384384
entry:
@@ -414,7 +414,7 @@ entry:
414414
; GCN: %[[r0:.*]] = bitcast float %tmp to i32
415415
; GCN: %__pow_sign = and i32 %__yeven, %[[r0]]
416416
; GCN: %[[r1:.*]] = bitcast float %__exp2 to i32
417-
; GCN: %[[r2:.*]] = or i32 %__pow_sign, %[[r1]]
417+
; GCN: %[[r2:.*]] = or disjoint i32 %__pow_sign, %[[r1]]
418418
; GCN: store i32 %[[r2]], ptr addrspace(1) %a, align 4
419419
define amdgpu_kernel void @test_pown(ptr addrspace(1) nocapture %a) {
420420
entry:
@@ -438,7 +438,7 @@ declare <2 x half> @_Z3powDv2_DhS_(<2 x half>, <2 x half>)
438438
; GCN: %1 = bitcast half %x to i16
439439
; GCN: %__pow_sign = and i16 %1, -32768
440440
; GCN: %2 = bitcast half %__exp2 to i16
441-
; GCN: %3 = or i16 %__pow_sign, %2
441+
; GCN: %3 = or disjoint i16 %__pow_sign, %2
442442
; GCN: %4 = bitcast i16 %3 to half
443443
define half @test_pow_fast_f16__y_13(half %x) {
444444
%powr = tail call fast half @_Z3powDhDh(half %x, half 13.0)
@@ -453,7 +453,7 @@ define half @test_pow_fast_f16__y_13(half %x) {
453453
; GCN: %1 = bitcast <2 x half> %x to <2 x i16>
454454
; GCN: %__pow_sign = and <2 x i16> %1, <i16 -32768, i16 -32768>
455455
; GCN: %2 = bitcast <2 x half> %__exp2 to <2 x i16>
456-
; GCN: %3 = or <2 x i16> %__pow_sign, %2
456+
; GCN: %3 = or disjoint <2 x i16> %__pow_sign, %2
457457
; GCN: %4 = bitcast <2 x i16> %3 to <2 x half>
458458
define <2 x half> @test_pow_fast_v2f16__y_13(<2 x half> %x) {
459459
%powr = tail call fast <2 x half> @_Z3powDv2_DhS_(<2 x half> %x, <2 x half> <half 13.0, half 13.0>)

‎llvm/test/Transforms/InstCombine/known-bits.ll

Lines changed: 10 additions & 39 deletions
Original file line numberDiff line numberDiff line change
@@ -485,10 +485,7 @@ if.else:
485485

486486
define i1 @test_sign_pos(float %x) {
487487
; CHECK-LABEL: @test_sign_pos(
488-
; CHECK-NEXT: [[FABS:%.*]] = call float @llvm.fabs.f32(float [[X:%.*]])
489-
; CHECK-NEXT: [[Y:%.*]] = bitcast float [[FABS]] to i32
490-
; CHECK-NEXT: [[SIGN:%.*]] = icmp sgt i32 [[Y]], -1
491-
; CHECK-NEXT: ret i1 [[SIGN]]
488+
; CHECK-NEXT: ret i1 true
492489
;
493490
%fabs = call float @llvm.fabs.f32(float %x)
494491
%y = bitcast float %fabs to i32
@@ -498,11 +495,7 @@ define i1 @test_sign_pos(float %x) {
498495

499496
define i1 @test_sign_neg(float %x) {
500497
; CHECK-LABEL: @test_sign_neg(
501-
; CHECK-NEXT: [[FABS:%.*]] = call float @llvm.fabs.f32(float [[X:%.*]])
502-
; CHECK-NEXT: [[FNABS:%.*]] = fneg float [[FABS]]
503-
; CHECK-NEXT: [[Y:%.*]] = bitcast float [[FNABS]] to i32
504-
; CHECK-NEXT: [[SIGN:%.*]] = icmp slt i32 [[Y]], 0
505-
; CHECK-NEXT: ret i1 [[SIGN]]
498+
; CHECK-NEXT: ret i1 true
506499
;
507500
%fabs = call float @llvm.fabs.f32(float %x)
508501
%fnabs = fneg float %fabs
@@ -513,10 +506,7 @@ define i1 @test_sign_neg(float %x) {
513506

514507
define <2 x i1> @test_sign_pos_vec(<2 x float> %x) {
515508
; CHECK-LABEL: @test_sign_pos_vec(
516-
; CHECK-NEXT: [[FABS:%.*]] = call <2 x float> @llvm.fabs.v2f32(<2 x float> [[X:%.*]])
517-
; CHECK-NEXT: [[Y:%.*]] = bitcast <2 x float> [[FABS]] to <2 x i32>
518-
; CHECK-NEXT: [[SIGN:%.*]] = icmp slt <2 x i32> [[Y]], zeroinitializer
519-
; CHECK-NEXT: ret <2 x i1> [[SIGN]]
509+
; CHECK-NEXT: ret <2 x i1> zeroinitializer
520510
;
521511
%fabs = call <2 x float> @llvm.fabs.v2f32(<2 x float> %x)
522512
%y = bitcast <2 x float> %fabs to <2 x i32>
@@ -526,9 +516,7 @@ define <2 x i1> @test_sign_pos_vec(<2 x float> %x) {
526516

527517
define i32 @test_inf_only(float nofpclass(nan sub norm zero) %x) {
528518
; CHECK-LABEL: @test_inf_only(
529-
; CHECK-NEXT: [[TMP1:%.*]] = call float @llvm.fabs.f32(float [[X:%.*]])
530-
; CHECK-NEXT: [[AND:%.*]] = bitcast float [[TMP1]] to i32
531-
; CHECK-NEXT: ret i32 [[AND]]
519+
; CHECK-NEXT: ret i32 2130706432
532520
;
533521
%y = bitcast float %x to i32
534522
%and = and i32 %y, 2147483647
@@ -537,9 +525,7 @@ define i32 @test_inf_only(float nofpclass(nan sub norm zero) %x) {
537525

538526
define i32 @test_zero_only(float nofpclass(nan sub norm inf) %x) {
539527
; CHECK-LABEL: @test_zero_only(
540-
; CHECK-NEXT: [[TMP1:%.*]] = call float @llvm.fabs.f32(float [[X:%.*]])
541-
; CHECK-NEXT: [[AND:%.*]] = bitcast float [[TMP1]] to i32
542-
; CHECK-NEXT: ret i32 [[AND]]
528+
; CHECK-NEXT: ret i32 0
543529
;
544530
%y = bitcast float %x to i32
545531
%and = and i32 %y, 2147483647
@@ -548,9 +534,7 @@ define i32 @test_zero_only(float nofpclass(nan sub norm inf) %x) {
548534

549535
define i32 @test_inf_nan_only(float nofpclass(sub norm zero) %x) {
550536
; CHECK-LABEL: @test_inf_nan_only(
551-
; CHECK-NEXT: [[Y:%.*]] = bitcast float [[X:%.*]] to i32
552-
; CHECK-NEXT: [[AND:%.*]] = and i32 [[Y]], 2130706432
553-
; CHECK-NEXT: ret i32 [[AND]]
537+
; CHECK-NEXT: ret i32 2130706432
554538
;
555539
%y = bitcast float %x to i32
556540
%and = and i32 %y, 2130706432
@@ -559,9 +543,7 @@ define i32 @test_inf_nan_only(float nofpclass(sub norm zero) %x) {
559543

560544
define i32 @test_sub_zero_only(float nofpclass(nan norm inf) %x) {
561545
; CHECK-LABEL: @test_sub_zero_only(
562-
; CHECK-NEXT: [[Y:%.*]] = bitcast float [[X:%.*]] to i32
563-
; CHECK-NEXT: [[AND:%.*]] = and i32 [[Y]], 2130706432
564-
; CHECK-NEXT: ret i32 [[AND]]
546+
; CHECK-NEXT: ret i32 0
565547
;
566548
%y = bitcast float %x to i32
567549
%and = and i32 %y, 2130706432
@@ -570,9 +552,7 @@ define i32 @test_sub_zero_only(float nofpclass(nan norm inf) %x) {
570552

571553
define i32 @test_inf_zero_only(float nofpclass(nan norm sub) %x) {
572554
; CHECK-LABEL: @test_inf_zero_only(
573-
; CHECK-NEXT: [[Y:%.*]] = bitcast float [[X:%.*]] to i32
574-
; CHECK-NEXT: [[AND:%.*]] = and i32 [[Y]], 16777215
575-
; CHECK-NEXT: ret i32 [[AND]]
555+
; CHECK-NEXT: ret i32 0
576556
;
577557
%y = bitcast float %x to i32
578558
%and = and i32 %y, 16777215
@@ -581,11 +561,7 @@ define i32 @test_inf_zero_only(float nofpclass(nan norm sub) %x) {
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define i1 @test_simplify_icmp(i32 %x) {
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; CHECK-LABEL: @test_simplify_icmp(
584-
; CHECK-NEXT: [[CONV_I_I:%.*]] = uitofp i32 [[X:%.*]] to double
585-
; CHECK-NEXT: [[TMP1:%.*]] = bitcast double [[CONV_I_I]] to i64
586-
; CHECK-NEXT: [[SHR_I_MASK_I:%.*]] = and i64 [[TMP1]], -140737488355328
587-
; CHECK-NEXT: [[CMP_I:%.*]] = icmp eq i64 [[SHR_I_MASK_I]], -1970324836974592
588-
; CHECK-NEXT: ret i1 [[CMP_I]]
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; CHECK-NEXT: ret i1 false
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;
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%conv.i.i = uitofp i32 %x to double
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%3 = bitcast double %conv.i.i to i64
@@ -600,12 +576,7 @@ define i16 @test_simplify_mask(i32 %ui, float %x) {
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; CHECK-NEXT: [[CMP:%.*]] = fcmp ogt float [[CONV]], [[X:%.*]]
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; CHECK-NEXT: br i1 [[CMP]], label [[IF_ELSE:%.*]], label [[IF_END:%.*]]
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; CHECK: if.end:
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; CHECK-NEXT: [[CAST:%.*]] = bitcast float [[CONV]] to i32
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; CHECK-NEXT: [[SHR:%.*]] = lshr i32 [[CAST]], 16
605-
; CHECK-NEXT: [[TRUNC:%.*]] = trunc i32 [[SHR]] to i16
606-
; CHECK-NEXT: [[AND:%.*]] = and i16 [[TRUNC]], -32768
607-
; CHECK-NEXT: [[OR:%.*]] = or disjoint i16 [[AND]], 31744
608-
; CHECK-NEXT: ret i16 [[OR]]
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; CHECK-NEXT: ret i16 31744
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; CHECK: if.else:
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; CHECK-NEXT: ret i16 0
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;

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