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LiqinWengLiqinWeng
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[LV][EVL] Support cast instruction with EVL-vectorization
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6 files changed

+364
-16
lines changed

6 files changed

+364
-16
lines changed

‎llvm/lib/Transforms/Vectorize/VPlan.h

Lines changed: 72 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -921,6 +921,7 @@ class VPSingleDefRecipe : public VPRecipeBase, public VPValue {
921921
case VPRecipeBase::VPWidenCallSC:
922922
case VPRecipeBase::VPWidenCanonicalIVSC:
923923
case VPRecipeBase::VPWidenCastSC:
924+
case VPRecipeBase::VPWidenCastEVLSC:
924925
case VPRecipeBase::VPWidenGEPSC:
925926
case VPRecipeBase::VPWidenSC:
926927
case VPRecipeBase::VPWidenEVLSC:
@@ -1112,6 +1113,7 @@ class VPRecipeWithIRFlags : public VPSingleDefRecipe {
11121113
R->getVPDefID() == VPRecipeBase::VPWidenEVLSC ||
11131114
R->getVPDefID() == VPRecipeBase::VPWidenGEPSC ||
11141115
R->getVPDefID() == VPRecipeBase::VPWidenCastSC ||
1116+
R->getVPDefID() == VPRecipeBase::VPWidenCastEVLSC ||
11151117
R->getVPDefID() == VPRecipeBase::VPReplicateSC ||
11161118
R->getVPDefID() == VPRecipeBase::VPVectorPointerSC;
11171119
}
@@ -1554,19 +1556,28 @@ class VPWidenCastRecipe : public VPRecipeWithIRFlags {
15541556
/// Result type for the cast.
15551557
Type *ResultTy;
15561558

1557-
public:
1558-
VPWidenCastRecipe(Instruction::CastOps Opcode, VPValue *Op, Type *ResultTy,
1559-
CastInst &UI)
1559+
protected:
1560+
VPWidenCastRecipe(unsigned VPDefOpcode, Instruction::CastOps Opcode,
1561+
VPValue *Op, Type *ResultTy, CastInst &UI)
15601562
: VPRecipeWithIRFlags(VPDef::VPWidenCastSC, Op, UI), Opcode(Opcode),
15611563
ResultTy(ResultTy) {
15621564
assert(UI.getOpcode() == Opcode &&
15631565
"opcode of underlying cast doesn't match");
15641566
}
15651567

1566-
VPWidenCastRecipe(Instruction::CastOps Opcode, VPValue *Op, Type *ResultTy)
1568+
VPWidenCastRecipe(unsigned VPDefOpcode, Instruction::CastOps Opcode,
1569+
VPValue *Op, Type *ResultTy)
15671570
: VPRecipeWithIRFlags(VPDef::VPWidenCastSC, Op), Opcode(Opcode),
15681571
ResultTy(ResultTy) {}
15691572

1573+
public:
1574+
VPWidenCastRecipe(Instruction::CastOps Opcode, VPValue *Op, Type *ResultTy,
1575+
CastInst &UI)
1576+
: VPWidenCastRecipe(VPDef::VPWidenCastSC, Opcode, Op, ResultTy, UI) {}
1577+
1578+
VPWidenCastRecipe(Instruction::CastOps Opcode, VPValue *Op, Type *ResultTy)
1579+
: VPWidenCastRecipe(VPDef::VPWidenCastSC, Opcode, Op, ResultTy) {}
1580+
15701581
~VPWidenCastRecipe() override = default;
15711582

15721583
VPWidenCastRecipe *clone() override {
@@ -1577,7 +1588,15 @@ class VPWidenCastRecipe : public VPRecipeWithIRFlags {
15771588
return new VPWidenCastRecipe(Opcode, getOperand(0), ResultTy);
15781589
}
15791590

1580-
VP_CLASSOF_IMPL(VPDef::VPWidenCastSC)
1591+
static inline bool classof(const VPRecipeBase *R) {
1592+
return R->getVPDefID() == VPRecipeBase::VPWidenCastSC ||
1593+
R->getVPDefID() == VPRecipeBase::VPWidenCastEVLSC;
1594+
}
1595+
1596+
static inline bool classof(const VPUser *U) {
1597+
auto *R = dyn_cast<VPRecipeBase>(U);
1598+
return R && classof(R);
1599+
}
15811600

15821601
/// Produce widened copies of the cast.
15831602
void execute(VPTransformState &State) override;
@@ -1594,6 +1613,54 @@ class VPWidenCastRecipe : public VPRecipeWithIRFlags {
15941613
Type *getResultType() const { return ResultTy; }
15951614
};
15961615

1616+
// A recipe for widening cast operation with vector-predication intrinsics with
1617+
/// explicit vector length (EVL).
1618+
class VPWidenCastEVLRecipe : public VPWidenCastRecipe {
1619+
using VPRecipeWithIRFlags::transferFlags;
1620+
1621+
public:
1622+
VPWidenCastEVLRecipe(Instruction::CastOps Opcode, VPValue *Op, Type *ResultTy,
1623+
VPValue &EVL)
1624+
: VPWidenCastRecipe(VPDef::VPWidenCastEVLSC, Opcode, Op, ResultTy) {
1625+
addOperand(&EVL);
1626+
}
1627+
VPWidenCastEVLRecipe(VPWidenCastRecipe &W, VPValue &EVL)
1628+
: VPWidenCastEVLRecipe(W.getOpcode(), W.getOperand(0), W.getResultType(),
1629+
EVL) {
1630+
transferFlags(W);
1631+
}
1632+
1633+
~VPWidenCastEVLRecipe() override = default;
1634+
1635+
VPWidenCastEVLRecipe *clone() final {
1636+
llvm_unreachable("VPWidenEVLRecipe cannot be cloned");
1637+
return nullptr;
1638+
}
1639+
1640+
VP_CLASSOF_IMPL(VPDef::VPWidenCastEVLSC)
1641+
1642+
VPValue *getEVL() { return getOperand(getNumOperands() - 1); }
1643+
const VPValue *getEVL() const { return getOperand(getNumOperands() - 1); }
1644+
1645+
/// Produce a vp-intrinsic copies of the cast.
1646+
void execute(VPTransformState &State) final;
1647+
1648+
/// Returns true if the recipe only uses the first lane of operand \p Op.
1649+
bool onlyFirstLaneUsed(const VPValue *Op) const override {
1650+
assert(is_contained(operands(), Op) &&
1651+
"Op must be an operand of the recipe");
1652+
// EVL in that recipe is always the last operand, thus any use before means
1653+
// the VPValue should be vectorized.
1654+
return getEVL() == Op;
1655+
}
1656+
1657+
#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
1658+
/// Print the recipe.
1659+
void print(raw_ostream &O, const Twine &Indent,
1660+
VPSlotTracker &SlotTracker) const final;
1661+
#endif
1662+
};
1663+
15971664
/// VPScalarCastRecipe is a recipe to create scalar cast instructions.
15981665
class VPScalarCastRecipe : public VPSingleDefRecipe {
15991666
Instruction::CastOps Opcode;

‎llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp

Lines changed: 45 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -69,6 +69,7 @@ bool VPRecipeBase::mayWriteToMemory() const {
6969
case VPReductionSC:
7070
case VPWidenCanonicalIVSC:
7171
case VPWidenCastSC:
72+
case VPWidenCastEVLSC:
7273
case VPWidenGEPSC:
7374
case VPWidenIntOrFpInductionSC:
7475
case VPWidenLoadEVLSC:
@@ -112,6 +113,7 @@ bool VPRecipeBase::mayReadFromMemory() const {
112113
case VPReductionSC:
113114
case VPWidenCanonicalIVSC:
114115
case VPWidenCastSC:
116+
case VPWidenCastEVLSC:
115117
case VPWidenGEPSC:
116118
case VPWidenIntOrFpInductionSC:
117119
case VPWidenPHISC:
@@ -162,6 +164,7 @@ bool VPRecipeBase::mayHaveSideEffects() const {
162164
case VPScalarIVStepsSC:
163165
case VPWidenCanonicalIVSC:
164166
case VPWidenCastSC:
167+
case VPWidenCastEVLSC:
165168
case VPWidenGEPSC:
166169
case VPWidenIntOrFpInductionSC:
167170
case VPWidenPHISC:
@@ -1381,12 +1384,53 @@ void VPWidenCastRecipe::execute(VPTransformState &State) {
13811384
}
13821385
}
13831386

1387+
void VPWidenCastEVLRecipe::execute(VPTransformState &State) {
1388+
unsigned Opcode = getOpcode();
1389+
State.setDebugLocFrom(getDebugLoc());
1390+
assert(State.UF == 1 && "Expected only UF == 1 when vectorizing with "
1391+
"explicit vector length.");
1392+
1393+
// TODO: add more cast instruction, eg: fptoint/inttofp/inttoptr/fptofp
1394+
if (Opcode == Instruction::SExt || Opcode == Instruction::ZExt ||
1395+
Opcode == Instruction::Trunc) {
1396+
Value *SrcVal = State.get(getOperand(0), 0);
1397+
VectorType *DsType = VectorType::get(getResultType(), State.VF);
1398+
1399+
IRBuilderBase &BuilderIR = State.Builder;
1400+
VectorBuilder Builder(BuilderIR);
1401+
Value *Mask = BuilderIR.CreateVectorSplat(State.VF, BuilderIR.getTrue());
1402+
Builder.setMask(Mask).setEVL(State.get(getEVL(), 0, /*NeedsScalar=*/true));
1403+
1404+
Value *VPInst =
1405+
Builder.createVectorInstruction(Opcode, DsType, {SrcVal}, "vp.cast");
1406+
1407+
if (VPInst) {
1408+
if (auto *VecOp = dyn_cast<CastInst>(VPInst))
1409+
VecOp->copyIRFlags(getUnderlyingInstr());
1410+
}
1411+
1412+
State.set(this, VPInst, 0);
1413+
State.addMetadata(VPInst,
1414+
dyn_cast_or_null<Instruction>(getUnderlyingValue()));
1415+
}
1416+
}
1417+
13841418
#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
13851419
void VPWidenCastRecipe::print(raw_ostream &O, const Twine &Indent,
13861420
VPSlotTracker &SlotTracker) const {
13871421
O << Indent << "WIDEN-CAST ";
13881422
printAsOperand(O, SlotTracker);
1389-
O << " = " << Instruction::getOpcodeName(Opcode) << " ";
1423+
O << " = " << Instruction::getOpcodeName(Opcode);
1424+
printFlags(O);
1425+
printOperands(O, SlotTracker);
1426+
O << " to " << *getResultType();
1427+
}
1428+
1429+
void VPWidenCastEVLRecipe::print(raw_ostream &O, const Twine &Indent,
1430+
VPSlotTracker &SlotTracker) const {
1431+
O << Indent << "WIDEN-CAST ";
1432+
printAsOperand(O, SlotTracker);
1433+
O << " = vp." << Instruction::getOpcodeName(getOpcode());
13901434
printFlags(O);
13911435
printOperands(O, SlotTracker);
13921436
O << " to " << *getResultType();

‎llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp

Lines changed: 9 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1343,6 +1343,15 @@ static void transformRecipestoEVLRecipes(VPlan &Plan, VPValue &EVL) {
13431343
return nullptr;
13441344
return new VPWidenEVLRecipe(*W, EVL);
13451345
})
1346+
.Case<VPWidenCastRecipe>(
1347+
[&](VPWidenCastRecipe *W) -> VPRecipeBase * {
1348+
unsigned Opcode = W->getOpcode();
1349+
if (Opcode != Instruction::SExt &&
1350+
Opcode != Instruction::ZExt &&
1351+
Opcode != Instruction::Trunc)
1352+
return nullptr;
1353+
return new VPWidenCastEVLRecipe(*W, EVL);
1354+
})
13461355
.Case<VPReductionRecipe>([&](VPReductionRecipe *Red) {
13471356
VPValue *NewMask = GetNewMask(Red->getCondOp());
13481357
return new VPReductionEVLRecipe(*Red, EVL, NewMask);

‎llvm/lib/Transforms/Vectorize/VPlanValue.h

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -351,6 +351,7 @@ class VPDef {
351351
VPWidenCallSC,
352352
VPWidenCanonicalIVSC,
353353
VPWidenCastSC,
354+
VPWidenCastEVLSC,
354355
VPWidenGEPSC,
355356
VPWidenLoadEVLSC,
356357
VPWidenLoadSC,

‎llvm/test/Transforms/LoopVectorize/RISCV/inloop-reduction.ll

Lines changed: 10 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -159,38 +159,38 @@ define i32 @add_i16_i32(ptr nocapture readonly %x, i32 %n) {
159159
; IF-EVL-INLOOP: vector.body:
160160
; IF-EVL-INLOOP-NEXT: [[INDEX:%.*]] = phi i32 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ]
161161
; IF-EVL-INLOOP-NEXT: [[EVL_BASED_IV:%.*]] = phi i32 [ 0, [[VECTOR_PH]] ], [ [[INDEX_EVL_NEXT:%.*]], [[VECTOR_BODY]] ]
162-
; IF-EVL-INLOOP-NEXT: [[VEC_PHI:%.*]] = phi i32 [ 0, [[VECTOR_PH]] ], [ [[TMP12:%.*]], [[VECTOR_BODY]] ]
162+
; IF-EVL-INLOOP-NEXT: [[VEC_PHI:%.*]] = phi i32 [ 0, [[VECTOR_PH]] ], [ [[TMP11:%.*]], [[VECTOR_BODY]] ]
163163
; IF-EVL-INLOOP-NEXT: [[TMP5:%.*]] = sub i32 [[N]], [[EVL_BASED_IV]]
164164
; IF-EVL-INLOOP-NEXT: [[TMP6:%.*]] = call i32 @llvm.experimental.get.vector.length.i32(i32 [[TMP5]], i32 8, i1 true)
165165
; IF-EVL-INLOOP-NEXT: [[TMP7:%.*]] = add i32 [[EVL_BASED_IV]], 0
166166
; IF-EVL-INLOOP-NEXT: [[TMP8:%.*]] = getelementptr inbounds i16, ptr [[X:%.*]], i32 [[TMP7]]
167167
; IF-EVL-INLOOP-NEXT: [[TMP9:%.*]] = getelementptr inbounds i16, ptr [[TMP8]], i32 0
168168
; IF-EVL-INLOOP-NEXT: [[VP_OP_LOAD:%.*]] = call <vscale x 8 x i16> @llvm.vp.load.nxv8i16.p0(ptr align 2 [[TMP9]], <vscale x 8 x i1> shufflevector (<vscale x 8 x i1> insertelement (<vscale x 8 x i1> poison, i1 true, i64 0), <vscale x 8 x i1> poison, <vscale x 8 x i32> zeroinitializer), i32 [[TMP6]])
169-
; IF-EVL-INLOOP-NEXT: [[TMP10:%.*]] = sext <vscale x 8 x i16> [[VP_OP_LOAD]] to <vscale x 8 x i32>
170-
; IF-EVL-INLOOP-NEXT: [[TMP11:%.*]] = call i32 @llvm.vp.reduce.add.nxv8i32(i32 0, <vscale x 8 x i32> [[TMP10]], <vscale x 8 x i1> shufflevector (<vscale x 8 x i1> insertelement (<vscale x 8 x i1> poison, i1 true, i64 0), <vscale x 8 x i1> poison, <vscale x 8 x i32> zeroinitializer), i32 [[TMP6]])
171-
; IF-EVL-INLOOP-NEXT: [[TMP12]] = add i32 [[TMP11]], [[VEC_PHI]]
169+
; IF-EVL-INLOOP-NEXT: [[VP_CAST:%.*]] = call <vscale x 8 x i32> @llvm.vp.sext.nxv8i32.nxv8i16(<vscale x 8 x i16> [[VP_OP_LOAD]], <vscale x 8 x i1> shufflevector (<vscale x 8 x i1> insertelement (<vscale x 8 x i1> poison, i1 true, i64 0), <vscale x 8 x i1> poison, <vscale x 8 x i32> zeroinitializer), i32 [[TMP6]])
170+
; IF-EVL-INLOOP-NEXT: [[TMP10:%.*]] = call i32 @llvm.vp.reduce.add.nxv8i32(i32 0, <vscale x 8 x i32> [[VP_CAST]], <vscale x 8 x i1> shufflevector (<vscale x 8 x i1> insertelement (<vscale x 8 x i1> poison, i1 true, i64 0), <vscale x 8 x i1> poison, <vscale x 8 x i32> zeroinitializer), i32 [[TMP6]])
171+
; IF-EVL-INLOOP-NEXT: [[TMP11]] = add i32 [[TMP10]], [[VEC_PHI]]
172172
; IF-EVL-INLOOP-NEXT: [[INDEX_EVL_NEXT]] = add i32 [[TMP6]], [[EVL_BASED_IV]]
173173
; IF-EVL-INLOOP-NEXT: [[INDEX_NEXT]] = add i32 [[INDEX]], [[TMP4]]
174-
; IF-EVL-INLOOP-NEXT: [[TMP13:%.*]] = icmp eq i32 [[INDEX_NEXT]], [[N_VEC]]
175-
; IF-EVL-INLOOP-NEXT: br i1 [[TMP13]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]]
174+
; IF-EVL-INLOOP-NEXT: [[TMP12:%.*]] = icmp eq i32 [[INDEX_NEXT]], [[N_VEC]]
175+
; IF-EVL-INLOOP-NEXT: br i1 [[TMP12]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]]
176176
; IF-EVL-INLOOP: middle.block:
177177
; IF-EVL-INLOOP-NEXT: br i1 true, label [[FOR_COND_CLEANUP_LOOPEXIT:%.*]], label [[SCALAR_PH]]
178178
; IF-EVL-INLOOP: scalar.ph:
179179
; IF-EVL-INLOOP-NEXT: [[BC_RESUME_VAL:%.*]] = phi i32 [ [[N_VEC]], [[MIDDLE_BLOCK]] ], [ 0, [[FOR_BODY_PREHEADER]] ]
180-
; IF-EVL-INLOOP-NEXT: [[BC_MERGE_RDX:%.*]] = phi i32 [ [[TMP12]], [[MIDDLE_BLOCK]] ], [ 0, [[FOR_BODY_PREHEADER]] ]
180+
; IF-EVL-INLOOP-NEXT: [[BC_MERGE_RDX:%.*]] = phi i32 [ [[TMP11]], [[MIDDLE_BLOCK]] ], [ 0, [[FOR_BODY_PREHEADER]] ]
181181
; IF-EVL-INLOOP-NEXT: br label [[FOR_BODY:%.*]]
182182
; IF-EVL-INLOOP: for.body:
183183
; IF-EVL-INLOOP-NEXT: [[I_08:%.*]] = phi i32 [ [[INC:%.*]], [[FOR_BODY]] ], [ [[BC_RESUME_VAL]], [[SCALAR_PH]] ]
184184
; IF-EVL-INLOOP-NEXT: [[R_07:%.*]] = phi i32 [ [[ADD:%.*]], [[FOR_BODY]] ], [ [[BC_MERGE_RDX]], [[SCALAR_PH]] ]
185185
; IF-EVL-INLOOP-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, ptr [[X]], i32 [[I_08]]
186-
; IF-EVL-INLOOP-NEXT: [[TMP14:%.*]] = load i16, ptr [[ARRAYIDX]], align 2
187-
; IF-EVL-INLOOP-NEXT: [[CONV:%.*]] = sext i16 [[TMP14]] to i32
186+
; IF-EVL-INLOOP-NEXT: [[TMP13:%.*]] = load i16, ptr [[ARRAYIDX]], align 2
187+
; IF-EVL-INLOOP-NEXT: [[CONV:%.*]] = sext i16 [[TMP13]] to i32
188188
; IF-EVL-INLOOP-NEXT: [[ADD]] = add nsw i32 [[R_07]], [[CONV]]
189189
; IF-EVL-INLOOP-NEXT: [[INC]] = add nuw nsw i32 [[I_08]], 1
190190
; IF-EVL-INLOOP-NEXT: [[EXITCOND:%.*]] = icmp eq i32 [[INC]], [[N]]
191191
; IF-EVL-INLOOP-NEXT: br i1 [[EXITCOND]], label [[FOR_COND_CLEANUP_LOOPEXIT]], label [[FOR_BODY]], !llvm.loop [[LOOP3:![0-9]+]]
192192
; IF-EVL-INLOOP: for.cond.cleanup.loopexit:
193-
; IF-EVL-INLOOP-NEXT: [[ADD_LCSSA:%.*]] = phi i32 [ [[ADD]], [[FOR_BODY]] ], [ [[TMP12]], [[MIDDLE_BLOCK]] ]
193+
; IF-EVL-INLOOP-NEXT: [[ADD_LCSSA:%.*]] = phi i32 [ [[ADD]], [[FOR_BODY]] ], [ [[TMP11]], [[MIDDLE_BLOCK]] ]
194194
; IF-EVL-INLOOP-NEXT: br label [[FOR_COND_CLEANUP]]
195195
; IF-EVL-INLOOP: for.cond.cleanup:
196196
; IF-EVL-INLOOP-NEXT: [[R_0_LCSSA:%.*]] = phi i32 [ 0, [[ENTRY:%.*]] ], [ [[ADD_LCSSA]], [[FOR_COND_CLEANUP_LOOPEXIT]] ]

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