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[AVR] Force relocations for non-encodable jumps (#121498)
This commit changes the branch emission logic so that instead of throwing the "branch target out of range" error, we emit a relocation instead.
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24 files changed

+75
-50
lines changed

24 files changed

+75
-50
lines changed

‎llvm/include/llvm/MC/MCAsmBackend.h

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -94,6 +94,7 @@ class MCAsmBackend {
9494
virtual bool shouldForceRelocation(const MCAssembler &Asm,
9595
const MCFixup &Fixup,
9696
const MCValue &Target,
97+
const uint64_t Value,
9798
const MCSubtargetInfo *STI) {
9899
return false;
99100
}

‎llvm/lib/MC/MCAssembler.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -231,7 +231,7 @@ bool MCAssembler::evaluateFixup(const MCFixup &Fixup, const MCFragment *DF,
231231

232232
// Let the backend force a relocation if needed.
233233
if (IsResolved &&
234-
getBackend().shouldForceRelocation(*this, Fixup, Target, STI)) {
234+
getBackend().shouldForceRelocation(*this, Fixup, Target, Value, STI)) {
235235
IsResolved = false;
236236
WasForced = true;
237237
}

‎llvm/lib/Target/AArch64/MCTargetDesc/AArch64AsmBackend.cpp

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -100,7 +100,7 @@ class AArch64AsmBackend : public MCAsmBackend {
100100
unsigned getFixupKindContainereSizeInBytes(unsigned Kind) const;
101101

102102
bool shouldForceRelocation(const MCAssembler &Asm, const MCFixup &Fixup,
103-
const MCValue &Target,
103+
const MCValue &Target, const uint64_t Value,
104104
const MCSubtargetInfo *STI) override;
105105
};
106106

@@ -512,6 +512,7 @@ bool AArch64AsmBackend::writeNopData(raw_ostream &OS, uint64_t Count,
512512
bool AArch64AsmBackend::shouldForceRelocation(const MCAssembler &Asm,
513513
const MCFixup &Fixup,
514514
const MCValue &Target,
515+
const uint64_t,
515516
const MCSubtargetInfo *STI) {
516517
unsigned Kind = Fixup.getKind();
517518
if (Kind >= FirstLiteralRelocationKind)

‎llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUAsmBackend.cpp

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -53,7 +53,7 @@ class AMDGPUAsmBackend : public MCAsmBackend {
5353
std::optional<MCFixupKind> getFixupKind(StringRef Name) const override;
5454
const MCFixupKindInfo &getFixupKindInfo(MCFixupKind Kind) const override;
5555
bool shouldForceRelocation(const MCAssembler &Asm, const MCFixup &Fixup,
56-
const MCValue &Target,
56+
const MCValue &Target, uint64_t Value,
5757
const MCSubtargetInfo *STI) override;
5858
};
5959

@@ -191,7 +191,7 @@ const MCFixupKindInfo &AMDGPUAsmBackend::getFixupKindInfo(
191191

192192
bool AMDGPUAsmBackend::shouldForceRelocation(const MCAssembler &,
193193
const MCFixup &Fixup,
194-
const MCValue &,
194+
const MCValue &, const uint64_t,
195195
const MCSubtargetInfo *STI) {
196196
return Fixup.getKind() >= FirstLiteralRelocationKind;
197197
}

‎llvm/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -909,7 +909,7 @@ unsigned ARMAsmBackend::adjustFixupValue(const MCAssembler &Asm,
909909

910910
bool ARMAsmBackend::shouldForceRelocation(const MCAssembler &Asm,
911911
const MCFixup &Fixup,
912-
const MCValue &Target,
912+
const MCValue &Target, const uint64_t,
913913
const MCSubtargetInfo *STI) {
914914
const MCSymbolRefExpr *A = Target.getSymA();
915915
const MCSymbol *Sym = A ? &A->getSymbol() : nullptr;

‎llvm/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.h

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -36,7 +36,7 @@ class ARMAsmBackend : public MCAsmBackend {
3636
const MCFixupKindInfo &getFixupKindInfo(MCFixupKind Kind) const override;
3737

3838
bool shouldForceRelocation(const MCAssembler &Asm, const MCFixup &Fixup,
39-
const MCValue &Target,
39+
const MCValue &Target, const uint64_t Value,
4040
const MCSubtargetInfo *STI) override;
4141

4242
unsigned adjustFixupValue(const MCAssembler &Asm, const MCFixup &Fixup,

‎llvm/lib/Target/AVR/MCTargetDesc/AVRAsmBackend.cpp

Lines changed: 31 additions & 27 deletions
Original file line numberDiff line numberDiff line change
@@ -32,22 +32,6 @@ namespace adjust {
3232

3333
using namespace llvm;
3434

35-
static void signed_width(unsigned Width, uint64_t Value,
36-
std::string Description, const MCFixup &Fixup,
37-
MCContext *Ctx) {
38-
if (!isIntN(Width, Value)) {
39-
std::string Diagnostic = "out of range " + Description;
40-
41-
int64_t Min = minIntN(Width);
42-
int64_t Max = maxIntN(Width);
43-
44-
Diagnostic += " (expected an integer in the range " + std::to_string(Min) +
45-
" to " + std::to_string(Max) + ")";
46-
47-
Ctx->reportError(Fixup.getLoc(), Diagnostic);
48-
}
49-
}
50-
5135
static void unsigned_width(unsigned Width, uint64_t Value,
5236
std::string Description, const MCFixup &Fixup,
5337
MCContext *Ctx) {
@@ -75,17 +59,18 @@ static void adjustBranch(unsigned Size, const MCFixup &Fixup, uint64_t &Value,
7559
}
7660

7761
/// Adjusts the value of a relative branch target before fixup application.
78-
static void adjustRelativeBranch(unsigned Size, const MCFixup &Fixup,
79-
uint64_t &Value, MCContext *Ctx) {
62+
static bool adjustRelativeBranch(unsigned Size, const MCFixup &Fixup,
63+
uint64_t &Value, const MCSubtargetInfo *STI) {
8064
// Jumps are relative to the current instruction.
8165
Value -= 2;
8266

8367
// We have one extra bit of precision because the value is rightshifted by
8468
// one.
8569
Size += 1;
8670

87-
if (!isIntN(Size, Value) &&
88-
Ctx->getSubtargetInfo()->hasFeature(AVR::FeatureWrappingRjmp)) {
71+
assert(STI && "STI can not be NULL");
72+
73+
if (!isIntN(Size, Value) && STI->hasFeature(AVR::FeatureWrappingRjmp)) {
8974
const int32_t FlashSize = 0x2000;
9075
int32_t SignedValue = Value;
9176

@@ -97,10 +82,14 @@ static void adjustRelativeBranch(unsigned Size, const MCFixup &Fixup,
9782
}
9883
}
9984

100-
signed_width(Size, Value, std::string("branch target"), Fixup, Ctx);
85+
if (!isIntN(Size, Value)) {
86+
return false;
87+
}
10188

10289
// Rightshifts the value by one.
10390
AVR::fixups::adjustBranchTarget(Value);
91+
92+
return true;
10493
}
10594

10695
/// 22-bit absolute fixup.
@@ -127,7 +116,9 @@ static void fixup_call(unsigned Size, const MCFixup &Fixup, uint64_t &Value,
127116
/// Offset of 0 (so the result is left shifted by 3 bits before application).
128117
static void fixup_7_pcrel(unsigned Size, const MCFixup &Fixup, uint64_t &Value,
129118
MCContext *Ctx) {
130-
adjustRelativeBranch(Size, Fixup, Value, Ctx);
119+
if (!adjustRelativeBranch(Size, Fixup, Value, Ctx->getSubtargetInfo())) {
120+
llvm_unreachable("should've been emitted as a relocation");
121+
}
131122

132123
// Because the value may be negative, we must mask out the sign bits
133124
Value &= 0x7f;
@@ -141,7 +132,9 @@ static void fixup_7_pcrel(unsigned Size, const MCFixup &Fixup, uint64_t &Value,
141132
/// Offset of 0 (so the result isn't left-shifted before application).
142133
static void fixup_13_pcrel(unsigned Size, const MCFixup &Fixup, uint64_t &Value,
143134
MCContext *Ctx) {
144-
adjustRelativeBranch(Size, Fixup, Value, Ctx);
135+
if (!adjustRelativeBranch(Size, Fixup, Value, Ctx->getSubtargetInfo())) {
136+
llvm_unreachable("should've been emitted as a relocation");
137+
}
145138

146139
// Because the value may be negative, we must mask out the sign bits
147140
Value &= 0xfff;
@@ -182,7 +175,7 @@ static void fixup_port5(const MCFixup &Fixup, uint64_t &Value, MCContext *Ctx) {
182175
Value <<= 3;
183176
}
184177

185-
/// 6-bit port number fixup on the `IN` family of instructions.
178+
/// 6-bit port number fixup on the IN family of instructions.
186179
///
187180
/// Resolves to:
188181
/// 1011 0AAd dddd AAAA
@@ -513,14 +506,25 @@ bool AVRAsmBackend::writeNopData(raw_ostream &OS, uint64_t Count,
513506
bool AVRAsmBackend::shouldForceRelocation(const MCAssembler &Asm,
514507
const MCFixup &Fixup,
515508
const MCValue &Target,
509+
const uint64_t Value,
516510
const MCSubtargetInfo *STI) {
517511
switch ((unsigned)Fixup.getKind()) {
518512
default:
519513
return Fixup.getKind() >= FirstLiteralRelocationKind;
514+
520515
case AVR::fixup_7_pcrel:
521-
case AVR::fixup_13_pcrel:
522-
// Always resolve relocations for PC-relative branches
523-
return false;
516+
case AVR::fixup_13_pcrel: {
517+
uint64_t ValueEx = Value;
518+
uint64_t Size = AVRAsmBackend::getFixupKindInfo(Fixup.getKind()).TargetSize;
519+
520+
// If the jump is too large to encode it, fall back to a relocation.
521+
//
522+
// Note that trying to actually link that relocation *would* fail, but the
523+
// hopes are that the module we're currently compiling won't be actually
524+
// linked to the final binary.
525+
return !adjust::adjustRelativeBranch(Size, Fixup, ValueEx, STI);
526+
}
527+
524528
case AVR::fixup_call:
525529
return true;
526530
}

‎llvm/lib/Target/AVR/MCTargetDesc/AVRAsmBackend.h

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -53,7 +53,7 @@ class AVRAsmBackend : public MCAsmBackend {
5353
const MCSubtargetInfo *STI) const override;
5454

5555
bool shouldForceRelocation(const MCAssembler &Asm, const MCFixup &Fixup,
56-
const MCValue &Target,
56+
const MCValue &Target, const uint64_t Value,
5757
const MCSubtargetInfo *STI) override;
5858

5959
private:

‎llvm/lib/Target/CSKY/MCTargetDesc/CSKYAsmBackend.cpp

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -262,6 +262,7 @@ bool CSKYAsmBackend::mayNeedRelaxation(const MCInst &Inst,
262262
bool CSKYAsmBackend::shouldForceRelocation(const MCAssembler &Asm,
263263
const MCFixup &Fixup,
264264
const MCValue &Target,
265+
const uint64_t /*Value*/,
265266
const MCSubtargetInfo * /*STI*/) {
266267
if (Fixup.getKind() >= FirstLiteralRelocationKind)
267268
return true;

‎llvm/lib/Target/CSKY/MCTargetDesc/CSKYAsmBackend.h

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -52,7 +52,7 @@ class CSKYAsmBackend : public MCAsmBackend {
5252
const MCSubtargetInfo *STI) const override;
5353

5454
bool shouldForceRelocation(const MCAssembler &Asm, const MCFixup &Fixup,
55-
const MCValue &Target,
55+
const MCValue &Target, const uint64_t Value,
5656
const MCSubtargetInfo *STI) override;
5757

5858
std::unique_ptr<MCObjectTargetWriter>

‎llvm/lib/Target/Hexagon/MCTargetDesc/HexagonAsmBackend.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -201,7 +201,7 @@ class HexagonAsmBackend : public MCAsmBackend {
201201
}
202202

203203
bool shouldForceRelocation(const MCAssembler &Asm, const MCFixup &Fixup,
204-
const MCValue &Target,
204+
const MCValue &Target, const uint64_t,
205205
const MCSubtargetInfo *STI) override {
206206
switch(Fixup.getTargetKind()) {
207207
default:

‎llvm/lib/Target/LoongArch/MCTargetDesc/LoongArchAsmBackend.cpp

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -251,6 +251,7 @@ bool LoongArchAsmBackend::shouldInsertFixupForCodeAlign(MCAssembler &Asm,
251251
bool LoongArchAsmBackend::shouldForceRelocation(const MCAssembler &Asm,
252252
const MCFixup &Fixup,
253253
const MCValue &Target,
254+
const uint64_t,
254255
const MCSubtargetInfo *STI) {
255256
if (Fixup.getKind() >= FirstLiteralRelocationKind)
256257
return true;

‎llvm/lib/Target/LoongArch/MCTargetDesc/LoongArchAsmBackend.h

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -57,7 +57,7 @@ class LoongArchAsmBackend : public MCAsmBackend {
5757
MCAlignFragment &AF) override;
5858

5959
bool shouldForceRelocation(const MCAssembler &Asm, const MCFixup &Fixup,
60-
const MCValue &Target,
60+
const MCValue &Target, const uint64_t Value,
6161
const MCSubtargetInfo *STI) override;
6262

6363
unsigned getNumFixupKinds() const override {

‎llvm/lib/Target/Mips/MCTargetDesc/MipsAsmBackend.cpp

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -546,6 +546,7 @@ bool MipsAsmBackend::writeNopData(raw_ostream &OS, uint64_t Count,
546546
bool MipsAsmBackend::shouldForceRelocation(const MCAssembler &Asm,
547547
const MCFixup &Fixup,
548548
const MCValue &Target,
549+
const uint64_t,
549550
const MCSubtargetInfo *STI) {
550551
if (Fixup.getKind() >= FirstLiteralRelocationKind)
551552
return true;

‎llvm/lib/Target/Mips/MCTargetDesc/MipsAsmBackend.h

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -55,7 +55,7 @@ class MipsAsmBackend : public MCAsmBackend {
5555
const MCSubtargetInfo *STI) const override;
5656

5757
bool shouldForceRelocation(const MCAssembler &Asm, const MCFixup &Fixup,
58-
const MCValue &Target,
58+
const MCValue &Target, const uint64_t Value,
5959
const MCSubtargetInfo *STI) override;
6060

6161
bool isMicroMips(const MCSymbol *Sym) const override;

‎llvm/lib/Target/PowerPC/MCTargetDesc/PPCAsmBackend.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -162,7 +162,7 @@ class PPCAsmBackend : public MCAsmBackend {
162162
}
163163

164164
bool shouldForceRelocation(const MCAssembler &Asm, const MCFixup &Fixup,
165-
const MCValue &Target,
165+
const MCValue &Target, const uint64_t,
166166
const MCSubtargetInfo *STI) override {
167167
MCFixupKind Kind = Fixup.getKind();
168168
switch ((unsigned)Kind) {

‎llvm/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.cpp

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -114,6 +114,7 @@ RISCVAsmBackend::getFixupKindInfo(MCFixupKind Kind) const {
114114
bool RISCVAsmBackend::shouldForceRelocation(const MCAssembler &Asm,
115115
const MCFixup &Fixup,
116116
const MCValue &Target,
117+
const uint64_t,
117118
const MCSubtargetInfo *STI) {
118119
if (Fixup.getKind() >= FirstLiteralRelocationKind)
119120
return true;
@@ -568,7 +569,7 @@ bool RISCVAsmBackend::evaluateTargetFixup(const MCAssembler &Asm,
568569
Value = Asm.getSymbolOffset(SA) + AUIPCTarget.getConstant();
569570
Value -= Asm.getFragmentOffset(*AUIPCDF) + AUIPCFixup->getOffset();
570571

571-
if (shouldForceRelocation(Asm, *AUIPCFixup, AUIPCTarget, STI)) {
572+
if (shouldForceRelocation(Asm, *AUIPCFixup, AUIPCTarget, Value, STI)) {
572573
WasForced = true;
573574
return false;
574575
}

‎llvm/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.h

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -65,7 +65,7 @@ class RISCVAsmBackend : public MCAsmBackend {
6565
createObjectTargetWriter() const override;
6666

6767
bool shouldForceRelocation(const MCAssembler &Asm, const MCFixup &Fixup,
68-
const MCValue &Target,
68+
const MCValue &Target, const uint64_t Value,
6969
const MCSubtargetInfo *STI) override;
7070

7171
bool fixupNeedsRelaxationAdvanced(const MCAssembler &Asm,

‎llvm/lib/Target/Sparc/MCTargetDesc/SparcAsmBackend.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -273,7 +273,7 @@ namespace {
273273
}
274274

275275
bool shouldForceRelocation(const MCAssembler &Asm, const MCFixup &Fixup,
276-
const MCValue &Target,
276+
const MCValue &Target, const uint64_t,
277277
const MCSubtargetInfo *STI) override {
278278
if (Fixup.getKind() >= FirstLiteralRelocationKind)
279279
return true;

‎llvm/lib/Target/SystemZ/MCTargetDesc/SystemZMCAsmBackend.cpp

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -116,7 +116,7 @@ class SystemZMCAsmBackend : public MCAsmBackend {
116116
std::optional<MCFixupKind> getFixupKind(StringRef Name) const override;
117117
const MCFixupKindInfo &getFixupKindInfo(MCFixupKind Kind) const override;
118118
bool shouldForceRelocation(const MCAssembler &Asm, const MCFixup &Fixup,
119-
const MCValue &Target,
119+
const MCValue &Target, const uint64_t Value,
120120
const MCSubtargetInfo *STI) override;
121121
void applyFixup(const MCAssembler &Asm, const MCFixup &Fixup,
122122
const MCValue &Target, MutableArrayRef<char> Data,
@@ -161,7 +161,7 @@ SystemZMCAsmBackend::getFixupKindInfo(MCFixupKind Kind) const {
161161

162162
bool SystemZMCAsmBackend::shouldForceRelocation(const MCAssembler &,
163163
const MCFixup &Fixup,
164-
const MCValue &,
164+
const MCValue &, const uint64_t,
165165
const MCSubtargetInfo *STI) {
166166
return Fixup.getKind() >= FirstLiteralRelocationKind;
167167
}

‎llvm/lib/Target/VE/MCTargetDesc/VEAsmBackend.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -132,7 +132,7 @@ class VEAsmBackend : public MCAsmBackend {
132132
}
133133

134134
bool shouldForceRelocation(const MCAssembler &Asm, const MCFixup &Fixup,
135-
const MCValue &Target,
135+
const MCValue &Target, const uint64_t,
136136
const MCSubtargetInfo *STI) override {
137137
switch ((VE::Fixups)Fixup.getKind()) {
138138
default:

‎llvm/lib/Target/X86/MCTargetDesc/X86AsmBackend.cpp

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -174,7 +174,7 @@ class X86AsmBackend : public MCAsmBackend {
174174
const MCFixupKindInfo &getFixupKindInfo(MCFixupKind Kind) const override;
175175

176176
bool shouldForceRelocation(const MCAssembler &Asm, const MCFixup &Fixup,
177-
const MCValue &Target,
177+
const MCValue &Target, const uint64_t Value,
178178
const MCSubtargetInfo *STI) override;
179179

180180
void applyFixup(const MCAssembler &Asm, const MCFixup &Fixup,
@@ -658,6 +658,7 @@ const MCFixupKindInfo &X86AsmBackend::getFixupKindInfo(MCFixupKind Kind) const {
658658

659659
bool X86AsmBackend::shouldForceRelocation(const MCAssembler &,
660660
const MCFixup &Fixup, const MCValue &,
661+
const uint64_t,
661662
const MCSubtargetInfo *STI) {
662663
return Fixup.getKind() >= FirstLiteralRelocationKind;
663664
}

‎llvm/test/CodeGen/AVR/branch-relaxation-long-backward.ll

Lines changed: 9 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,5 @@
11
; RUN: llc < %s -mtriple=avr -mcpu=attiny85 -filetype=obj -o - | llvm-objdump --mcpu=attiny85 -dr --no-show-raw-insn --no-leading-addr - | FileCheck --check-prefix=ATTINY85 %s
2-
; RUN: not llc < %s -mtriple=avr -mcpu=avr25 -filetype=obj -o - 2>&1 | FileCheck --check-prefix=AVR25 %s
2+
; RUN: llc < %s -mtriple=avr -mcpu=avr25 -filetype=obj -o - | llvm-objdump --mcpu=avr25 -dr --no-show-raw-insn --no-leading-addr - | FileCheck --check-prefix=AVR25 %s
33
; RUN: llc < %s -mtriple=avr -mcpu=avr3 -filetype=obj -o - | llvm-objdump --mcpu=avr3 -dr --no-show-raw-insn --no-leading-addr - | FileCheck --check-prefix=AVR3 %s
44

55
; ATTINY85: <main>:
@@ -10,7 +10,14 @@
1010
; ATTINY85: ldi r24, 0x3
1111
; ATTINY85-NEXT: ret
1212

13-
; AVR25: error: out of range branch target (expected an integer in the range -4096 to 4095)
13+
; AVR25: <main>:
14+
; AVR25-NEXT: andi r24, 0x1
15+
; AVR25: cpi r24, 0x0
16+
; AVR25-NEXT: breq .+2
17+
; AVR25-NEXT: rjmp .-2
18+
; AVR25-NEXT: R_AVR_13_PCREL .text+0x2
19+
; AVR25: ldi r24, 0x3
20+
; AVR25-NEXT: ret
1421

1522
; AVR3: <main>:
1623
; AVR3-NEXT: andi r24, 0x1

‎llvm/test/CodeGen/AVR/branch-relaxation-long-forward.ll

Lines changed: 9 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,5 @@
11
; RUN: llc < %s -mtriple=avr -mcpu=attiny85 -filetype=obj -o - | llvm-objdump --mcpu=attiny85 -dr --no-show-raw-insn --no-leading-addr - | FileCheck --check-prefix=ATTINY85 %s
2-
; RUN: not llc < %s -mtriple=avr -mcpu=avr25 -filetype=obj -o - 2>&1 | FileCheck --check-prefix=AVR25 %s
2+
; RUN: llc < %s -mtriple=avr -mcpu=avr25 -filetype=obj -o - | llvm-objdump --mcpu=avr25 -dr --no-show-raw-insn --no-leading-addr - | FileCheck --check-prefix=AVR25 %s
33
; RUN: llc < %s -mtriple=avr -mcpu=avr3 -filetype=obj -o - | llvm-objdump --mcpu=avr3 -dr --no-show-raw-insn --no-leading-addr - | FileCheck --check-prefix=AVR3 %s
44

55
; ATTINY85: <main>:
@@ -10,7 +10,14 @@
1010
; ATTINY85: ldi r24, 0x3
1111
; ATTINY85-NEXT: ret
1212

13-
; AVR25: error: out of range branch target (expected an integer in the range -4096 to 4095)
13+
; AVR25: <main>:
14+
; AVR25-NEXT: andi r24, 0x1
15+
; AVR25-NEXT: cpi r24, 0x0
16+
; AVR25-NEXT: brne .+2
17+
; AVR25-NEXT: rjmp .-2
18+
; AVR25-NEXT: R_AVR_13_PCREL .text+0x100c
19+
; AVR25: ldi r24, 0x3
20+
; AVR25-NEXT: ret
1421

1522
; AVR3: <main>:
1623
; AVR3-NEXT: andi r24, 0x1

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