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Author: jofrn

llvm/lib/CodeGen/LiveVariables.cpp

@@ -214,7 +214,6 @@ void LiveVariables::HandleVirtRegDef(Register Reg, MachineInstr &MI) {
 }
 
 /// FindLastPartialDef - Return the last partial def of the specified register.
-/// Also returns the sub-registers that're defined by the instruction.
 MachineInstr *LiveVariables::FindLastPartialDef(Register Reg) {
   unsigned LastDefDist = 0;
   MachineInstr *LastDef = nullptr;
@@ -250,12 +249,12 @@ void LiveVariables::HandlePhysRegUse(Register Reg, MachineInstr &MI) {
     // ...
     //    = EAX
     // All of the sub-registers must have been defined before the use of Reg!
-    MachineInstr *LastPartialDef = FindLastPartialDef(Reg);
+    //MachineInstr *LastPartialDef = FindLastPartialDef(Reg);
     // If LastPartialDef is NULL, it must be using a livein register.
-    if (LastPartialDef) {
-      LastPartialDef->addOperand(
-          MachineOperand::CreateReg(Reg, true /*IsDef*/, true /*IsImp*/));
-    }
+    //if (LastPartialDef) {
+      //LastPartialDef->addOperand(
+          //MachineOperand::CreateReg(Reg, true /*IsDef*/, true /*IsImp*/));
+    //}
   } else if (LastDef && !PhysRegUse[Reg.id()] &&
              !LastDef->findRegisterDefOperand(Reg, /*TRI=*/nullptr))
     // Last def defines the super register, add an implicit def of reg.

llvm/test/CodeGen/AMDGPU/fncall-implicitdef.ll

@@ -1,19 +1,18 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
-; RUN: llc -mtriple=amdgcn -mcpu=gfx900 -O1 %s -o - | FileCheck %s
+; RUN: llc -mtriple=amdgcn-amd-amdpal -mcpu=gfx900 -O1 %s -o - | FileCheck %s
 
 define amdgpu_ps <4 x float> @caller(ptr %ptr) {
 ; CHECK-LABEL: caller:
 ; CHECK:       ; %bb.0:
 ; CHECK-NEXT:    flat_load_dword v1, v[0:1]
+; CHECK-NEXT:    s_mov_b32 s5, fn@abs32@hi
+; CHECK-NEXT:    s_mov_b32 s4, fn@abs32@lo
+; CHECK-NEXT:    s_mov_b64 s[8:9], 0
 ; CHECK-NEXT:    s_mov_b32 s0, 0
 ; CHECK-NEXT:    s_mov_b32 s1, 0
 ; CHECK-NEXT:    s_mov_b32 s2, 0
-; CHECK-NEXT:    s_getpc_b64 s[4:5]
-; CHECK-NEXT:    s_add_u32 s4, s4, fn@rel32@lo+4
-; CHECK-NEXT:    s_addc_u32 s5, s5, fn@rel32@hi+12
-; CHECK-NEXT:    s_mov_b64 s[8:9], 36
-; CHECK-NEXT:    v_mov_b32_e32 v0, 0
 ; CHECK-NEXT:    s_mov_b32 s3, 0
+; CHECK-NEXT:    v_mov_b32_e32 v0, 0
 ; CHECK-NEXT:    v_mov_b32_e32 v2, 0
 ; CHECK-NEXT:    s_mov_b32 s32, 0
 ; CHECK-NEXT:    s_swappc_b64 s[30:31], s[4:5]

llvm/test/CodeGen/AMDGPU/livevars-implicitdef.mir

@@ -1,7 +1,7 @@
 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5
 # RUN: llc -mtriple=amdgcn --run-pass=livevars -o - %s | FileCheck %s
 ---
-# Check that super register is implicitly defined for an sgpr copy.
+# Check that super register is defined for an sgpr copy.
 name:            sgpr_copy
 tracksRegLiveness: true
 body:             |
@@ -12,19 +12,19 @@ body:             |
     ; CHECK-NEXT: $sgpr0 = COPY %sval
     ; CHECK-NEXT: $sgpr1 = COPY %sval
     ; CHECK-NEXT: $sgpr2 = COPY %sval
-    ; CHECK-NEXT: $sgpr3 = COPY killed %sval, implicit-def $sgpr0_sgpr1_sgpr2_sgpr3
-    ; CHECK-NEXT: dead $sgpr30_sgpr31 = COPY killed $sgpr0_sgpr1_sgpr2_sgpr3
+    ; CHECK-NEXT: $sgpr3 = COPY killed %sval
+    ; CHECK-NEXT: SI_RETURN implicit killed $sgpr0_sgpr1_sgpr2_sgpr3
     %sval:sreg_32 = S_MOV_B32 0
 
     $sgpr0 = COPY %sval
     $sgpr1 = COPY %sval
     $sgpr2 = COPY %sval
     $sgpr3 = COPY %sval
-    $sgpr30_sgpr31 = COPY $sgpr0_sgpr1_sgpr2_sgpr3
+    SI_RETURN implicit $sgpr0_sgpr1_sgpr2_sgpr3
 
 ...
 ---
-# Check that super register is implicitly defined for a vgpr vector copy.
+# Check that super register is defined for a vgpr vector copy.
 name:            vgpr_copy
 tracksRegLiveness: true
 body:             |
@@ -35,7 +35,7 @@ body:             |
     ; CHECK-NEXT: $vgpr0 = COPY %vval
     ; CHECK-NEXT: $vgpr1 = COPY %vval
     ; CHECK-NEXT: $vgpr2 = COPY %vval
-    ; CHECK-NEXT: $vgpr3 = COPY killed %vval, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3
+    ; CHECK-NEXT: $vgpr3 = COPY killed %vval
     ; CHECK-NEXT: dead [[COPY:%[0-9]+]]:vgpr_32 = COPY killed $vgpr0_vgpr1_vgpr2_vgpr3
     %vval:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
 
@@ -47,7 +47,7 @@ body:             |
 
 ...
 ---
-# Check that super register is implicitly defined when there is a hole.
+# Check that super register is defined when there is a hole.
 name:            sgpr_copy_hole
 tracksRegLiveness: true
 body:             |
@@ -56,18 +56,18 @@ body:             |
     ; CHECK: %sval:sreg_32 = S_MOV_B32 0
     ; CHECK-NEXT: $sgpr0 = COPY %sval
     ; CHECK-NEXT: $sgpr2 = COPY %sval
-    ; CHECK-NEXT: $sgpr3 = COPY killed %sval, implicit-def $sgpr0_sgpr1_sgpr2_sgpr3
-    ; CHECK-NEXT: dead $sgpr30_sgpr31 = COPY killed $sgpr0_sgpr1_sgpr2_sgpr3
+    ; CHECK-NEXT: $sgpr3 = COPY killed %sval
+    ; CHECK-NEXT: SI_RETURN implicit killed $sgpr0_sgpr1_sgpr2_sgpr3
     %sval:sreg_32 = S_MOV_B32 0
 
     $sgpr0 = COPY %sval
     $sgpr2 = COPY %sval
     $sgpr3 = COPY %sval
-    $sgpr30_sgpr31 = COPY $sgpr0_sgpr1_sgpr2_sgpr3
+    SI_RETURN implicit $sgpr0_sgpr1_sgpr2_sgpr3
 
 ...
 ---
-# Check that super register is imp-def when a pair interrupts the sequence.
+# Check that super register is defined when a pair interrupts the sequence.
 name:            vgpr_copy_pair
 tracksRegLiveness: true
 body:             |
@@ -76,8 +76,8 @@ body:             |
     ; CHECK: %vval:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
     ; CHECK-NEXT: $vgpr0 = COPY %vval
     ; CHECK-NEXT: $vgpr1 = COPY %vval
-    ; CHECK-NEXT: $vgpr2 = COPY %vval, implicit-def $vgpr1_vgpr2
-    ; CHECK-NEXT: $vgpr3 = COPY killed %vval, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3
+    ; CHECK-NEXT: $vgpr2 = COPY %vval
+    ; CHECK-NEXT: $vgpr3 = COPY killed %vval
     ; CHECK-NEXT: dead [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr1_vgpr2
     ; CHECK-NEXT: dead [[COPY1:%[0-9]+]]:vgpr_32 = COPY killed $vgpr0_vgpr1_vgpr2_vgpr3
     %vval:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
@@ -88,3 +88,4 @@ body:             |
     $vgpr3 = COPY %vval
     %0:vgpr_32 = COPY $vgpr1_vgpr2
     %1:vgpr_32 = COPY $vgpr0_vgpr1_vgpr2_vgpr3
+...