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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
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- ; RUN: llc -global-isel=1 -march =amdgcn -mcpu=gfx1100 -verify-machineinstrs < %s | FileCheck -check-prefix=GISEL-GFX11 %s
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- ; RUN: llc -global-isel=1 -march =amdgcn -mcpu=gfx1030 -verify-machineinstrs < %s | FileCheck -check-prefix=GISEL-GFX10 %s
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- ; RUN: llc -global-isel=0 -march =amdgcn -mcpu=gfx1100 -verify-machineinstrs < %s | FileCheck -check-prefix=DAGISEL-GFX11 %s
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- ; RUN: llc -global-isel=0 -march =amdgcn -mcpu=gfx1030 -verify-machineinstrs < %s | FileCheck -check-prefix=DAGISEL-GFX10 %s
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+ ; RUN: llc -global-isel=1 -mtriple =amdgcn--amdpal -mcpu=gfx1100 -verify-machineinstrs < %s | FileCheck -check-prefix=GISEL-GFX11 %s
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+ ; RUN: llc -global-isel=1 -mtriple =amdgcn--amdpal -mcpu=gfx1030 -verify-machineinstrs < %s | FileCheck -check-prefix=GISEL-GFX10 %s
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+ ; RUN: llc -global-isel=0 -mtriple =amdgcn--amdpal -mcpu=gfx1100 -verify-machineinstrs < %s | FileCheck -check-prefix=DAGISEL-GFX11 %s
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+ ; RUN: llc -global-isel=0 -mtriple =amdgcn--amdpal -mcpu=gfx1030 -verify-machineinstrs < %s | FileCheck -check-prefix=DAGISEL-GFX10 %s
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declare amdgpu_gfx void @use (...)
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- ; FIXME: The values of the counters are undefined on entry to amdgpu_cs_chain functions, so these waits are unnecessary.
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-
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define amdgpu_cs_chain void @amdgpu_cs_chain_no_stack ({ptr , i32 , <4 x i32 >} inreg %a , {ptr , i32 , <4 x i32 >} %b ) {
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; GISEL-GFX11-LABEL: amdgpu_cs_chain_no_stack:
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; GISEL-GFX11: ; %bb.0:
@@ -398,11 +396,14 @@ define amdgpu_cs void @cs_to_chain(<3 x i32> inreg %a, <3 x i32> %b) {
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;
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; GISEL-GFX10-LABEL: cs_to_chain:
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; GISEL-GFX10: ; %bb.0:
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- ; GISEL-GFX10-NEXT: s_mov_b32 s100, SCRATCH_RSRC_DWORD0
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- ; GISEL-GFX10-NEXT: s_mov_b32 s101, SCRATCH_RSRC_DWORD1
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- ; GISEL-GFX10-NEXT: s_mov_b32 s102, -1
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- ; GISEL-GFX10-NEXT: s_mov_b32 s103, 0x31c16000
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+ ; GISEL-GFX10-NEXT: s_getpc_b64 s[100:101]
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+ ; GISEL-GFX10-NEXT: s_mov_b32 s100, s0
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; GISEL-GFX10-NEXT: v_mov_b32_e32 v3, v0
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+ ; GISEL-GFX10-NEXT: s_load_dwordx4 s[100:103], s[100:101], 0x10
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+ ; GISEL-GFX10-NEXT: v_mov_b32_e32 v9, v1
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+ ; GISEL-GFX10-NEXT: v_mov_b32_e32 v10, v2
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+ ; GISEL-GFX10-NEXT: s_waitcnt lgkmcnt(0)
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+ ; GISEL-GFX10-NEXT: s_bitset0_b32 s103, 21
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; GISEL-GFX10-NEXT: s_add_u32 s100, s100, s3
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; GISEL-GFX10-NEXT: s_addc_u32 s101, s101, 0
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; GISEL-GFX10-NEXT: s_mov_b32 s3, s0
@@ -412,8 +413,6 @@ define amdgpu_cs void @cs_to_chain(<3 x i32> inreg %a, <3 x i32> %b) {
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; GISEL-GFX10-NEXT: s_mov_b64 s[48:49], s[100:101]
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; GISEL-GFX10-NEXT: s_mov_b32 s0, s3
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; GISEL-GFX10-NEXT: v_mov_b32_e32 v8, v3
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- ; GISEL-GFX10-NEXT: v_mov_b32_e32 v9, v1
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- ; GISEL-GFX10-NEXT: v_mov_b32_e32 v10, v2
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; GISEL-GFX10-NEXT: s_mov_b64 s[50:51], s[102:103]
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; GISEL-GFX10-NEXT: s_mov_b32 exec_lo, -1
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; GISEL-GFX10-NEXT: s_getpc_b64 s[4:5]
@@ -442,27 +441,28 @@ define amdgpu_cs void @cs_to_chain(<3 x i32> inreg %a, <3 x i32> %b) {
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;
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; DAGISEL-GFX10-LABEL: cs_to_chain:
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; DAGISEL-GFX10: ; %bb.0:
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- ; DAGISEL-GFX10-NEXT: s_mov_b32 s100, SCRATCH_RSRC_DWORD0
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- ; DAGISEL-GFX10-NEXT: s_mov_b32 s101, SCRATCH_RSRC_DWORD1
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- ; DAGISEL-GFX10-NEXT: s_mov_b32 s102, -1
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- ; DAGISEL-GFX10-NEXT: s_mov_b32 s103, 0x31c16000
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+ ; DAGISEL-GFX10-NEXT: s_getpc_b64 s[100:101]
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+ ; DAGISEL-GFX10-NEXT: s_mov_b32 s100, s0
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+ ; DAGISEL-GFX10-NEXT: v_mov_b32_e32 v3, v0
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+ ; DAGISEL-GFX10-NEXT: s_load_dwordx4 s[100:103], s[100:101], 0x10
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+ ; DAGISEL-GFX10-NEXT: v_mov_b32_e32 v9, v1
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+ ; DAGISEL-GFX10-NEXT: v_mov_b32_e32 v10, v2
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+ ; DAGISEL-GFX10-NEXT: s_waitcnt lgkmcnt(0)
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+ ; DAGISEL-GFX10-NEXT: s_bitset0_b32 s103, 21
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; DAGISEL-GFX10-NEXT: s_add_u32 s100, s100, s3
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; DAGISEL-GFX10-NEXT: s_addc_u32 s101, s101, 0
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; DAGISEL-GFX10-NEXT: s_getpc_b64 s[4:5]
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; DAGISEL-GFX10-NEXT: s_add_u32 s4, s4, chain_callee@gotpcrel32@lo+4
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; DAGISEL-GFX10-NEXT: s_addc_u32 s5, s5, chain_callee@gotpcrel32@hi+12
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- ; DAGISEL-GFX10-NEXT: v_mov_b32_e32 v3, v0
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- ; DAGISEL-GFX10-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x0
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; DAGISEL-GFX10-NEXT: s_mov_b32 s3, s0
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+ ; DAGISEL-GFX10-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x0
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; DAGISEL-GFX10-NEXT: ;;#ASMSTART
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; DAGISEL-GFX10-NEXT: s_nop
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; DAGISEL-GFX10-NEXT: ;;#ASMEND
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; DAGISEL-GFX10-NEXT: s_mov_b64 s[48:49], s[100:101]
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; DAGISEL-GFX10-NEXT: s_mov_b64 s[50:51], s[102:103]
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; DAGISEL-GFX10-NEXT: s_mov_b32 s0, s3
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; DAGISEL-GFX10-NEXT: v_mov_b32_e32 v8, v3
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- ; DAGISEL-GFX10-NEXT: v_mov_b32_e32 v9, v1
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- ; DAGISEL-GFX10-NEXT: v_mov_b32_e32 v10, v2
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; DAGISEL-GFX10-NEXT: s_mov_b32 exec_lo, -1
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; DAGISEL-GFX10-NEXT: s_waitcnt lgkmcnt(0)
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; DAGISEL-GFX10-NEXT: s_setpc_b64 s[4:5]
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